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Details

Name: vectorial_generator
Created: Mar 22, 2013
Updated: Mar 31, 2013
SVN Updated: Mar 30, 2014
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
Star1you like it: star it!

Other project properties

Category:Other
Language:VHDL
Development status:Stable
Additional info:Design done, FPGA proven
WishBone compliant: No
WishBone version: n/a
License: Others

Description

Vectorial generator:

-Interface: bit or bus
-Configuration: dynamic
-Applications: waveform generator, serial or parallel communication

Examples:

-Included in the own .vhd headfile

Configuration:

-It is necessary to adjust the following type which defines the input size (it affects to area resources):

SUBTYPE valores_vector IS INTEGER RANGE -1 TO nat_synth_65536'high; -- values range for each sample (always from -1)
TYPE vector_integer IS ARRAY (nat_synth_128'high DOWNTO 0) OF valores_vector; -- number of samples*2

where:

SUBTYPE nat_synth_65536 IS NATURAL RANGE 0 TO 65535;
SUBTYPE nat_synth_2048 IS NATURAL RANGE 0 TO 2047;
(...)
SUBTYPE nat_synth_16 IS NATURAL RANGE 0 TO 15;