OpenCores

Versatile memory controller :: Overview

Details

Name: versatile_mem_ctrl
Created: Jun 18, 2009
Updated: Nov 4, 2010
SVN Updated: Aug 11, 2011
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: reported / solved

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Other project properties

Category: Memory core
Language: Verilog
Development status: Planning
Additional info: none
WishBone compliant: Yes
WishBone version: n/a
License: LGPL

Overview

This is a modular memory controller supporting different types of memories. Initial design will have support for SDR SDRAM. Upcoming releases will add support for DDR SDRAM and possibly other variants as well

The design is built with the following modules

  1. Wishbone interface
  2. Dual async FIFO buffers
  3. Specific memory controller

Wishbone interface
The wishbone interface supports up to 8 independent interfaces where 4 are high priority real time ports

Dual async FIFO buffers
This design uses up to 8 outgoing and up to 8 incoming FIFO queues. On the outgoing channels control and data are transmitted and on the incoming read data is received. These are async FIFO supporting different clock domains for wishbine and memory side. FIFO implemenation is based on versatile_FIFO found on OpenCores.

SDR SDRAM controller
A state machine is used for communication to/from memories.

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