VLIW Processor
Project maintainers
Details
Name: vliw_processor
Created: Mar 31, 2018
Updated: Jul 25, 2019
SVN: No files checked in
Bugs: 1 reported / 0 solved
Created: Mar 31, 2018
Updated: Jul 25, 2019
SVN: No files checked in
Bugs: 1 reported / 0 solved
Star3you like it: star it!
Other project properties
Category:Processor
Language:VHDL
Development status:Alpha
Additional info:Design done
WishBone compliant: No
WishBone version: n/a
License: LGPL
Language:VHDL
Development status:Alpha
Additional info:Design done
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
Small core VLIW processor (proof of concept).
Static Multi Issue, based on a classic RISC pipeline.
Just the core, no interfaces are build yet, design is "WIP"
© copyright 1999-2018 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.