OpenCores

Asynchronous WISHBONE-compatible SDRAM controller :: Overview

Project maintainers

Details

Name: yadmc
Created: Aug 1, 2008
Updated: Aug 7, 2010
SVN Updated: Aug 7, 2010
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: reported / solved

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Other project properties

Category: Memory core
Language: Verilog
Development status: Stable
Additional info: none
WishBone compliant: No
WishBone version: n/a
License: GPL

Description

SUPERSEDED BY HPDMC.
Please do not ask me about this core! It is old and totally unsupported. HPDMC support, however, is available from the Milkymist-devel mailing list.

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