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carry_save_adder :: Overview



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Details

Name: carry_save_adder
Created: Jan 8, 2019
Updated: Jan 31, 2019
SVN: No files checked in
Bugs: 1 reported / 0 solved
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Other project properties

Category:Arithmetic core
Language:Verilog
Development status:Planning
Additional info:
WishBone compliant: No
WishBone version: n/a
License: LGPL

Description

This project is a 32-bit carry save adder. I initially made a 1-bit CSA and used two of those to make one CSA unit which can be cascaded to make n-bit adders, which is what has been done in this project.

The 1-bit CSA follows the following equations to compute the sum and carry:
sum: when a=b, s=cin
a!=b, s=!cin
cout: when a=b, cout=a
a!=b, cout=cin

Using this, the sum and carry can be computed faster.

When this 1-bit CSA is used to add n-bit numbers, it has to be used in two layers. When used in CSA units, it becomes simpler to read and to use for n-bit adder designs.

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