OpenCores

RISC_Core_I :: Overview



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Details

Name: risc_core_i
Created: Dec 29, 2001
Updated: Jan 17, 2002
SVN Updated: Mar 10, 2009
SVN: Browse
Latest version: download (might take a bit to start...)
Statistics: View
Bugs: 0 reported / 0 solved
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Other project properties

Category:Processor
Language:
Development status:Planning
Additional info:
WishBone compliant: No
WishBone version: n/a
License:

motivation

This project is my diploma paper i have written to gratuate at the University of Applied Sciences St.Gallen (Switzerland).

Description

This is a 4 stage 16-Bit RISC processor system on chip designed for a Xilinx Virtex FPGA. RAM and ROM both are blockRAM based.
Additionally, it is equiped with a parallel multiplier, a 8-Bit input and a 8-Bit output port.
This core wasn't designed for commercial but for educational use. RAM, ROM and the ports are designed with the schematic editor from Xilinx ISE. RAM and ROM are dual ported for an additional access over a pci bridge. The CPU is programmed in VHDL.

Remark

The papers are written in german.