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Name: zap
Created: Apr 30, 2017
Updated: Dec 12, 2018
SVN Updated: Sep 18, 2021
SVN: Browse
Latest version: download (might take a bit to start...)
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Bugs: 0 reported / 0 solved
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Other project properties

Category:Processor
Language:Verilog
Development status:Alpha
Additional info:Design done, Specification done
WishBone compliant: Yes
WishBone version: B.3
License: GPL

The ZAP ARM Processor (ARMv5T Compatible, FPGA Synthesizable Soft Processor)

Author : Revanth Kamaraj (revanth91kamaraj@gmail.com)

Introduction

The ZAP processor is a 10 stage pipelined processor for FPGA with support for cache and MMU (ARMv5T compliant).

Please note that the processor is not an ARM clone but a completely different RTL design, written from scratch (in FPGA compliant Verilog-2001), that can run ARM v5T binaries (both user and kernel code), hence, no particular ARMX number is specified.

This project was originally created for the ORCONF-2016 Student Design Contest.

ZAP is specifically designed to work with FPGAs. To keep the code generic across FPGA vendors, inference based coding style is followed.

Wishbone logo

Repos

This project is hosted on Github and Opencores.

GIT: https://github.com/krevanth/ZAP

SVN: https://opencores.org/projects/zap

Features

ZAP Processor (zap_top.v)

The ZAP core is a pipelined ATMv5T processor for FPGA.

PropertyDescription
HDLVerilog-2001
AuthorRevanth Kamaraj
ARM v5T ISA SupportFully compatible
Branch PredictorDirect mapped bimodal
Write BufferYes
Abort ModelBase Restored
Integrated v5T CP15Yes
External Coproc. BusNo
Cache Interface128-Bit custom interface
26-Bit SupportNo
L1 Code CacheDirect mapped virtual
L1 Data CacheDirect mapped virtual
Cache Write PolicyWriteback
L1 Code TLBDirect mapped
L1 Data TLBDirect mapped
Bus Interface32-bit Wishbone B3 Linear incrementing burst
Cache/TLB Lock SupportNo
CP15 Compliancev5T (No fine pages)
FCSE SupportYes
Cache Read Speed (Hit)320MB/s @ 80MHz CLK
Cache Write Speed(Hit)160MB/s @ 80MHz CLK
Cache Line Size16B
  • 10-stage pipeline design. Pipeline has extensive bypass network to resolve dependencies. Most operations execute at a rate of 1 operation per clock.
  • 2 write ports for the register file to allow LDR/STR with writeback to execute as a single instruction.
  • Instructions of ALU + Shift can allow execution of subsequent commands with dependencies if the subsequent command doesn't use the shifter. This is done by having a dual feedback network.
  • The core is specifically designed for use in FGPA and relies on FGPA inference to allow portability across FPGA vendors.

CPU Configuration (zap_top.v)

ParameterDefaultDescription
BP_ENTRIES1024Branch Predictor Settings. Predictor RAM depth. Must be 2^n and > 2
FIFO_DEPTH4Branch Predictor Settings. Command FIFO depth. Must be 2^n and > 2
STORE_BUFFER_DEPTH16Branch Predictor Settings. Depth of the store buffer. Must be 2^n and > 2
DATA_SECTION_TLB_ENTRIES4Data Cache/MMU Configuration. Section TLB entries. Must be 2^n (n > 0)
DATA_LPAGE_TLB_ENTRIES8Data Cache/MMU Configuration. Large page TLB entries. Must be 2^n (n > 0)
DATA_SPAGE_TLB_ENTRIES16Data Cache/MMU Configuration. Small page TLB entries. Must be 2^n (n > 0)
DATA_CACHE_SIZE1024Data Cache/MMU Configuration. Cache size in bytes. Must be at least 256B and 2^n
CODE_SECTION_TLB_ENTRIES4Instruction Cache/MMU Configuration. Section TLB entries. Must be 2^n (n > 0)
CODE_LPAGE_TLB_ENTRIES8Instruction Cache/MMU Configuration. Large page TLB entries. Must be 2^n (n > 0)
CODE_SPAGE_TLB_ENTRIES16Instruction Cache/MMU Configuration. Small page TLB entries. Must be 2^n (n > 0)
CODE_CACHE_SIZE1024Instruction Cache/MMU Configuration. Cache size in bytes. Must be at least 256B and 2^n

CPU IO Interface (zap_top.v)

Wishbone B3 compatible 32-bit bus.

DirSizePortDescription
inputi_clkClock
inputi_resetReset
inputi_irqInterrupt. Level Sensitive.
inputi_fiqFast Interrupt. Level Sensitive.
outputo_wb_cycWishbone B3 Signal
outputo_wb_stbWIshbone B3 signal
output31:0o_wb_adrWishbone B3 signal.
outputo_wb_weWishbone B3 signal.
output31:0o_wb_datWishbone B3 signal.
output3:0o_wb_selWishbone B3 signal.
output2:0o_wb_ctiWishbone B3 signal. Cycle Type Indicator (Supported modes: Incrementing Burst, End of Burst)
output1:0o_wb_bteWishbone B3 signal. Burst Type Indicator (Supported modes: Linear)
inputi_wb_ackWishbone B3 signal.
input31:0i_wb_datWishbone B3 signal.
outputo_wb_stb_nxtIGNORE THIS PORT. LEAVE OPEN.
outputo_wb_cyc_nxtIGNORE THIS PORT. LEAVE OPEN.
output31:0o_wb_adr_nxtIGNORE THIS PORT. LEAVE OPEN.

Directory Structure

    ├── LICENSE
    ├── makefile
    ├── README.md
    └── src
    
            ├── rtl
            │   └── cpu
            │       ├── zap_alu_main.v
            │       ├── zap_cache_fsm.v
            │       ├── zap_cache_tag_ram.v
            │       ├── zap_cache.v
            │       ├── zap_core.v
            │       ├── zap_cp15_cb.v
            │       ├── zap_decode_main.v
            │       ├── zap_decode.v
            │       ├── zap_decompile.v
            │       ├── zap_defines.vh
            │       ├── zap_fetch_main.v
            │       ├── zap_fifo.v
            │       ├── zap_functions.vh
            │       ├── zap_issue_main.v
            │       ├── zap_localparams.vh
            │       ├── zap_mem_inv_block.v
            │       ├── zap_memory_main.v
            │       ├── zap_predecode_compress.v
            │       ├── zap_predecode_coproc.v
            │       ├── zap_predecode_main.v
            │       ├── zap_predecode_mem_fsm.v
            │       ├── zap_ram_simple.v
            │       ├── zap_register_file.v
            │       ├── zap_shifter_main.v
            │       ├── zap_shifter_multiply.v
            │       ├── zap_shift_shifter.v
            │       ├── zap_sync_fifo.v
            │       ├── zap_thumb_decoder.v
            │       ├── zap_tlb_check.v
            │       ├── zap_tlb_fsm.v
            │       ├── zap_tlb.v
            │       ├── zap_top.v
            │       ├── zap_wb_adapter.v
            │       ├── zap_wb_merger.v
            │       └── zap_writeback.v
            ├── scripts
            │   ├── bin2vlog.pl
            │   ├── Config.cfg_template
            │   ├── makefile
            │   ├── run_sim.pl
            │   └── uart_input.bash
            ├── testbench
            │   ├── chip_top.v
            │   ├── External_IP
            │   │   └── uart16550
            │   │       ├── doc
            │   │       │   ├── CHANGES.txt
            │   │       │   ├── src
            │   │       │   │   └── UART_spec.doc
            │   │       │   └── UART_spec.pdf
            │   │       └── rtl
            │   │           ├── raminfr.v
            │   │           ├── uart_debug_if.v
            │   │           ├── uart_defines.v
            │   │           ├── uart_receiver.v
            │   │           ├── uart_regs.v
            │   │           ├── uart_rfifo.v
            │   │           ├── uart_sync_flops.v
            │   │           ├── uart_tfifo.v
            │   │           ├── uart_top.v
            │   │           ├── uart_transmitter.v
            │   │           └── uart_wb.v
            │   ├── ram.v
            │   ├── timer.v
            │   ├── uart_rx_logger.v
            │   ├── uart_tx_dumper.v
            │   ├── vic.v
            │   └── zap_tb.v
            └── ts
                ├── arm_test
                │   ├── arm_test.c
                │   ├── arm_test.ld
                │   ├── arm_test.s
                │   ├── Config.cfg
                │   ├── Description.txt
                │   └── makefile
                ├── factorial
                │   ├── Config.cfg
                │   ├── Description.txt
                │   ├── factorial.c
                │   ├── factorial.ld
                │   ├── factorial.s
                │   └── makefile
                ├── makefile
                ├── thumb_test
                │   ├── Config.cfg
                │   ├── Description.txt
                │   ├── linker.ld
                │   ├── main.c
                │   ├── makefile
                │   └── thumb.s
                └── uart
                    ├── Config.cfg
                    ├── Description.txt
                    ├── irq_handler.c
                    ├── main.c
                    ├── makefile
                    ├── uart.c
                    ├── uart.h
                    ├── uart.ld
                    └── uart.s

Run Sample Tests

Tested on Ubuntu 16.04 LTS/18.04 LTS

Let the variable $test_name hold the name of the test. See the src/ts directory for some basic tests pre-installed. Available test names are: factorial, arm_test, thumb_test, uart. New tests can be added using these as starting templates. Please note that these will be run on the SOC platform (chip_top) that consist of the ZAP processor, 2 x UARTs, a VIC and a timer.

sudo apt-get install gcc-arm-none-eabi binutils-arm-none-eabi gdb openocd 
sudo apt-get install iverilog gtkwave make perl xterm
cd $PROJ_ROOT/src/ts/$test_name # $PROJ_ROOT is the project directory.
make                            # Runs the test using IVerilog.
cd $PROJ_ROOT/obj/ts/$test_name # Switch to object folder.
gvim zap.log.gz                 # View the log file
gtkwave zap.vcd.gz              # Exists if selected by Config.cfg of that test case.

To use this processor in your SOC, instantiate this top level CPU module in your project: /src/rtl/cpu/zap_top.v

FPGA Timing Performance (Vivado, Retime Enabled)

FPGA PartSpeedCritical Path
xc7a35tiftg256-1L80MHzCache access

License

                GNU GENERAL PUBLIC LICENSE
                   Version 2, June 1991

Copyright (C) 1989, 1991 Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed.

                        Preamble

The licenses for most software are designed to take away your freedom to share and change it. By contrast, the GNU General Public License is intended to guarantee your freedom to share and change free software--to make sure the software is free for all its users. This General Public License applies to most of the Free Software Foundation's software and to any other program whose authors commit to using it. (Some other Free Software Foundation software is covered by the GNU Lesser General Public License instead.) You can apply it to your programs, too.

When we speak of free software, we are referring to freedom, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for this service if you wish), that you receive source code or can get it if you want it, that you can change the software or use pieces of it in new free programs; and that you know you can do these things.

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                GNU GENERAL PUBLIC LICENSE

TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION

  1. This License applies to any program or other work which contains a notice placed by the copyright holder saying it may be distributed under the terms of this General Public License. The "Program", below, refers to any such program or work, and a "work based on the Program" means either the Program or any derivative work under copyright law: that is to say, a work containing the Program or a portion of it, either verbatim or with modifications and/or translated into another language. (Hereinafter, translation is included without limitation in the term "modification".) Each licensee is addressed as "you".

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The hypothetical commands show w' andshow c' should show the appropriate parts of the General Public License. Of course, the commands you use may be called something other than show w' andshow c'; they could even be mouse-clicks or menu items--whatever suits your program.

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