OpenCores
Written in:
Stage:
License:
Wishbone version:

Arithmetic core 106

Prototype board 41

Communication controller 205

Coprocessor 7

Crypto core 75

DSP core 43

ECC core 23

Library 20

Memory core 48

ProjectFilesStatisticsStatusLicenseWishbone version
16-bit SDRAM ControllerYesStats
Done
Wishbone Compliant
GPL
2Q cacheYesStats
Done
LGPL
*8/16/32 bit SDRAM ControllerYesStats
Done
Wishbone Compliant
OpenCores Certified Project
GPL
Asynchronous WISHBONE-compatible SDRAM controllerYesStats
GPL
BRSFmnCEYesStats
Done
LGPL
CF InterleaverYesStats
CFI flash controllerYesStats
LGPL
DDR SDRAM Controller CoreYesStats
DDR2NoStats
LGPL
DDR2 mem controller for Digilent Genesys BoardYesStats
Wishbone Compliant
LGPL
DDR2 SDRAM ControllerYesStats
LGPL
DDR3 SDRAM controllerYesStats
Done
Has external files
LGPL
DDR3 Synthesizable BFMYesStats
Done
LGPL
DirectMappedCacheControllerYesStats
LGPL
DPSFmnCEYesStats
Done
LGPL
FAT32 ParserYesStats
LGPL
FIFO libraryYesStats
Others
Functional simulation models for commercially available RAMsYesStats
Done
LGPL
Generic FIFOYesStats
LGPL
Generic FIFOsYesStats
High Latency Bursting WISHBONE Wrapper for Xilinx MIGYesStats
Wishbone Compliant
LGPL
*High Performance Dynamic Memory ControllerYesStats
Done
OpenCores Certified Project
GPL
High Speed SDRAM Controller With Adaptive Bank Management and Command PipelineYesStats
Done
Memory coresYesStats
Memory sizerYesStats
Wishbone Compliant
NAND Controller (ONFI compliant)YesStats
Done
LGPL
OPB PSRAM ControllerYesStats
GPL
Open FreeListYesStats
LGPL
openHMCYesStats
Done
LGPL
Parametrized FIFO based on SRL16EYesStats
Done
LGPL
RAM libraryYesStats
Others
RAM_wbYesStats
Done
Wishbone Compliant
LGPL
Scratch DDR SDRAM ControllerYesStats
LGPL
Single Port ASRAMYesStats
Done
LGPL
sp_ram to 3p_ram WISHBONE WrapperYesStats
Wishbone Compliant
LGPL
srl_fifoYesStats
Done
LGPL
SSRAM interfaceYesStats
Stack designNoStats
GPL
synchronous_reset_fifo with testbenchYesStats
Done
LGPL
USB NAND Flash ReaderYesStats
LGPL
Versatile FIFOYesStats
LGPL
Versatile memory controllerYesStats
Wishbone Compliant
LGPL
wb_async_mem_bridgeYesStats
Wishbone Compliant
LGPL
wb_size_bridgeYesStats
Done
Wishbone Compliant
Wishbone DDR3 SDRAM ControllerYesStats
Wishbone Compliant
GPL
Wishbone FLASH Interface for Parallel FLASHYesStats
Done
Wishbone Compliant
LGPL
Wishbone Interface for SPI FLASHYesStats
LGPL
ZBT SRAM ControllerYesStats
Wishbone Compliant

Other 116

Processor 208

System on Chip 80

System on Module 2

System controller 22

Testing / Verification 35

Video controller 46

Uncategorized 94