`timescale 1ns / 1ns
/*///////////////////////////////////////
This is the 1 bit adder block.
This has been further implemented to form
the CSA_unit.
///////////////////////////////////////*/
module csa_1Bit(
    input a,
    input b,
    input c,
    output s,
    output cout
    );

wire x = a ^ b;

not(xbar, x);

and a1(s1, c, xbar);
and a2(s2, ~c, x);
or o1(s, s1, s2);

and a3(cout1, a, xbar);
and a4(cout2, c, x);
or o2(cout, cout1, cout2);

endmodule