URL https://opencores.org/ocsvn/uart2bus_testbench/uart2bus_testbench/trunk

Subversion Repositories uart2bus_testbench

[/] [uart2bus_testbench/] [further_enhancement] - Blame information for rev 12

Line No. Rev Author Line

Line No.	Rev	Author	Line
1	12	HanySalah	`Add general test that includes the all sequences and do general coverage driven verification`
2			`Add uvm command line parser to define the type of the simulation either coverage driven or simulation based`
3			`Add python script to run the simulation`

HanySalah

Add general test that includes the all sequences and do general coverage driven verification

Add uvm command line parser to define the type of the simulation either coverage driven or simulation based

Add python script to run the simulation