URL https://opencores.org/ocsvn/reed_solomon_decoder/reed_solomon_decoder/trunk

Subversion Repositories reed_solomon_decoder

[/] [reed_solomon_decoder/] [trunk/] - Rev 5

Rev	Log message	Author	Age	Path
5	Updated documentation	vk.semiconductors	5127d 19h	/reed_solomon_decoder/trunk/
4	Added simulation & synthesis scripts.	vk.semiconductors	5127d 20h	/reed_solomon_decoder/trunk/
3	* Read_me.txt file is added, the file contains the description of the simulation files.	vk.semiconductors	5394d 01h	/reed_solomon_decoder/trunk/
2	Initial commit of Reed Solomon Decoder Verilog core (204,188,8) corrects up to 8 errors per block Pipelined and verfied on FPGA	aelmahmoudy	5407d 00h	/reed_solomon_decoder/trunk/
1	The project was created and the structure was created	root	5407d 01h	/reed_solomon_decoder/trunk/