URL
https://opencores.org/ocsvn/nand_controller/nand_controller/trunk
Error creating feed file, please check write permissions.
nand_controller
WebSVN RSS feed - nand_controller
https://opencores.org/websvn//websvn/listing?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&
Thu, 28 Mar 2024 18:22:17 +0100
FeedCreator 1.7.2
-
Fixed r/w trigger in direct operations
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=19
<div><strong>Rev 19 - pradd</strong> (1 file(s) modified)</div><div>Fixed r/w trigger in direct operations</div>~ /nand_controller/trunk/VHDL/nand_master.vhd<br />
pradd
Thu, 30 Jun 2016 08:25:41 +0100
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=19
-
Fixed r/w trigger in direct operations
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=18
<div><strong>Rev 18 - pradd</strong> (1 file(s) modified)</div><div>Fixed r/w trigger in direct operations</div>~ /nand_controller/trunk/VHDL/nand_master.vhd<br />
pradd
Thu, 30 Jun 2016 08:24:52 +0100
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=18
-
Added bypass commands to the controller's interface
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=16
<div><strong>Rev 16 - pradd</strong> (4 file(s) modified)</div><div>Added bypass commands to the controller's interface</div>+ /nand_controller/trunk/Doc/ONFI NAND Controller Avalon MM.docx<br />+ /nand_controller/trunk/Doc/ONFI NAND Controller Avalon MM.pdf<br />~ /nand_controller/trunk/VHDL/nand_master.vhd<br />~ /nand_controller/trunk/VHDL/onfi_package.vhd<br />
pradd
Wed, 29 Jun 2016 22:30:41 +0100
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=16
-
Added Avalon Memory Mapped slave interface
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=15
<div><strong>Rev 15 - pradd</strong> (1 file(s) modified)</div><div>Added Avalon Memory Mapped slave interface</div>+ /nand_controller/trunk/VHDL/nand_avalon.vhd<br />
pradd
Fri, 18 Sep 2015 20:50:47 +0100
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=15
-
Fixed READ_PAGE initial delay bug. Now the first byte is ...
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=14
<div><strong>Rev 14 - pradd</strong> (1 file(s) modified)</div><div>Fixed READ_PAGE initial delay bug. Now the first byte is ...</div>~ /nand_controller/trunk/VHDL/nand_master.vhd<br />
pradd
Fri, 18 Sep 2015 20:47:44 +0100
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=14
-
Fixed delay handling in M_NAND_READ_PARAM_PAGE
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=13
<div><strong>Rev 13 - pradd</strong> (1 file(s) modified)</div><div>Fixed delay handling in M_NAND_READ_PARAM_PAGE</div>~ /nand_controller/trunk/VHDL/nand_master.vhd<br />
pradd
Thu, 17 Sep 2015 23:57:04 +0100
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=13
-
Minor changes to nand_master.vhd and onfi_package.vhd.
Added documentation.
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=12
<div><strong>Rev 12 - pradd</strong> (5 file(s) modified)</div><div>Minor changes to nand_master.vhd and onfi_package.vhd.<br />
Added documentation.</div>+ /nand_controller/trunk/Doc<br />+ /nand_controller/trunk/Doc/NAND Controller.docx<br />+ /nand_controller/trunk/Doc/NAND Controller.pdf<br />~ /nand_controller/trunk/VHDL/nand_master.vhd<br />~ /nand_controller/trunk/VHDL/onfi_package.vhd<br />
pradd
Sat, 29 Aug 2015 23:20:42 +0100
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=12
-
Changed io_unit data_reg assignment timing.
Added testbench.vhd.
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=11
<div><strong>Rev 11 - pradd</strong> (2 file(s) modified)</div><div>Changed io_unit data_reg assignment timing.<br />
<br />
Added testbench.vhd.</div>~ /nand_controller/trunk/VHDL/io_unit.vhd<br />+ /nand_controller/trunk/VHDL/testbench.vhd<br />
pradd
Wed, 26 Aug 2015 20:39:24 +0100
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=11
-
Minor fixes.
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=10
<div><strong>Rev 10 - pradd</strong> (1 file(s) modified)</div><div>Minor fixes.</div>~ /nand_controller/trunk/VHDL/nand_master.vhd<br />
pradd
Wed, 26 Aug 2015 00:48:28 +0100
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=10
-
Submission of actually working code :-)
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=9
<div><strong>Rev 9 - pradd</strong> (7 file(s) modified)</div><div>Submission of actually working code :-)</div>+ /nand_controller/trunk/VHDL/io_unit.vhd<br />+ /nand_controller/trunk/VHDL/latch_unit.vhd<br />- /nand_controller/trunk/VHDL/nand_ctrl.vhd<br />- /nand_controller/trunk/VHDL/nand_interface.vhd<br />+ /nand_controller/trunk/VHDL/nand_master.vhd<br />- /nand_controller/trunk/VHDL/nand_stuff.vhd<br />+ /nand_controller/trunk/VHDL/onfi_package.vhd<br />
pradd
Tue, 25 Aug 2015 17:44:37 +0100
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=9
-
Initial check in of nand_ctrl.vhd - this file implements the ...
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=8
<div><strong>Rev 8 - pradd</strong> (1 file(s) modified)</div><div>Initial check in of nand_ctrl.vhd - this file implements the ...</div>+ /nand_controller/trunk/VHDL/nand_ctrl.vhd<br />
pradd
Thu, 28 May 2015 22:23:28 +0100
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=8
-
Added a note on clock_cycle generic signal
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=7
<div><strong>Rev 7 - pradd</strong> (1 file(s) modified)</div><div>Added a note on clock_cycle generic signal</div>~ /nand_controller/trunk/VHDL/nand_stuff.vhd<br />
pradd
Thu, 28 May 2015 19:47:01 +0100
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=7
-
Initial check in of 'NAND_STUFF' package.
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=6
<div><strong>Rev 6 - pradd</strong> (1 file(s) modified)</div><div>Initial check in of 'NAND_STUFF' package.</div>+ /nand_controller/trunk/VHDL/nand_stuff.vhd<br />
pradd
Wed, 27 May 2015 23:49:21 +0100
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=6
-
Added physical connection table for 'nand_io' bits/pins
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=5
<div><strong>Rev 5 - pradd</strong> (1 file(s) modified)</div><div>Added physical connection table for 'nand_io' bits/pins</div>~ /nand_controller/trunk/VHDL/nand_interface.vhd<br />
pradd
Wed, 27 May 2015 23:45:34 +0100
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=5
-
Added some explanation regarding x8 and x16 NAND devices pinout ...
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=4
<div><strong>Rev 4 - pradd</strong> (1 file(s) modified)</div><div>Added some explanation regarding x8 and x16 NAND devices pinout ...</div>~ /nand_controller/trunk/VHDL/nand_interface.vhd<br />
pradd
Wed, 27 May 2015 23:30:23 +0100
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=4
-
Added CE2# - Chip Enable for second die on 8Gbit ...
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=3
<div><strong>Rev 3 - pradd</strong> (1 file(s) modified)</div><div>Added CE2# - Chip Enable for second die on 8Gbit ...</div>~ /nand_controller/trunk/VHDL/nand_interface.vhd<br />
pradd
Wed, 27 May 2015 22:48:06 +0100
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=3
-
Initial check-in:
nand_interface.vhd - contains implementation of simplistic NAND Flash ...
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=2
<div><strong>Rev 2 - pradd</strong> (2 file(s) modified)</div><div>Initial check-in:<br />
nand_interface.vhd - contains implementation of simplistic NAND Flash interface. ...</div>+ /nand_controller/trunk/VHDL<br />+ /nand_controller/trunk/VHDL/nand_interface.vhd<br />
pradd
Wed, 27 May 2015 19:46:29 +0100
https://opencores.org/websvn//websvn/revision?repname=nand_controller&path=%2Fnand_controller%2Ftrunk%2FVHDL%2F&rev=2
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.