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//////////////////////////////////////////////////////////////////////
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//// ////
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//// 8051 alu carry select module ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// http://www.opencores.org/cores/8051/ ////
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//// ////
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//// Description ////
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//// Multiplexer wiht whitch we select carry in alu ////
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//// ////
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//// To Do: ////
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//// nothing ////
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//// ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// ver: 1
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//
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// synopsys translate_off
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`include "oc8051_timescale.v"
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// synopsys translate_on
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`include "oc8051_defines.v"
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module oc8051_cy_select (cy_sel, cy_in, data_in, data_out);
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//
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// cy_sel (in) carry select, from decoder (see defines.v) [oc8051_decoder.cy_sel -r]
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// cy_in (in) carry input [oc8051_psw.data_out[7] ]
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// data_in (in) ram data input [oc8051_ram_sel.bit_out]
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// data_out (out) data output [oc8051_alu.srcCy]
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//
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input [1:0] cy_sel;
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input cy_in, data_in;
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output data_out;
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reg data_out;
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always @(cy_sel or cy_in or data_in)
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begin
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case (cy_sel)
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`OC8051_CY_0: data_out = 1'b0;
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`OC8051_CY_PSW: data_out = cy_in;
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`OC8051_CY_RAM: data_out = data_in;
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`OC8051_CY_1: data_out = 1'b1;
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default: data_out = 1'bx;
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endcase
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end
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endmodule
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