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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_decoder.v] - Blame information for rev 40

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1 40 simont
////////////////////////////////////////////////////////////////////// 
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////                                                              ////
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////  8051 core decoder                                           ////
4
////                                                              ////
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////  This file is part of the 8051 cores project                 ////
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////  http://www.opencores.org/cores/8051/                        ////
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////                                                              ////
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////  Description                                                 ////
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////   Main 8051 core module. decodes instruction and creates     ////
10
////   control sigals.                                            ////
11
////                                                              ////
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////  To Do:                                                      ////
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////   optimize state machine, especially IDS ASS and AS3         ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Simon Teran, simont@opencores.org                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
24
//// removed from the file and that any derivative work contains  ////
25
//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
28
//// and/or modify it under the terms of the GNU Lesser General   ////
29
//// Public License as published by the Free Software Foundation; ////
30
//// either version 2.1 of the License, or (at your option) any   ////
31
//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37
//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
41
//// from http://www.opencores.org/lgpl.shtml                     ////
42
////                                                              ////
43
//////////////////////////////////////////////////////////////////////
44
//
45
// ver: 1
46
//
47
 
48
// synopsys translate_off
49
`include "oc8051_timescale.v"
50
// synopsys translate_on
51
 
52
`include "oc8051_defines.v"
53
 
54
 
55
 
56
module oc8051_decoder (clk, rst, op_in, eq, ram_rd_sel, ram_wr_sel, bit_addr,
57
wr, src_sel1, src_sel2, src_sel3, alu_op, psw_set, cy_sel, imm_sel, pc_wr,
58
pc_sel, comp_sel, rom_addr_sel, ext_addr_sel, wad2, rd, we_o, reti,
59
rmw, stb_o, ack_i, wr_xaddr);
60
//
61
// clk          (in)  clock
62
// rst          (in)  reset
63
// op_in        (in)  operation code [oc8051_op_select.op1]
64
// eq           (in)  compare result [oc8051_comp.eq]
65
// ram_rd_sel   (out) select, whitch address will be send to ram for read [oc8051_ram_rd_sel.sel, oc8051_sp.ram_rd_sel]
66
// ram_wr_sel   (out) select, whitch address will be send to ram for write [oc8051_ram_wr_sel.sel -r, oc8051_sp.ram_wr_sel -r]
67
// wr           (out) write - if 1 then we will write to ram [oc8051_ram_top.wr -r, oc8051_acc.wr -r, oc8051_b_register.wr -r, oc8051_sp.wr-r, oc8051_dptr.wr -r, oc8051_psw.wr -r, oc8051_indi_addr.wr -r, oc8051_ports.wr -r]
68
// src_sel1     (out) select alu source 1 [oc8051_alu_src1_sel.sel -r]
69
// src_sel2     (out) select alu source 2 [oc8051_alu_src2_sel.sel -r]
70
// src_sel3     (out) select alu source 3 [oc8051_alu_src3_sel.sel -r]
71
// alu_op       (out) alu operation [oc8051_alu.op_code -r]
72
// psw_set      (out) will we remember cy, ac, ov from alu [oc8051_psw.set -r]
73
// cy_sel       (out) carry in alu select [oc8051_cy_select.cy_sel -r]
74
// comp_sel     (out) compare source select [oc8051_comp.sel]
75
// bit_addr     (out) if instruction is bit addresable [oc8051_ram_top.bit_addr -r, oc8051_acc.wr_bit -r, oc8051_b_register.wr_bit-r, oc8051_sp.wr_bit -r, oc8051_dptr.wr_bit -r, oc8051_psw.wr_bit -r, oc8051_indi_addr.wr_bit -r, oc8051_ports.wr_bit -r]
76
// wad2         (out) write acc from destination 2 [oc8051_acc.wad2 -r]
77
// imm_sel      (out) immediate select [oc8051_immediate_sel.sel -r]
78
// pc_wr        (out) pc write [oc8051_pc.wr]
79
// pc_sel       (out) pc select [oc8051_pc.pc_wr_sel]
80
// rom_addr_sel (out) rom address select (alu destination or pc) [oc8051_rom_addr_sel.select]
81
// ext_addr_sel (out) external address select (dptr or Ri) [oc8051_ext_addr_sel.select]
82
// rd           (out) read from rom [oc8051_pc.rd, oc8051_op_select.rd]
83
// we_o         (out) write to external rom [pin]
84
// reti         (out) return from interrupt [pin]
85
// rmw          (out) read modify write feature [oc8051_ports.rmw]
86
//
87
 
88
input clk, rst, eq, ack_i;
89
input [7:0] op_in;
90
 
91
output wr, reti, we_o, bit_addr, src_sel3, rom_addr_sel, ext_addr_sel,
92
pc_wr, wad2, rmw, stb_o, wr_xaddr;
93
output [1:0] ram_rd_sel, src_sel1, src_sel2, psw_set, cy_sel, pc_sel, comp_sel;
94
output [2:0] ram_wr_sel, imm_sel;
95
output [3:0] alu_op;
96
output rd;
97
 
98
reg reti, write_x, rmw, stb_buff, we_buff;
99
reg wr,  bit_addr, src_sel3, rom_addr_sel, ext_addr_sel, pc_wr, wad2, stb, stbw, wr_xaddr;
100
reg [1:0] comp_sel, psw_set, ram_rd_sel, src_sel1, src_sel2, pc_sel, cy_sel;
101
reg [3:0] alu_op;
102
reg [2:0] ram_wr_sel, imm_sel;
103
 
104
//
105
// state        if 2'b00 then normal execution, sle instructin that need more than one clock
106
// op           instruction buffer
107
reg [1:0] state;
108
reg [7:0] op;
109
 
110
//
111
// if state = 2'b00 then read nex instruction
112
assign rd = !state[0] && !state[1] && !stb_o;
113
 
114
assign stb_o = stb_buff || stbw;
115
assign we_o = we_buff;
116
//assign we_o = write_x || we_buff;
117
 
118
//
119
// main block
120
// case of instruction set control signals
121
always @(op_in or eq or state or op or stb_o)
122
begin
123
  if (stb_o) begin
124
          ram_rd_sel = `OC8051_RRS_DC;
125
          ram_wr_sel = `OC8051_RWS_DC;
126
          src_sel1 = `OC8051_ASS_DC;
127
          src_sel2 = `OC8051_ASS_DC;
128
          alu_op = `OC8051_ALU_NOP;
129
          imm_sel = `OC8051_IDS_DC;
130
          wr = 1'b0;
131
          psw_set = `OC8051_PS_NOT;
132
          cy_sel = `OC8051_CY_0;
133
          pc_wr = `OC8051_PCW_N;
134
          pc_sel = `OC8051_PIS_DC;
135
          src_sel3 = `OC8051_AS3_DC;
136
          comp_sel = `OC8051_CSS_DC;
137
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
138
          wad2 = `OC8051_WAD_N;
139
          rom_addr_sel = `OC8051_RAS_PC;
140
  end else begin
141
    case (state)
142
      2'b01: begin
143
    casex (op)
144
      `OC8051_ACALL :begin
145
          ram_rd_sel = `OC8051_RRS_DC;
146
          ram_wr_sel = `OC8051_RWS_SP;
147
          src_sel1 = `OC8051_ASS_IMM;
148
          src_sel2 = `OC8051_ASS_DC;
149
          alu_op = `OC8051_ALU_NOP;
150
          imm_sel = `OC8051_IDS_PCH;
151
          wr = 1'b1;
152
          psw_set = `OC8051_PS_NOT;
153
          cy_sel = `OC8051_CY_0;
154
          pc_wr = `OC8051_PCW_N;
155
          pc_sel = `OC8051_PIS_DC;
156
          comp_sel = `OC8051_CSS_DC;
157
          src_sel3 = `OC8051_AS3_DC;
158
          comp_sel = `OC8051_CSS_DC;
159
          rmw = `OC8051_RMW_N;
160
          bit_addr = 1'b0;
161
          wad2 = `OC8051_WAD_N;
162
          rom_addr_sel = `OC8051_RAS_PC;
163
 
164
 
165
        end
166
      `OC8051_AJMP : begin
167
          ram_rd_sel = `OC8051_RRS_DC;
168
          ram_wr_sel = `OC8051_RWS_DC;
169
          src_sel1 = `OC8051_ASS_DC;
170
          src_sel2 = `OC8051_ASS_DC;
171
          alu_op = `OC8051_ALU_NOP;
172
          imm_sel = `OC8051_IDS_DC;
173
          wr = 1'b0;
174
          psw_set = `OC8051_PS_NOT;
175
          cy_sel = `OC8051_CY_0;
176
          pc_wr = `OC8051_PCW_N;
177
          pc_sel = `OC8051_PIS_DC;
178
          comp_sel = `OC8051_CSS_DC;
179
          src_sel3 = `OC8051_AS3_DC;
180
          comp_sel = `OC8051_CSS_DC;
181
          rmw = `OC8051_RMW_N;
182
          bit_addr = 1'b0;
183
          wad2 = `OC8051_WAD_N;
184
          rom_addr_sel = `OC8051_RAS_PC;
185
 
186
 
187
        end
188
      `OC8051_LCALL :begin
189
          ram_rd_sel = `OC8051_RRS_DC;
190
          ram_wr_sel = `OC8051_RWS_SP;
191
          src_sel1 = `OC8051_ASS_IMM;
192
          src_sel2 = `OC8051_ASS_DC;
193
          alu_op = `OC8051_ALU_NOP;
194
          imm_sel = `OC8051_IDS_PCH;
195
          wr = 1'b1;
196
          psw_set = `OC8051_PS_NOT;
197
          cy_sel = `OC8051_CY_0;
198
          pc_wr = `OC8051_PCW_N;
199
          pc_sel = `OC8051_PIS_DC;
200
          comp_sel = `OC8051_CSS_DC;
201
          src_sel3 = `OC8051_AS3_DC;
202
          comp_sel = `OC8051_CSS_DC;
203
          rmw = `OC8051_RMW_N;
204
          bit_addr = 1'b0;
205
          wad2 = `OC8051_WAD_N;
206
          rom_addr_sel = `OC8051_RAS_PC;
207
 
208
 
209
        end
210
      `OC8051_MOVC_DP :begin
211
          ram_rd_sel = `OC8051_RRS_DC;
212
          ram_wr_sel = `OC8051_RWS_ACC;
213
          src_sel1 = `OC8051_ASS_IMM;
214
          src_sel2 = `OC8051_ASS_DC;
215
          alu_op = `OC8051_ALU_NOP;
216
          wr = 1'b1;
217
          psw_set = `OC8051_PS_NOT;
218
          cy_sel = `OC8051_CY_0;
219
          pc_wr = `OC8051_PCW_N;
220
          pc_sel = `OC8051_PIS_DC;
221
          imm_sel = `OC8051_IDS_OP1;
222
          src_sel3 = `OC8051_AS3_DP;
223
          comp_sel = `OC8051_CSS_DC;
224
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
225
          wad2 = `OC8051_WAD_N;
226
          rom_addr_sel = `OC8051_RAS_PC;
227
 
228
 
229
        end
230
      `OC8051_MOVC_PC :begin
231
          ram_rd_sel = `OC8051_RRS_DC;
232
          ram_wr_sel = `OC8051_RWS_ACC;
233
          src_sel1 = `OC8051_ASS_IMM;
234
          src_sel2 = `OC8051_ASS_DC;
235
          alu_op = `OC8051_ALU_NOP;
236
          wr = 1'b1;
237
          psw_set = `OC8051_PS_NOT;
238
          cy_sel = `OC8051_CY_0;
239
          pc_wr = `OC8051_PCW_N;
240
          pc_sel = `OC8051_PIS_DC;
241
          imm_sel = `OC8051_IDS_OP1;
242
          src_sel3 = `OC8051_AS3_PC;
243
          comp_sel = `OC8051_CSS_DC;
244
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
245
          wad2 = `OC8051_WAD_N;
246
          rom_addr_sel = `OC8051_RAS_PC;
247
 
248
        end
249
      `OC8051_DIV : begin
250
          ram_rd_sel = `OC8051_RRS_D;
251
          ram_wr_sel = `OC8051_RWS_B;
252
          src_sel1 = `OC8051_ASS_ACC;
253
          src_sel2 = `OC8051_ASS_RAM;
254
          alu_op = `OC8051_ALU_DIV;
255
          wr = 1'b1;
256
          psw_set = `OC8051_PS_OV;
257
          cy_sel = `OC8051_CY_0;
258
          pc_wr = `OC8051_PCW_N;
259
          pc_sel = `OC8051_PIS_DC;
260
          imm_sel = `OC8051_IDS_DC;
261
          src_sel3 = `OC8051_AS3_DC;
262
          comp_sel = `OC8051_CSS_DC;
263
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
264
          wad2 = `OC8051_WAD_Y;
265
          rom_addr_sel = `OC8051_RAS_PC;
266
 
267
        end
268
      `OC8051_MUL : begin
269
          ram_rd_sel = `OC8051_RRS_D;
270
          ram_wr_sel = `OC8051_RWS_B;
271
          src_sel1 = `OC8051_ASS_ACC;
272
          src_sel2 = `OC8051_ASS_RAM;
273
          alu_op = `OC8051_ALU_MUL;
274
          wr = 1'b1;
275
          psw_set = `OC8051_PS_OV;
276
          cy_sel = `OC8051_CY_0;
277
          pc_wr = `OC8051_PCW_N;
278
          pc_sel = `OC8051_PIS_DC;
279
          imm_sel = `OC8051_IDS_DC;
280
          src_sel3 = `OC8051_AS3_DC;
281
          comp_sel = `OC8051_CSS_DC;
282
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
283
          wad2 = `OC8051_WAD_Y;
284
          rom_addr_sel = `OC8051_RAS_PC;
285
 
286
        end
287
      default begin
288
          ram_rd_sel = `OC8051_RRS_DC;
289
          ram_wr_sel = `OC8051_RWS_DC;
290
          src_sel1 = `OC8051_ASS_DC;
291
          src_sel2 = `OC8051_ASS_DC;
292
          alu_op = `OC8051_ALU_NOP;
293
          wr = 1'b0;
294
          psw_set = `OC8051_PS_NOT;
295
          cy_sel = `OC8051_CY_0;
296
          pc_wr = `OC8051_PCW_N;
297
          pc_sel = `OC8051_PIS_DC;
298
          imm_sel = `OC8051_IDS_DC;
299
          src_sel3 = `OC8051_AS3_DC;
300
          comp_sel = `OC8051_CSS_DC;
301
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
302
          wad2 = `OC8051_WAD_N;
303
          rom_addr_sel = `OC8051_RAS_PC;
304
 
305
 
306
      end
307
    endcase
308
    end
309
    2'b10:
310
    casex (op)
311
      `OC8051_CJNE_R : begin
312
          ram_rd_sel = `OC8051_RRS_DC;
313
          ram_wr_sel = `OC8051_RWS_DC;
314
          src_sel1 = `OC8051_ASS_DC;
315
          src_sel2 = `OC8051_ASS_DC;
316
          alu_op = `OC8051_ALU_NOP;
317
          wr = 1'b0;
318
          psw_set = `OC8051_PS_NOT;
319
          cy_sel = `OC8051_CY_0;
320
          pc_wr = !eq;
321
          pc_sel = `OC8051_PIS_ALU;
322
          imm_sel = `OC8051_IDS_DC;
323
          src_sel3 = `OC8051_AS3_DC;
324
          comp_sel = `OC8051_CSS_DES;
325
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
326
          wad2 = `OC8051_WAD_N;
327
          rom_addr_sel = `OC8051_RAS_PC;
328
 
329
 
330
        end
331
      `OC8051_CJNE_I : begin
332
          ram_rd_sel = `OC8051_RRS_DC;
333
          ram_wr_sel = `OC8051_RWS_DC;
334
          src_sel1 = `OC8051_ASS_DC;
335
          src_sel2 = `OC8051_ASS_DC;
336
          alu_op = `OC8051_ALU_NOP;
337
          wr = 1'b0;
338
          psw_set = `OC8051_PS_NOT;
339
          cy_sel = `OC8051_CY_0;
340
          pc_wr = !eq;
341
          pc_sel = `OC8051_PIS_ALU;
342
          imm_sel = `OC8051_IDS_DC;
343
          src_sel3 = `OC8051_AS3_DC;
344
          comp_sel = `OC8051_CSS_DES;
345
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
346
          wad2 = `OC8051_WAD_N;
347
          rom_addr_sel = `OC8051_RAS_PC;
348
 
349
 
350
        end
351
      `OC8051_CJNE_D : begin
352
          ram_rd_sel = `OC8051_RRS_DC;
353
          ram_wr_sel = `OC8051_RWS_DC;
354
          src_sel1 = `OC8051_ASS_DC;
355
          src_sel2 = `OC8051_ASS_DC;
356
          alu_op = `OC8051_ALU_NOP;
357
          wr = 1'b0;
358
          psw_set = `OC8051_PS_NOT;
359
          cy_sel = `OC8051_CY_0;
360
          pc_wr = !eq;
361
          pc_sel = `OC8051_PIS_ALU;
362
          imm_sel = `OC8051_IDS_DC;
363
          src_sel3 = `OC8051_AS3_DC;
364
          comp_sel = `OC8051_CSS_DES;
365
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
366
          wad2 = `OC8051_WAD_N;
367
          rom_addr_sel = `OC8051_RAS_PC;
368
 
369
 
370
        end
371
      `OC8051_CJNE_C : begin
372
          ram_rd_sel = `OC8051_RRS_DC;
373
          ram_wr_sel = `OC8051_RWS_DC;
374
          src_sel1 = `OC8051_ASS_DC;
375
          src_sel2 = `OC8051_ASS_DC;
376
          alu_op = `OC8051_ALU_NOP;
377
          wr = 1'b0;
378
          psw_set = `OC8051_PS_NOT;
379
          cy_sel = `OC8051_CY_0;
380
          pc_wr = !eq;
381
          pc_sel = `OC8051_PIS_ALU;
382
          imm_sel = `OC8051_IDS_DC;
383
          src_sel3 = `OC8051_AS3_DC;
384
          comp_sel = `OC8051_CSS_DES;
385
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
386
          wad2 = `OC8051_WAD_N;
387
          rom_addr_sel = `OC8051_RAS_PC;
388
 
389
 
390
        end
391
      `OC8051_DJNZ_R : begin
392
          ram_rd_sel = `OC8051_RRS_DC;
393
          ram_wr_sel = `OC8051_RWS_DC;
394
          src_sel1 = `OC8051_ASS_DC;
395
          src_sel2 = `OC8051_ASS_DC;
396
          alu_op = `OC8051_ALU_NOP;
397
          wr = 1'b0;
398
          psw_set = `OC8051_PS_NOT;
399
          cy_sel = `OC8051_CY_0;
400
          pc_wr = !eq;
401
          pc_sel = `OC8051_PIS_ALU;
402
          imm_sel = `OC8051_IDS_DC;
403
          src_sel3 = `OC8051_AS3_DC;
404
          comp_sel = `OC8051_CSS_DES;
405
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
406
          wad2 = `OC8051_WAD_N;
407
          rom_addr_sel = `OC8051_RAS_PC;
408
 
409
 
410
        end
411
      `OC8051_DJNZ_D : begin
412
          ram_rd_sel = `OC8051_RRS_DC;
413
          ram_wr_sel = `OC8051_RWS_DC;
414
          src_sel1 = `OC8051_ASS_DC;
415
          src_sel2 = `OC8051_ASS_DC;
416
          alu_op = `OC8051_ALU_NOP;
417
          wr = 1'b0;
418
          psw_set = `OC8051_PS_NOT;
419
          cy_sel = `OC8051_CY_0;
420
          pc_wr = !eq;
421
          pc_sel = `OC8051_PIS_ALU;
422
          imm_sel = `OC8051_IDS_DC;
423
          src_sel3 = `OC8051_AS3_DC;
424
          comp_sel = `OC8051_CSS_DES;
425
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
426
          wad2 = `OC8051_WAD_N;
427
          rom_addr_sel = `OC8051_RAS_PC;
428
 
429
 
430
        end
431
      `OC8051_JB : begin
432
          ram_rd_sel = `OC8051_RRS_DC;
433
          ram_wr_sel = `OC8051_RWS_DC;
434
          src_sel1 = `OC8051_ASS_DC;
435
          src_sel2 = `OC8051_ASS_DC;
436
          alu_op = `OC8051_ALU_NOP;
437
          wr = 1'b0;
438
          psw_set = `OC8051_PS_NOT;
439
          cy_sel = `OC8051_CY_0;
440
          pc_wr = eq;
441
          pc_sel = `OC8051_PIS_ALU;
442
          imm_sel = `OC8051_IDS_DC;
443
          src_sel3 = `OC8051_AS3_DC;
444
          comp_sel = `OC8051_CSS_BIT;
445
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
446
          wad2 = `OC8051_WAD_N;
447
          rom_addr_sel = `OC8051_RAS_PC;
448
 
449
 
450
        end
451
      `OC8051_JBC : begin
452
          ram_rd_sel = `OC8051_RRS_DC;
453
          ram_wr_sel = `OC8051_RWS_D;
454
          src_sel1 = `OC8051_ASS_DC;
455
          src_sel2 = `OC8051_ASS_DC;
456
          alu_op = `OC8051_ALU_NOP;
457
          wr = 1'b1;
458
          psw_set = `OC8051_PS_NOT;
459
          cy_sel = `OC8051_CY_0;
460
          pc_wr = eq;
461
          pc_sel = `OC8051_PIS_ALU;
462
          imm_sel = `OC8051_IDS_DC;
463
          src_sel3 = `OC8051_AS3_DC;
464
          comp_sel = `OC8051_CSS_BIT;
465
          rmw = `OC8051_RMW_N;        bit_addr = 1'b1;
466
          wad2 = `OC8051_WAD_N;
467
          rom_addr_sel = `OC8051_RAS_PC;
468
 
469
 
470
        end
471
      `OC8051_JC : begin
472
          ram_rd_sel = `OC8051_RRS_DC;
473
          ram_wr_sel = `OC8051_RWS_DC;
474
          src_sel1 = `OC8051_ASS_DC;
475
          src_sel2 = `OC8051_ASS_DC;
476
          alu_op = `OC8051_ALU_NOP;
477
          wr = 1'b0;
478
          psw_set = `OC8051_PS_NOT;
479
          cy_sel = `OC8051_CY_0;
480
          pc_wr = eq;
481
          pc_sel = `OC8051_PIS_ALU;
482
          imm_sel = `OC8051_IDS_DC;
483
          src_sel3 = `OC8051_AS3_DC;
484
          comp_sel = `OC8051_CSS_CY;
485
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
486
          wad2 = `OC8051_WAD_N;
487
          rom_addr_sel = `OC8051_RAS_PC;
488
 
489
 
490
        end
491
      `OC8051_JMP : begin
492
          ram_rd_sel = `OC8051_RRS_DC;
493
          ram_wr_sel = `OC8051_RWS_DC;
494
          src_sel1 = `OC8051_ASS_DC;
495
          src_sel2 = `OC8051_ASS_DC;
496
          alu_op = `OC8051_ALU_NOP;
497
          wr = 1'b0;
498
          psw_set = `OC8051_PS_NOT;
499
          cy_sel = `OC8051_CY_0;
500
          pc_wr = `OC8051_PCW_Y;
501
          pc_sel = `OC8051_PIS_ALU;
502
          imm_sel = `OC8051_IDS_DC;
503
          src_sel3 = `OC8051_AS3_DC;
504
          comp_sel = `OC8051_CSS_BIT;
505
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
506
          wad2 = `OC8051_WAD_N;
507
          rom_addr_sel = `OC8051_RAS_PC;
508
 
509
 
510
        end
511
      `OC8051_JNB : begin
512
          ram_rd_sel = `OC8051_RRS_DC;
513
          ram_wr_sel = `OC8051_RWS_DC;
514
          src_sel1 = `OC8051_ASS_DC;
515
          src_sel2 = `OC8051_ASS_DC;
516
          alu_op = `OC8051_ALU_NOP;
517
          wr = 1'b0;
518
          psw_set = `OC8051_PS_NOT;
519
          cy_sel = `OC8051_CY_0;
520
          pc_wr = !eq;
521
          pc_sel = `OC8051_PIS_ALU;
522
          imm_sel = `OC8051_IDS_DC;
523
          src_sel3 = `OC8051_AS3_DC;
524
          comp_sel = `OC8051_CSS_BIT;
525
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
526
          wad2 = `OC8051_WAD_N;
527
          rom_addr_sel = `OC8051_RAS_PC;
528
 
529
 
530
        end
531
      `OC8051_JNC : begin
532
          ram_rd_sel = `OC8051_RRS_DC;
533
          ram_wr_sel = `OC8051_RWS_DC;
534
          src_sel1 = `OC8051_ASS_DC;
535
          src_sel2 = `OC8051_ASS_DC;
536
          alu_op = `OC8051_ALU_NOP;
537
          wr = 1'b0;
538
          psw_set = `OC8051_PS_NOT;
539
          cy_sel = `OC8051_CY_0;
540
          pc_wr = !eq;
541
          pc_sel = `OC8051_PIS_ALU;
542
          imm_sel = `OC8051_IDS_DC;
543
          src_sel3 = `OC8051_AS3_DC;
544
          comp_sel = `OC8051_CSS_CY;
545
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
546
          wad2 = `OC8051_WAD_N;
547
          rom_addr_sel = `OC8051_RAS_PC;
548
 
549
 
550
        end
551
      `OC8051_JNZ : begin
552
          ram_rd_sel = `OC8051_RRS_DC;
553
          ram_wr_sel = `OC8051_RWS_DC;
554
          src_sel1 = `OC8051_ASS_DC;
555
          src_sel2 = `OC8051_ASS_DC;
556
          alu_op = `OC8051_ALU_NOP;
557
          wr = 1'b0;
558
          psw_set = `OC8051_PS_NOT;
559
          cy_sel = `OC8051_CY_0;
560
          pc_wr = !eq;
561
          pc_sel = `OC8051_PIS_ALU;
562
          imm_sel = `OC8051_IDS_DC;
563
          src_sel3 = `OC8051_AS3_DC;
564
          comp_sel = `OC8051_CSS_AZ;
565
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
566
          wad2 = `OC8051_WAD_N;
567
          rom_addr_sel = `OC8051_RAS_PC;
568
 
569
 
570
        end
571
      `OC8051_JZ : begin
572
          ram_rd_sel = `OC8051_RRS_DC;
573
          ram_wr_sel = `OC8051_RWS_DC;
574
          src_sel1 = `OC8051_ASS_DC;
575
          src_sel2 = `OC8051_ASS_DC;
576
          alu_op = `OC8051_ALU_NOP;
577
          wr = 1'b0;
578
          psw_set = `OC8051_PS_NOT;
579
          cy_sel = `OC8051_CY_0;
580
          pc_wr = eq;
581
          pc_sel = `OC8051_PIS_ALU;
582
          imm_sel = `OC8051_IDS_DC;
583
          src_sel3 = `OC8051_AS3_DC;
584
          comp_sel = `OC8051_CSS_AZ;
585
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
586
          wad2 = `OC8051_WAD_N;
587
          rom_addr_sel = `OC8051_RAS_PC;
588
 
589
 
590
        end
591
      `OC8051_MOVC_DP :begin
592
          ram_rd_sel = `OC8051_RRS_DC;
593
          ram_wr_sel = `OC8051_RWS_DC;
594
          src_sel1 = `OC8051_ASS_DC;
595
          src_sel2 = `OC8051_ASS_DC;
596
          alu_op = `OC8051_ALU_NOP;
597
          wr = 1'b0;
598
          psw_set = `OC8051_PS_NOT;
599
          cy_sel = `OC8051_CY_0;
600
          pc_wr = `OC8051_PCW_N;
601
          pc_sel = `OC8051_PIS_DC;
602
          imm_sel = `OC8051_IDS_DC;
603
          src_sel3 = `OC8051_AS3_DP;
604
          comp_sel = `OC8051_CSS_DC;
605
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
606
          wad2 = `OC8051_WAD_N;
607
          rom_addr_sel = `OC8051_RAS_DES;
608
 
609
 
610
        end
611
      `OC8051_MOVC_PC :begin
612
          ram_rd_sel = `OC8051_RRS_DC;
613
          ram_wr_sel = `OC8051_RWS_DC;
614
          src_sel1 = `OC8051_ASS_DC;
615
          src_sel2 = `OC8051_ASS_DC;
616
          alu_op = `OC8051_ALU_NOP;
617
          wr = 1'b0;
618
          psw_set = `OC8051_PS_NOT;
619
          cy_sel = `OC8051_CY_0;
620
          pc_wr = `OC8051_PCW_N;
621
          pc_sel = `OC8051_PIS_DC;
622
          imm_sel = `OC8051_IDS_DC;
623
          src_sel3 = `OC8051_AS3_PC;
624
          comp_sel = `OC8051_CSS_DC;
625
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
626
          wad2 = `OC8051_WAD_N;
627
          rom_addr_sel = `OC8051_RAS_DES;
628
 
629
        end
630
      `OC8051_SJMP : begin
631
          ram_rd_sel = `OC8051_RRS_DC;
632
          ram_wr_sel = `OC8051_RWS_DC;
633
          src_sel1 = `OC8051_ASS_DC;
634
          src_sel2 = `OC8051_ASS_DC;
635
          alu_op = `OC8051_ALU_NOP;
636
          wr = 1'b0;
637
          psw_set = `OC8051_PS_NOT;
638
          cy_sel = `OC8051_CY_0;
639
          pc_wr = `OC8051_PCW_Y;
640
          pc_sel = `OC8051_PIS_ALU;
641
          imm_sel = `OC8051_IDS_DC;
642
          src_sel3 = `OC8051_AS3_DC;
643
          comp_sel = `OC8051_CSS_DC;
644
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
645
          wad2 = `OC8051_WAD_N;
646
          rom_addr_sel = `OC8051_RAS_PC;
647
 
648
        end
649
      `OC8051_DIV : begin
650
          ram_rd_sel = `OC8051_RRS_D;
651
          ram_wr_sel = `OC8051_RWS_B;
652
          src_sel1 = `OC8051_ASS_ACC;
653
          src_sel2 = `OC8051_ASS_RAM;
654
          alu_op = `OC8051_ALU_DIV;
655
          wr = 1'b0;
656
          psw_set = `OC8051_PS_OV;
657
          cy_sel = `OC8051_CY_0;
658
          pc_wr = `OC8051_PCW_N;
659
          pc_sel = `OC8051_PIS_DC;
660
          imm_sel = `OC8051_IDS_DC;
661
          src_sel3 = `OC8051_AS3_DC;
662
          comp_sel = `OC8051_CSS_DC;
663
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
664
          wad2 = `OC8051_WAD_N;
665
          rom_addr_sel = `OC8051_RAS_PC;
666
 
667
        end
668
      `OC8051_MUL : begin
669
          ram_rd_sel = `OC8051_RRS_D;
670
          ram_wr_sel = `OC8051_RWS_B;
671
          src_sel1 = `OC8051_ASS_ACC;
672
          src_sel2 = `OC8051_ASS_RAM;
673
          alu_op = `OC8051_ALU_MUL;
674
          wr = 1'b0;
675
          psw_set = `OC8051_PS_OV;
676
          cy_sel = `OC8051_CY_0;
677
          pc_wr = `OC8051_PCW_N;
678
          pc_sel = `OC8051_PIS_DC;
679
          imm_sel = `OC8051_IDS_DC;
680
          src_sel3 = `OC8051_AS3_DC;
681
          comp_sel = `OC8051_CSS_DC;
682
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
683
          wad2 = `OC8051_WAD_N;
684
          rom_addr_sel = `OC8051_RAS_PC;
685
 
686
        end
687
      default begin
688
          ram_rd_sel = `OC8051_RRS_DC;
689
          ram_wr_sel = `OC8051_RWS_DC;
690
          src_sel1 = `OC8051_ASS_DC;
691
          src_sel2 = `OC8051_ASS_DC;
692
          alu_op = `OC8051_ALU_NOP;
693
          wr = 1'b0;
694
          psw_set = `OC8051_PS_NOT;
695
          cy_sel = `OC8051_CY_0;
696
          pc_wr = `OC8051_PCW_N;
697
          pc_sel = `OC8051_PIS_DC;
698
          imm_sel = `OC8051_IDS_DC;
699
          src_sel3 = `OC8051_AS3_DC;
700
          comp_sel = `OC8051_CSS_DC;
701
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
702
          wad2 = `OC8051_WAD_N;
703
          rom_addr_sel = `OC8051_RAS_PC;
704
 
705
      end
706
    endcase
707
 
708
    2'b11:
709
    casex (op)
710
      `OC8051_CJNE_R : begin
711
          ram_rd_sel = `OC8051_RRS_DC;
712
          ram_wr_sel = `OC8051_RWS_DC;
713
          src_sel1 = `OC8051_ASS_IMM;
714
          src_sel2 = `OC8051_ASS_IMM;
715
          alu_op = `OC8051_ALU_PCS;
716
          wr = 1'b0;
717
          psw_set = `OC8051_PS_NOT;
718
          cy_sel = `OC8051_CY_0;
719
          pc_wr = `OC8051_PCW_N;
720
          pc_sel = `OC8051_PIS_DC;
721
          imm_sel = `OC8051_IDS_OP3_PCL;
722
          src_sel3 = `OC8051_AS3_PC;
723
          comp_sel = `OC8051_CSS_DC;
724
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
725
          wad2 = `OC8051_WAD_N;
726
          rom_addr_sel = `OC8051_RAS_PC;
727
 
728
        end
729
      `OC8051_CJNE_I : begin
730
          ram_rd_sel = `OC8051_RRS_DC;
731
          ram_wr_sel = `OC8051_RWS_DC;
732
          src_sel1 = `OC8051_ASS_IMM;
733
          src_sel2 = `OC8051_ASS_IMM;
734
          alu_op = `OC8051_ALU_PCS;
735
          wr = 1'b0;
736
          psw_set = `OC8051_PS_NOT;
737
          cy_sel = `OC8051_CY_0;
738
          pc_wr = `OC8051_PCW_N;
739
          pc_sel = `OC8051_PIS_DC;
740
          imm_sel = `OC8051_IDS_OP3_PCL;
741
          src_sel3 = `OC8051_AS3_PC;
742
          comp_sel = `OC8051_CSS_DC;
743
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
744
          wad2 = `OC8051_WAD_N;
745
          rom_addr_sel = `OC8051_RAS_PC;
746
 
747
        end
748
      `OC8051_CJNE_D : begin
749
          ram_rd_sel = `OC8051_RRS_DC;
750
          ram_wr_sel = `OC8051_RWS_DC;
751
          src_sel1 = `OC8051_ASS_IMM;
752
          src_sel2 = `OC8051_ASS_IMM;
753
          alu_op = `OC8051_ALU_PCS;
754
          wr = 1'b0;
755
          psw_set = `OC8051_PS_NOT;
756
          cy_sel = `OC8051_CY_0;
757
          pc_wr = `OC8051_PCW_N;
758
          pc_sel = `OC8051_PIS_DC;
759
          imm_sel = `OC8051_IDS_OP3_PCL;
760
          src_sel3 = `OC8051_AS3_PC;
761
          comp_sel = `OC8051_CSS_DC;
762
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
763
          wad2 = `OC8051_WAD_N;
764
          rom_addr_sel = `OC8051_RAS_PC;
765
 
766
        end
767
      `OC8051_CJNE_C : begin
768
          ram_rd_sel = `OC8051_RRS_DC;
769
          ram_wr_sel = `OC8051_RWS_DC;
770
          src_sel1 = `OC8051_ASS_IMM;
771
          src_sel2 = `OC8051_ASS_IMM;
772
          alu_op = `OC8051_ALU_PCS;
773
          wr = 1'b0;
774
          psw_set = `OC8051_PS_NOT;
775
          cy_sel = `OC8051_CY_0;
776
          pc_wr = `OC8051_PCW_N;
777
          pc_sel = `OC8051_PIS_DC;
778
          imm_sel = `OC8051_IDS_OP3_PCL;
779
          src_sel3 = `OC8051_AS3_PC;
780
          comp_sel = `OC8051_CSS_DC;
781
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
782
          wad2 = `OC8051_WAD_N;
783
          rom_addr_sel = `OC8051_RAS_PC;
784
 
785
        end
786
      `OC8051_DJNZ_R : begin
787
          ram_rd_sel = `OC8051_RRS_DC;
788
          ram_wr_sel = `OC8051_RWS_DC;
789
          src_sel1 = `OC8051_ASS_IMM;
790
          src_sel2 = `OC8051_ASS_IMM;
791
          alu_op = `OC8051_ALU_PCS;
792
          wr = 1'b0;
793
          psw_set = `OC8051_PS_NOT;
794
          cy_sel = `OC8051_CY_0;
795
          pc_wr = `OC8051_PCW_N;
796
          pc_sel = `OC8051_PIS_DC;
797
          imm_sel = `OC8051_IDS_OP2_PCL;
798
          src_sel3 = `OC8051_AS3_PC;
799
          comp_sel = `OC8051_CSS_DC;
800
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
801
          wad2 = `OC8051_WAD_N;
802
          rom_addr_sel = `OC8051_RAS_PC;
803
 
804
        end
805
      `OC8051_DJNZ_D : begin
806
          ram_rd_sel = `OC8051_RRS_DC;
807
          ram_wr_sel = `OC8051_RWS_DC;
808
          src_sel1 = `OC8051_ASS_IMM;
809
          src_sel2 = `OC8051_ASS_IMM;
810
          alu_op = `OC8051_ALU_PCS;
811
          wr = 1'b0;
812
          psw_set = `OC8051_PS_NOT;
813
          cy_sel = `OC8051_CY_0;
814
          pc_wr = `OC8051_PCW_N;
815
          pc_sel = `OC8051_PIS_DC;
816
          imm_sel = `OC8051_IDS_OP3_PCL;
817
          src_sel3 = `OC8051_AS3_PC;
818
          comp_sel = `OC8051_CSS_DC;
819
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
820
          wad2 = `OC8051_WAD_N;
821
          rom_addr_sel = `OC8051_RAS_PC;
822
 
823
        end
824
      `OC8051_RET : begin
825
          ram_rd_sel = `OC8051_RRS_SP;
826
          ram_wr_sel = `OC8051_RWS_DC;
827
          src_sel1 = `OC8051_ASS_RAM;
828
          src_sel2 = `OC8051_ASS_DC;
829
          alu_op = `OC8051_ALU_NOP;
830
          wr = 1'b0;
831
          psw_set = `OC8051_PS_NOT;
832
          cy_sel = `OC8051_CY_0;
833
          pc_wr = `OC8051_PCW_Y;
834
          pc_sel = `OC8051_PIS_SP;
835
          imm_sel = `OC8051_IDS_DC;
836
          src_sel3 = `OC8051_AS3_DC;
837
          comp_sel = `OC8051_CSS_DC;
838
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
839
          wad2 = `OC8051_WAD_N;
840
          rom_addr_sel = `OC8051_RAS_PC;
841
 
842
        end
843
      `OC8051_RETI : begin
844
          ram_rd_sel = `OC8051_RRS_SP;
845
          ram_wr_sel = `OC8051_RWS_DC;
846
          src_sel1 = `OC8051_ASS_RAM;
847
          src_sel2 = `OC8051_ASS_DC;
848
          alu_op = `OC8051_ALU_NOP;
849
          wr = 1'b0;
850
          psw_set = `OC8051_PS_NOT;
851
          cy_sel = `OC8051_CY_0;
852
          pc_wr = `OC8051_PCW_Y;
853
          pc_sel = `OC8051_PIS_SP;
854
          imm_sel = `OC8051_IDS_DC;
855
          src_sel3 = `OC8051_AS3_DC;
856
          comp_sel = `OC8051_CSS_DC;
857
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
858
          wad2 = `OC8051_WAD_N;
859
          rom_addr_sel = `OC8051_RAS_PC;
860
 
861
        end
862
      `OC8051_DIV : begin
863
          ram_rd_sel = `OC8051_RRS_D;
864
          ram_wr_sel = `OC8051_RWS_B;
865
          src_sel1 = `OC8051_ASS_ACC;
866
          src_sel2 = `OC8051_ASS_RAM;
867
          alu_op = `OC8051_ALU_DIV;
868
          wr = 1'b0;
869
          psw_set = `OC8051_PS_OV;
870
          cy_sel = `OC8051_CY_0;
871
          pc_wr = `OC8051_PCW_N;
872
          pc_sel = `OC8051_PIS_DC;
873
          imm_sel = `OC8051_IDS_DC;
874
          src_sel3 = `OC8051_AS3_DC;
875
          comp_sel = `OC8051_CSS_DC;
876
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
877
          wad2 = `OC8051_WAD_N;
878
          rom_addr_sel = `OC8051_RAS_PC;
879
 
880
        end
881
      `OC8051_MUL : begin
882
          ram_rd_sel = `OC8051_RRS_D;
883
          ram_wr_sel = `OC8051_RWS_B;
884
          src_sel1 = `OC8051_ASS_ACC;
885
          src_sel2 = `OC8051_ASS_RAM;
886
          alu_op = `OC8051_ALU_MUL;
887
          wr = 1'b0;
888
          psw_set = `OC8051_PS_OV;
889
          cy_sel = `OC8051_CY_0;
890
          pc_wr = `OC8051_PCW_N;
891
          pc_sel = `OC8051_PIS_DC;
892
          imm_sel = `OC8051_IDS_DC;
893
          src_sel3 = `OC8051_AS3_DC;
894
          comp_sel = `OC8051_CSS_DC;
895
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
896
          wad2 = `OC8051_WAD_N;
897
          rom_addr_sel = `OC8051_RAS_PC;
898
 
899
        end
900
     default begin
901
          ram_rd_sel = `OC8051_RRS_DC;
902
          ram_wr_sel = `OC8051_RWS_DC;
903
          src_sel1 = `OC8051_ASS_DC;
904
          src_sel2 = `OC8051_ASS_DC;
905
          alu_op = `OC8051_ALU_NOP;
906
          wr = 1'b0;
907
          psw_set = `OC8051_PS_NOT;
908
          cy_sel = `OC8051_CY_0;
909
          pc_wr = `OC8051_PCW_N;
910
          pc_sel = `OC8051_PIS_DC;
911
          imm_sel = `OC8051_IDS_DC;
912
          src_sel3 = `OC8051_AS3_DC;
913
          comp_sel = `OC8051_CSS_DC;
914
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
915
          wad2 = `OC8051_WAD_N;
916
          rom_addr_sel = `OC8051_RAS_PC;
917
 
918
      end
919
    endcase
920
    default: begin
921
    casex (op_in)
922
      `OC8051_ACALL :begin
923
          ram_rd_sel = `OC8051_RRS_DC;
924
          ram_wr_sel = `OC8051_RWS_SP;
925
          src_sel1 = `OC8051_ASS_IMM;
926
          src_sel2 = `OC8051_ASS_DC;
927
          alu_op = `OC8051_ALU_NOP;
928
          imm_sel = `OC8051_IDS_PCL;
929
          wr = 1'b1;
930
          psw_set = `OC8051_PS_NOT;
931
          cy_sel = `OC8051_CY_0;
932
          pc_wr = `OC8051_PCW_Y;
933
          pc_sel = `OC8051_PIS_I11;
934
          src_sel3 = `OC8051_AS3_DC;
935
          comp_sel = `OC8051_CSS_DC;
936
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
937
          wad2 = `OC8051_WAD_N;
938
          rom_addr_sel = `OC8051_RAS_PC;
939
 
940
        end
941
      `OC8051_AJMP : begin
942
          ram_rd_sel = `OC8051_RRS_DC;
943
          ram_wr_sel = `OC8051_RWS_DC;
944
          src_sel1 = `OC8051_ASS_DC;
945
          src_sel2 = `OC8051_ASS_DC;
946
          alu_op = `OC8051_ALU_NOP;
947
          imm_sel = `OC8051_IDS_DC;
948
          wr = 1'b0;
949
          psw_set = `OC8051_PS_NOT;
950
          cy_sel = `OC8051_CY_0;
951
          pc_wr = `OC8051_PCW_Y;
952
          pc_sel = `OC8051_PIS_I11;
953
          src_sel3 = `OC8051_AS3_DC;
954
          comp_sel = `OC8051_CSS_DC;
955
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
956
          wad2 = `OC8051_WAD_N;
957
          rom_addr_sel = `OC8051_RAS_PC;
958
 
959
        end
960
      `OC8051_ADD_R : begin
961
          ram_rd_sel = `OC8051_RRS_RN;
962
          ram_wr_sel = `OC8051_RWS_ACC;
963
          src_sel1 = `OC8051_ASS_ACC;
964
          src_sel2 = `OC8051_ASS_RAM;
965
          alu_op = `OC8051_ALU_ADD;
966
          wr = 1'b1;
967
          psw_set = `OC8051_PS_AC;
968
          cy_sel = `OC8051_CY_0;
969
          pc_wr = `OC8051_PCW_N;
970
          pc_sel = `OC8051_PIS_DC;
971
          imm_sel = `OC8051_IDS_DC;
972
          src_sel3 = `OC8051_AS3_DC;
973
          comp_sel = `OC8051_CSS_DC;
974
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
975
          wad2 = `OC8051_WAD_N;
976
          rom_addr_sel = `OC8051_RAS_PC;
977
 
978
        end
979
      `OC8051_ADDC_R : begin
980
          ram_rd_sel = `OC8051_RRS_RN;
981
          ram_wr_sel = `OC8051_RWS_ACC;
982
          src_sel1 = `OC8051_ASS_ACC;
983
          src_sel2 = `OC8051_ASS_RAM;
984
          alu_op = `OC8051_ALU_ADD;
985
          wr = 1'b1;
986
          psw_set = `OC8051_PS_AC;
987
          cy_sel = `OC8051_CY_PSW;
988
          pc_wr = `OC8051_PCW_N;
989
          pc_sel = `OC8051_PIS_DC;
990
          imm_sel = `OC8051_IDS_DC;
991
          src_sel3 = `OC8051_AS3_DC;
992
          comp_sel = `OC8051_CSS_DC;
993
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
994
          wad2 = `OC8051_WAD_N;
995
          rom_addr_sel = `OC8051_RAS_PC;
996
 
997
        end
998
      `OC8051_ANL_R : begin
999
          ram_rd_sel = `OC8051_RRS_RN;
1000
          ram_wr_sel = `OC8051_RWS_ACC;
1001
          src_sel1 = `OC8051_ASS_ACC;
1002
          src_sel2 = `OC8051_ASS_RAM;
1003
          alu_op = `OC8051_ALU_AND;
1004
          wr = 1'b1;
1005
          psw_set = `OC8051_PS_NOT;
1006
          cy_sel = `OC8051_CY_0;
1007
          pc_wr = `OC8051_PCW_N;
1008
          pc_sel = `OC8051_PIS_DC;
1009
          imm_sel = `OC8051_IDS_DC;
1010
          src_sel3 = `OC8051_AS3_DC;
1011
          comp_sel = `OC8051_CSS_DC;
1012
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1013
          wad2 = `OC8051_WAD_N;
1014
          rom_addr_sel = `OC8051_RAS_PC;
1015
 
1016
        end
1017
      `OC8051_CJNE_R : begin
1018
          ram_rd_sel = `OC8051_RRS_RN;
1019
          ram_wr_sel = `OC8051_RWS_DC;
1020
          src_sel1 = `OC8051_ASS_RAM;
1021
          src_sel2 = `OC8051_ASS_IMM;
1022
          alu_op = `OC8051_ALU_SUB;
1023
          wr = 1'b0;
1024
          psw_set = `OC8051_PS_CY;
1025
          cy_sel = `OC8051_CY_0;
1026
          pc_wr = `OC8051_PCW_N;
1027
          pc_sel = `OC8051_PIS_DC;
1028
          imm_sel = `OC8051_IDS_OP2;
1029
          src_sel3 = `OC8051_AS3_DC;
1030
          comp_sel = `OC8051_CSS_DC;
1031
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1032
          wad2 = `OC8051_WAD_N;
1033
          rom_addr_sel = `OC8051_RAS_PC;
1034
 
1035
        end
1036
      `OC8051_DEC_R : begin
1037
          ram_rd_sel = `OC8051_RRS_RN;
1038
          ram_wr_sel = `OC8051_RWS_RN;
1039
          src_sel1 = `OC8051_ASS_RAM;
1040
          src_sel2 = `OC8051_ASS_ZERO;
1041
          alu_op = `OC8051_ALU_SUB;
1042
          wr = 1'b1;
1043
          psw_set = `OC8051_PS_NOT;
1044
          cy_sel = `OC8051_CY_1;
1045
          pc_wr = `OC8051_PCW_N;
1046
          pc_sel = `OC8051_PIS_DC;
1047
          imm_sel = `OC8051_IDS_DC;
1048
          src_sel3 = `OC8051_AS3_DC;
1049
          comp_sel = `OC8051_CSS_DC;
1050
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1051
          wad2 = `OC8051_WAD_N;
1052
          rom_addr_sel = `OC8051_RAS_PC;
1053
 
1054
        end
1055
      `OC8051_DJNZ_R : begin
1056
          ram_rd_sel = `OC8051_RRS_RN;
1057
          ram_wr_sel = `OC8051_RWS_RN;
1058
          src_sel1 = `OC8051_ASS_RAM;
1059
          src_sel2 = `OC8051_ASS_ZERO;
1060
          alu_op = `OC8051_ALU_SUB;
1061
          wr = 1'b1;
1062
          psw_set = `OC8051_PS_NOT;
1063
          cy_sel = `OC8051_CY_1;
1064
          pc_wr = `OC8051_PCW_N;
1065
          pc_sel = `OC8051_PIS_DC;
1066
          imm_sel = `OC8051_IDS_DC;
1067
          src_sel3 = `OC8051_AS3_DC;
1068
          comp_sel = `OC8051_CSS_DC;
1069
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1070
          wad2 = `OC8051_WAD_N;
1071
          rom_addr_sel = `OC8051_RAS_PC;
1072
 
1073
        end
1074
      `OC8051_INC_R : begin
1075
          ram_rd_sel = `OC8051_RRS_RN;
1076
          ram_wr_sel = `OC8051_RWS_RN;
1077
          src_sel1 = `OC8051_ASS_RAM;
1078
          src_sel2 = `OC8051_ASS_ZERO;
1079
          alu_op = `OC8051_ALU_ADD;
1080
          wr = 1'b1;
1081
          psw_set = `OC8051_PS_NOT;
1082
          cy_sel = `OC8051_CY_1;
1083
          pc_wr = `OC8051_PCW_N;
1084
          pc_sel = `OC8051_PIS_DC;
1085
          imm_sel = `OC8051_IDS_DC;
1086
          src_sel3 = `OC8051_AS3_DC;
1087
          comp_sel = `OC8051_CSS_DC;
1088
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1089
          wad2 = `OC8051_WAD_N;
1090
          rom_addr_sel = `OC8051_RAS_PC;
1091
 
1092
        end
1093
      `OC8051_MOV_R : begin
1094
          ram_rd_sel = `OC8051_RRS_RN;
1095
          ram_wr_sel = `OC8051_RWS_ACC;
1096
          src_sel1 = `OC8051_ASS_RAM;
1097
          src_sel2 = `OC8051_ASS_DC;
1098
          alu_op = `OC8051_ALU_NOP;
1099
          wr = 1'b1;
1100
          psw_set = `OC8051_PS_NOT;
1101
          cy_sel = `OC8051_CY_0;
1102
          pc_wr = `OC8051_PCW_N;
1103
          pc_sel = `OC8051_PIS_DC;
1104
          imm_sel = `OC8051_IDS_DC;
1105
          src_sel3 = `OC8051_AS3_DC;
1106
          comp_sel = `OC8051_CSS_DC;
1107
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1108
          wad2 = `OC8051_WAD_N;
1109
          rom_addr_sel = `OC8051_RAS_PC;
1110
 
1111
        end
1112
 
1113
      `OC8051_MOV_AR : begin
1114
          ram_rd_sel = `OC8051_RRS_DC;
1115
          ram_wr_sel = `OC8051_RWS_RN;
1116
          src_sel1 = `OC8051_ASS_ACC;
1117
          src_sel2 = `OC8051_ASS_DC;
1118
          alu_op = `OC8051_ALU_NOP;
1119
          wr = 1'b1;
1120
          psw_set = `OC8051_PS_NOT;
1121
          cy_sel = `OC8051_CY_0;
1122
          pc_wr = `OC8051_PCW_N;
1123
          pc_sel = `OC8051_PIS_DC;
1124
          imm_sel = `OC8051_IDS_DC;
1125
          src_sel3 = `OC8051_AS3_DC;
1126
          comp_sel = `OC8051_CSS_DC;
1127
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1128
          wad2 = `OC8051_WAD_N;
1129
          rom_addr_sel = `OC8051_RAS_PC;
1130
 
1131
        end
1132
      `OC8051_MOV_DR : begin
1133
          ram_rd_sel = `OC8051_RRS_D;
1134
          ram_wr_sel = `OC8051_RWS_RN;
1135
          src_sel1 = `OC8051_ASS_RAM;
1136
          src_sel2 = `OC8051_ASS_DC;
1137
          alu_op = `OC8051_ALU_NOP;
1138
          wr = 1'b1;
1139
          psw_set = `OC8051_PS_NOT;
1140
          cy_sel = `OC8051_CY_0;
1141
          pc_wr = `OC8051_PCW_N;
1142
          pc_sel = `OC8051_PIS_DC;
1143
          imm_sel = `OC8051_IDS_DC;
1144
          src_sel3 = `OC8051_AS3_DC;
1145
          comp_sel = `OC8051_CSS_DC;
1146
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1147
          wad2 = `OC8051_WAD_N;
1148
          rom_addr_sel = `OC8051_RAS_PC;
1149
 
1150
        end
1151
      `OC8051_MOV_CR : begin
1152
          ram_rd_sel = `OC8051_RRS_DC;
1153
          ram_wr_sel = `OC8051_RWS_RN;
1154
          src_sel1 = `OC8051_ASS_IMM;
1155
          src_sel2 = `OC8051_ASS_DC;
1156
          alu_op = `OC8051_ALU_NOP;
1157
          wr = 1'b1;
1158
          psw_set = `OC8051_PS_NOT;
1159
          cy_sel = `OC8051_CY_0;
1160
          pc_wr = `OC8051_PCW_N;
1161
          pc_sel = `OC8051_PIS_DC;
1162
          imm_sel = `OC8051_IDS_OP2;
1163
          src_sel3 = `OC8051_AS3_DC;
1164
          comp_sel = `OC8051_CSS_DC;
1165
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1166
          wad2 = `OC8051_WAD_N;
1167
          rom_addr_sel = `OC8051_RAS_PC;
1168
 
1169
        end
1170
      `OC8051_MOV_RD : begin
1171
          ram_rd_sel = `OC8051_RRS_RN;
1172
          ram_wr_sel = `OC8051_RWS_D;
1173
          src_sel1 = `OC8051_ASS_RAM;
1174
          src_sel2 = `OC8051_ASS_DC;
1175
          alu_op = `OC8051_ALU_NOP;
1176
          wr = 1'b1;
1177
          psw_set = `OC8051_PS_NOT;
1178
          cy_sel = `OC8051_CY_0;
1179
          pc_wr = `OC8051_PCW_N;
1180
          pc_sel = `OC8051_PIS_DC;
1181
          imm_sel = `OC8051_IDS_DC;
1182
          src_sel3 = `OC8051_AS3_DC;
1183
          comp_sel = `OC8051_CSS_DC;
1184
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1185
          wad2 = `OC8051_WAD_N;
1186
          rom_addr_sel = `OC8051_RAS_PC;
1187
 
1188
        end
1189
      `OC8051_ORL_R : begin
1190
          ram_rd_sel = `OC8051_RRS_RN;
1191
          ram_wr_sel = `OC8051_RWS_ACC;
1192
          src_sel1 = `OC8051_ASS_RAM;
1193
          src_sel2 = `OC8051_ASS_ACC;
1194
          alu_op = `OC8051_ALU_OR;
1195
          wr = 1'b1;
1196
          psw_set = `OC8051_PS_NOT;
1197
          cy_sel = `OC8051_CY_0;
1198
          pc_wr = `OC8051_PCW_N;
1199
          pc_sel = `OC8051_PIS_DC;
1200
          imm_sel = `OC8051_IDS_DC;
1201
          src_sel3 = `OC8051_AS3_DC;
1202
          comp_sel = `OC8051_CSS_DC;
1203
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1204
          wad2 = `OC8051_WAD_N;
1205
          rom_addr_sel = `OC8051_RAS_PC;
1206
 
1207
        end
1208
      `OC8051_SUBB_R : begin
1209
          ram_rd_sel = `OC8051_RRS_RN;
1210
          ram_wr_sel = `OC8051_RWS_ACC;
1211
          src_sel1 = `OC8051_ASS_ACC;
1212
          src_sel2 = `OC8051_ASS_RAM;
1213
          alu_op = `OC8051_ALU_SUB;
1214
          wr = 1'b1;
1215
          psw_set = `OC8051_PS_AC;
1216
          cy_sel = `OC8051_CY_PSW;
1217
          pc_wr = `OC8051_PCW_N;
1218
          pc_sel = `OC8051_PIS_DC;
1219
          imm_sel = `OC8051_IDS_DC;
1220
          src_sel3 = `OC8051_AS3_DC;
1221
          comp_sel = `OC8051_CSS_DC;
1222
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1223
          wad2 = `OC8051_WAD_N;
1224
          rom_addr_sel = `OC8051_RAS_PC;
1225
 
1226
        end
1227
      `OC8051_XCH_R : begin
1228
          ram_rd_sel = `OC8051_RRS_RN;
1229
          ram_wr_sel = `OC8051_RWS_RN;
1230
          src_sel1 = `OC8051_ASS_RAM;
1231
          src_sel2 = `OC8051_ASS_ACC;
1232
          alu_op = `OC8051_ALU_XCH;
1233
          wr = 1'b1;
1234
          psw_set = `OC8051_PS_NOT;
1235
          cy_sel = `OC8051_CY_1;
1236
          pc_wr = `OC8051_PCW_N;
1237
          pc_sel = `OC8051_PIS_DC;
1238
          imm_sel = `OC8051_IDS_DC;
1239
          src_sel3 = `OC8051_AS3_DC;
1240
          comp_sel = `OC8051_CSS_DC;
1241
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1242
          wad2 = `OC8051_WAD_Y;
1243
          rom_addr_sel = `OC8051_RAS_PC;
1244
 
1245
        end
1246
      `OC8051_XRL_R : begin
1247
          ram_rd_sel = `OC8051_RRS_RN;
1248
          ram_wr_sel = `OC8051_RWS_ACC;
1249
          src_sel1 = `OC8051_ASS_RAM;
1250
          src_sel2 = `OC8051_ASS_ACC;
1251
          alu_op = `OC8051_ALU_XOR;
1252
          wr = 1'b1;
1253
          psw_set = `OC8051_PS_NOT;
1254
          cy_sel = `OC8051_CY_0;
1255
          pc_wr = `OC8051_PCW_N;
1256
          pc_sel = `OC8051_PIS_DC;
1257
          imm_sel = `OC8051_IDS_DC;
1258
          src_sel3 = `OC8051_AS3_DC;
1259
          comp_sel = `OC8051_CSS_DC;
1260
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1261
          wad2 = `OC8051_WAD_N;
1262
          rom_addr_sel = `OC8051_RAS_PC;
1263
 
1264
        end
1265
 
1266
//op_code [7:1]
1267
      `OC8051_ADD_I : begin
1268
          ram_rd_sel = `OC8051_RRS_I;
1269
          ram_wr_sel = `OC8051_RWS_ACC;
1270
          src_sel1 = `OC8051_ASS_ACC;
1271
          src_sel2 = `OC8051_ASS_RAM;
1272
          alu_op = `OC8051_ALU_ADD;
1273
          wr = 1'b1;
1274
          psw_set = `OC8051_PS_AC;
1275
          cy_sel = `OC8051_CY_0;
1276
          pc_wr = `OC8051_PCW_N;
1277
          pc_sel = `OC8051_PIS_DC;
1278
          imm_sel = `OC8051_IDS_DC;
1279
          src_sel3 = `OC8051_AS3_DC;
1280
          comp_sel = `OC8051_CSS_DC;
1281
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1282
          wad2 = `OC8051_WAD_N;
1283
          rom_addr_sel = `OC8051_RAS_PC;
1284
 
1285
        end
1286
      `OC8051_ADDC_I : begin
1287
          ram_rd_sel = `OC8051_RRS_I;
1288
          ram_wr_sel = `OC8051_RWS_ACC;
1289
          src_sel1 = `OC8051_ASS_ACC;
1290
          src_sel2 = `OC8051_ASS_RAM;
1291
          alu_op = `OC8051_ALU_ADD;
1292
          wr = 1'b1;
1293
          psw_set = `OC8051_PS_AC;
1294
          cy_sel = `OC8051_CY_PSW;
1295
          pc_wr = `OC8051_PCW_N;
1296
          pc_sel = `OC8051_PIS_DC;
1297
          imm_sel = `OC8051_IDS_DC;
1298
          src_sel3 = `OC8051_AS3_DC;
1299
          comp_sel = `OC8051_CSS_DC;
1300
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1301
          wad2 = `OC8051_WAD_N;
1302
          rom_addr_sel = `OC8051_RAS_PC;
1303
 
1304
        end
1305
      `OC8051_ANL_I : begin
1306
          ram_rd_sel = `OC8051_RRS_I;
1307
          ram_wr_sel = `OC8051_RWS_ACC;
1308
          src_sel1 = `OC8051_ASS_ACC;
1309
          src_sel2 = `OC8051_ASS_RAM;
1310
          alu_op = `OC8051_ALU_AND;
1311
          wr = 1'b1;
1312
          psw_set = `OC8051_PS_NOT;
1313
          cy_sel = `OC8051_CY_0;
1314
          pc_wr = `OC8051_PCW_N;
1315
          pc_sel = `OC8051_PIS_DC;
1316
          imm_sel = `OC8051_IDS_DC;
1317
          src_sel3 = `OC8051_AS3_DC;
1318
          comp_sel = `OC8051_CSS_DC;
1319
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1320
          wad2 = `OC8051_WAD_N;
1321
          rom_addr_sel = `OC8051_RAS_PC;
1322
 
1323
        end
1324
      `OC8051_CJNE_I : begin
1325
          ram_rd_sel = `OC8051_RRS_I;
1326
          ram_wr_sel = `OC8051_RWS_DC;
1327
          src_sel1 = `OC8051_ASS_RAM;
1328
          src_sel2 = `OC8051_ASS_IMM;
1329
          alu_op = `OC8051_ALU_SUB;
1330
          wr = 1'b0;
1331
          psw_set = `OC8051_PS_CY;
1332
          cy_sel = `OC8051_CY_0;
1333
          pc_wr = `OC8051_PCW_N;
1334
          pc_sel = `OC8051_PIS_DC;
1335
          imm_sel = `OC8051_IDS_OP2;
1336
          src_sel3 = `OC8051_AS3_DC;
1337
          comp_sel = `OC8051_CSS_DC;
1338
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1339
          wad2 = `OC8051_WAD_N;
1340
          rom_addr_sel = `OC8051_RAS_PC;
1341
 
1342
        end
1343
      `OC8051_DEC_I : begin
1344
          ram_rd_sel = `OC8051_RRS_I;
1345
          ram_wr_sel = `OC8051_RWS_I;
1346
          src_sel1 = `OC8051_ASS_RAM;
1347
          src_sel2 = `OC8051_ASS_ZERO;
1348
          alu_op = `OC8051_ALU_SUB;
1349
          wr = 1'b1;
1350
          psw_set = `OC8051_PS_NOT;
1351
          cy_sel = `OC8051_CY_1;
1352
          pc_wr = `OC8051_PCW_N;
1353
          pc_sel = `OC8051_PIS_DC;
1354
          imm_sel = `OC8051_IDS_DC;
1355
          src_sel3 = `OC8051_AS3_DC;
1356
          comp_sel = `OC8051_CSS_DC;
1357
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1358
          wad2 = `OC8051_WAD_N;
1359
          rom_addr_sel = `OC8051_RAS_PC;
1360
 
1361
        end
1362
      `OC8051_INC_I : begin
1363
          ram_rd_sel = `OC8051_RRS_I;
1364
          ram_wr_sel = `OC8051_RWS_I;
1365
          src_sel1 = `OC8051_ASS_RAM;
1366
          src_sel2 = `OC8051_ASS_ZERO;
1367
          alu_op = `OC8051_ALU_ADD;
1368
          wr = 1'b1;
1369
          psw_set = `OC8051_PS_NOT;
1370
          cy_sel = `OC8051_CY_1;
1371
          pc_wr = `OC8051_PCW_N;
1372
          pc_sel = `OC8051_PIS_DC;
1373
          imm_sel = `OC8051_IDS_DC;
1374
          src_sel3 = `OC8051_AS3_DC;
1375
          comp_sel = `OC8051_CSS_DC;
1376
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1377
          wad2 = `OC8051_WAD_N;
1378
          rom_addr_sel = `OC8051_RAS_PC;
1379
 
1380
        end
1381
      `OC8051_MOV_I : begin
1382
          ram_rd_sel = `OC8051_RRS_I;
1383
          ram_wr_sel = `OC8051_RWS_ACC;
1384
          src_sel1 = `OC8051_ASS_RAM;
1385
          src_sel2 = `OC8051_ASS_DC;
1386
          alu_op = `OC8051_ALU_NOP;
1387
          wr = 1'b1;
1388
          psw_set = `OC8051_PS_NOT;
1389
          cy_sel = `OC8051_CY_0;
1390
          pc_wr = `OC8051_PCW_N;
1391
          pc_sel = `OC8051_PIS_DC;
1392
          imm_sel = `OC8051_IDS_DC;
1393
          src_sel3 = `OC8051_AS3_DC;
1394
          comp_sel = `OC8051_CSS_DC;
1395
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1396
          wad2 = `OC8051_WAD_N;
1397
          rom_addr_sel = `OC8051_RAS_PC;
1398
 
1399
        end
1400
      `OC8051_MOV_ID : begin
1401
          ram_rd_sel = `OC8051_RRS_I;
1402
          ram_wr_sel = `OC8051_RWS_D;
1403
          src_sel1 = `OC8051_ASS_RAM;
1404
          src_sel2 = `OC8051_ASS_DC;
1405
          alu_op = `OC8051_ALU_NOP;
1406
          wr = 1'b1;
1407
          psw_set = `OC8051_PS_NOT;
1408
          cy_sel = `OC8051_CY_0;
1409
          pc_wr = `OC8051_PCW_N;
1410
          pc_sel = `OC8051_PIS_DC;
1411
          imm_sel = `OC8051_IDS_DC;
1412
          src_sel3 = `OC8051_AS3_DC;
1413
          comp_sel = `OC8051_CSS_DC;
1414
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1415
          wad2 = `OC8051_WAD_N;
1416
          rom_addr_sel = `OC8051_RAS_PC;
1417
 
1418
        end
1419
      `OC8051_MOV_AI : begin
1420
          ram_rd_sel = `OC8051_RRS_DC;
1421
          ram_wr_sel = `OC8051_RWS_I;
1422
          src_sel1 = `OC8051_ASS_ACC;
1423
          src_sel2 = `OC8051_ASS_DC;
1424
          alu_op = `OC8051_ALU_NOP;
1425
          wr = 1'b1;
1426
          psw_set = `OC8051_PS_NOT;
1427
          cy_sel = `OC8051_CY_0;
1428
          pc_wr = `OC8051_PCW_N;
1429
          pc_sel = `OC8051_PIS_DC;
1430
          imm_sel = `OC8051_IDS_DC;
1431
          src_sel3 = `OC8051_AS3_DC;
1432
          comp_sel = `OC8051_CSS_DC;
1433
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1434
          wad2 = `OC8051_WAD_N;
1435
          rom_addr_sel = `OC8051_RAS_PC;
1436
 
1437
        end
1438
      `OC8051_MOV_DI : begin
1439
          ram_rd_sel = `OC8051_RRS_D;
1440
          ram_wr_sel = `OC8051_RWS_I;
1441
          src_sel1 = `OC8051_ASS_RAM;
1442
          src_sel2 = `OC8051_ASS_DC;
1443
          alu_op = `OC8051_ALU_NOP;
1444
          wr = 1'b1;
1445
          psw_set = `OC8051_PS_NOT;
1446
          cy_sel = `OC8051_CY_0;
1447
          pc_wr = `OC8051_PCW_N;
1448
          pc_sel = `OC8051_PIS_DC;
1449
          imm_sel = `OC8051_IDS_DC;
1450
          src_sel3 = `OC8051_AS3_DC;
1451
          comp_sel = `OC8051_CSS_DC;
1452
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1453
          wad2 = `OC8051_WAD_N;
1454
          rom_addr_sel = `OC8051_RAS_PC;
1455
 
1456
        end
1457
      `OC8051_MOV_CI : begin
1458
          ram_rd_sel = `OC8051_RRS_DC;
1459
          ram_wr_sel = `OC8051_RWS_I;
1460
          src_sel1 = `OC8051_ASS_IMM;
1461
          src_sel2 = `OC8051_ASS_DC;
1462
          alu_op = `OC8051_ALU_NOP;
1463
          wr = 1'b1;
1464
          psw_set = `OC8051_PS_NOT;
1465
          cy_sel = `OC8051_CY_0;
1466
          pc_wr = `OC8051_PCW_N;
1467
          pc_sel = `OC8051_PIS_DC;
1468
          imm_sel = `OC8051_IDS_OP2;
1469
          src_sel3 = `OC8051_AS3_DC;
1470
          comp_sel = `OC8051_CSS_DC;
1471
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1472
          wad2 = `OC8051_WAD_N;
1473
          rom_addr_sel = `OC8051_RAS_PC;
1474
 
1475
        end
1476
      `OC8051_MOVX_IA : begin
1477
          ram_rd_sel = `OC8051_RRS_DC;
1478
          ram_wr_sel = `OC8051_RWS_ACC;
1479
          src_sel1 = `OC8051_ASS_XRAM;
1480
          src_sel2 = `OC8051_ASS_DC;
1481
          alu_op = `OC8051_ALU_NOP;
1482
          wr = 1'b0;
1483
          psw_set = `OC8051_PS_NOT;
1484
          cy_sel = `OC8051_CY_0;
1485
          pc_wr = `OC8051_PCW_N;
1486
          pc_sel = `OC8051_PIS_DC;
1487
          imm_sel = `OC8051_IDS_OP2;
1488
          src_sel3 = `OC8051_AS3_DC;
1489
          comp_sel = `OC8051_CSS_DC;
1490
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1491
          wad2 = `OC8051_WAD_N;
1492
          rom_addr_sel = `OC8051_RAS_PC;
1493
        end
1494
      `OC8051_MOVX_AI :begin
1495
          ram_rd_sel = `OC8051_RRS_DC;
1496
          ram_wr_sel = `OC8051_RWS_ACC;
1497
          src_sel1 = `OC8051_ASS_DC;
1498
          src_sel2 = `OC8051_ASS_DC;
1499
          alu_op = `OC8051_ALU_NOP;
1500
          wr = 1'b0;
1501
          psw_set = `OC8051_PS_NOT;
1502
          cy_sel = `OC8051_CY_0;
1503
          pc_wr = `OC8051_PCW_N;
1504
          pc_sel = `OC8051_PIS_DC;
1505
          imm_sel = `OC8051_IDS_OP2;
1506
          src_sel3 = `OC8051_AS3_DC;
1507
          comp_sel = `OC8051_CSS_DC;
1508
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1509
          wad2 = `OC8051_WAD_N;
1510
          rom_addr_sel = `OC8051_RAS_PC;
1511
        end
1512
      `OC8051_ORL_I : begin
1513
          ram_rd_sel = `OC8051_RRS_I;
1514
          ram_wr_sel = `OC8051_RWS_ACC;
1515
          src_sel1 = `OC8051_ASS_RAM;
1516
          src_sel2 = `OC8051_ASS_ACC;
1517
          alu_op = `OC8051_ALU_OR;
1518
          wr = 1'b1;
1519
          psw_set = `OC8051_PS_NOT;
1520
          cy_sel = `OC8051_CY_0;
1521
          pc_wr = `OC8051_PCW_N;
1522
          pc_sel = `OC8051_PIS_DC;
1523
          imm_sel = `OC8051_IDS_DC;
1524
          src_sel3 = `OC8051_AS3_DC;
1525
          comp_sel = `OC8051_CSS_DC;
1526
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1527
          wad2 = `OC8051_WAD_N;
1528
          rom_addr_sel = `OC8051_RAS_PC;
1529
 
1530
        end
1531
      `OC8051_SUBB_I : begin
1532
          ram_rd_sel = `OC8051_RRS_I;
1533
          ram_wr_sel = `OC8051_RWS_ACC;
1534
          src_sel1 = `OC8051_ASS_ACC;
1535
          src_sel2 = `OC8051_ASS_RAM;
1536
          alu_op = `OC8051_ALU_SUB;
1537
          wr = 1'b1;
1538
          psw_set = `OC8051_PS_AC;
1539
          cy_sel = `OC8051_CY_PSW;
1540
          pc_wr = `OC8051_PCW_N;
1541
          pc_sel = `OC8051_PIS_DC;
1542
          imm_sel = `OC8051_IDS_DC;
1543
          src_sel3 = `OC8051_AS3_DC;
1544
          comp_sel = `OC8051_CSS_DC;
1545
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1546
          wad2 = `OC8051_WAD_N;
1547
          rom_addr_sel = `OC8051_RAS_PC;
1548
 
1549
        end
1550
      `OC8051_XCH_I : begin
1551
          ram_rd_sel = `OC8051_RRS_I;
1552
          ram_wr_sel = `OC8051_RWS_I;
1553
          src_sel1 = `OC8051_ASS_RAM;
1554
          src_sel2 = `OC8051_ASS_ACC;
1555
          alu_op = `OC8051_ALU_XCH;
1556
          wr = 1'b1;
1557
          psw_set = `OC8051_PS_NOT;
1558
          cy_sel = `OC8051_CY_1;
1559
          pc_wr = `OC8051_PCW_N;
1560
          pc_sel = `OC8051_PIS_DC;
1561
          imm_sel = `OC8051_IDS_DC;
1562
          src_sel3 = `OC8051_AS3_DC;
1563
          comp_sel = `OC8051_CSS_DC;
1564
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1565
          wad2 = `OC8051_WAD_Y;
1566
          rom_addr_sel = `OC8051_RAS_PC;
1567
 
1568
        end
1569
      `OC8051_XCHD :begin
1570
          ram_rd_sel = `OC8051_RRS_I;
1571
          ram_wr_sel = `OC8051_RWS_I;
1572
          src_sel1 = `OC8051_ASS_RAM;
1573
          src_sel2 = `OC8051_ASS_ACC;
1574
          alu_op = `OC8051_ALU_XCH;
1575
          wr = 1'b1;
1576
          psw_set = `OC8051_PS_NOT;
1577
          cy_sel = `OC8051_CY_0;
1578
          pc_wr = `OC8051_PCW_N;
1579
          pc_sel = `OC8051_PIS_DC;
1580
          imm_sel = `OC8051_IDS_DC;
1581
          src_sel3 = `OC8051_AS3_DC;
1582
          comp_sel = `OC8051_CSS_DC;
1583
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1584
          wad2 = `OC8051_WAD_Y;
1585
          rom_addr_sel = `OC8051_RAS_PC;
1586
 
1587
        end
1588
      `OC8051_XRL_I : begin
1589
          ram_rd_sel = `OC8051_RRS_I;
1590
          ram_wr_sel = `OC8051_RWS_ACC;
1591
          src_sel1 = `OC8051_ASS_RAM;
1592
          src_sel2 = `OC8051_ASS_ACC;
1593
          alu_op = `OC8051_ALU_XOR;
1594
          wr = 1'b1;
1595
          psw_set = `OC8051_PS_NOT;
1596
          cy_sel = `OC8051_CY_0;
1597
          pc_wr = `OC8051_PCW_N;
1598
          pc_sel = `OC8051_PIS_DC;
1599
          imm_sel = `OC8051_IDS_DC;
1600
          src_sel3 = `OC8051_AS3_DC;
1601
          comp_sel = `OC8051_CSS_DC;
1602
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1603
          wad2 = `OC8051_WAD_N;
1604
          rom_addr_sel = `OC8051_RAS_PC;
1605
 
1606
        end
1607
 
1608
//op_code [7:0]
1609
      `OC8051_ADD_D : begin
1610
          ram_rd_sel = `OC8051_RRS_D;
1611
          ram_wr_sel = `OC8051_RWS_ACC;
1612
          src_sel1 = `OC8051_ASS_ACC;
1613
          src_sel2 = `OC8051_ASS_RAM;
1614
          alu_op = `OC8051_ALU_ADD;
1615
          wr = 1'b1;
1616
          psw_set = `OC8051_PS_AC;
1617
          cy_sel = `OC8051_CY_0;
1618
          pc_wr = `OC8051_PCW_N;
1619
          pc_sel = `OC8051_PIS_DC;
1620
          imm_sel = `OC8051_IDS_DC;
1621
          src_sel3 = `OC8051_AS3_DC;
1622
          comp_sel = `OC8051_CSS_DC;
1623
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1624
          wad2 = `OC8051_WAD_N;
1625
          rom_addr_sel = `OC8051_RAS_PC;
1626
 
1627
        end
1628
      `OC8051_ADD_C : begin
1629
          ram_rd_sel = `OC8051_RRS_DC;
1630
          ram_wr_sel = `OC8051_RWS_ACC;
1631
          src_sel1 = `OC8051_ASS_IMM;
1632
          src_sel2 = `OC8051_ASS_ACC;
1633
          alu_op = `OC8051_ALU_ADD;
1634
          wr = 1'b1;
1635
          psw_set = `OC8051_PS_AC;
1636
          cy_sel = `OC8051_CY_0;
1637
          pc_wr = `OC8051_PCW_N;
1638
          pc_sel = `OC8051_PIS_DC;
1639
          imm_sel = `OC8051_IDS_OP2;
1640
          src_sel3 = `OC8051_AS3_DC;
1641
          comp_sel = `OC8051_CSS_DC;
1642
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1643
          wad2 = `OC8051_WAD_N;
1644
          rom_addr_sel = `OC8051_RAS_PC;
1645
 
1646
        end
1647
      `OC8051_ADDC_D : begin
1648
          ram_rd_sel = `OC8051_RRS_D;
1649
          ram_wr_sel = `OC8051_RWS_ACC;
1650
          src_sel1 = `OC8051_ASS_ACC;
1651
          src_sel2 = `OC8051_ASS_RAM;
1652
          alu_op = `OC8051_ALU_ADD;
1653
          wr = 1'b1;
1654
          psw_set = `OC8051_PS_AC;
1655
          cy_sel = `OC8051_CY_PSW;
1656
          pc_wr = `OC8051_PCW_N;
1657
          pc_sel = `OC8051_PIS_DC;
1658
          imm_sel = `OC8051_IDS_DC;
1659
          src_sel3 = `OC8051_AS3_DC;
1660
          comp_sel = `OC8051_CSS_DC;
1661
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1662
          wad2 = `OC8051_WAD_N;
1663
          rom_addr_sel = `OC8051_RAS_PC;
1664
 
1665
        end
1666
      `OC8051_ADDC_C : begin
1667
          ram_rd_sel = `OC8051_RRS_DC;
1668
          ram_wr_sel = `OC8051_RWS_ACC;
1669
          src_sel1 = `OC8051_ASS_IMM;
1670
          src_sel2 = `OC8051_ASS_ACC;
1671
          alu_op = `OC8051_ALU_ADD;
1672
          wr = 1'b1;
1673
          psw_set = `OC8051_PS_AC;
1674
          cy_sel = `OC8051_CY_PSW;
1675
          pc_wr = `OC8051_PCW_N;
1676
          pc_sel = `OC8051_PIS_DC;
1677
          imm_sel = `OC8051_IDS_OP2;
1678
          src_sel3 = `OC8051_AS3_DC;
1679
          comp_sel = `OC8051_CSS_DC;
1680
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1681
          wad2 = `OC8051_WAD_N;
1682
          rom_addr_sel = `OC8051_RAS_PC;
1683
 
1684
        end
1685
      `OC8051_ANL_D : begin
1686
          ram_rd_sel = `OC8051_RRS_D;
1687
          ram_wr_sel = `OC8051_RWS_ACC;
1688
          src_sel1 = `OC8051_ASS_ACC;
1689
          src_sel2 = `OC8051_ASS_RAM;
1690
          alu_op = `OC8051_ALU_AND;
1691
          wr = 1'b1;
1692
          psw_set = `OC8051_PS_NOT;
1693
          cy_sel = `OC8051_CY_0;
1694
          pc_wr = `OC8051_PCW_N;
1695
          pc_sel = `OC8051_PIS_DC;
1696
          imm_sel = `OC8051_IDS_DC;
1697
          src_sel3 = `OC8051_AS3_DC;
1698
          comp_sel = `OC8051_CSS_DC;
1699
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1700
          wad2 = `OC8051_WAD_N;
1701
          rom_addr_sel = `OC8051_RAS_PC;
1702
 
1703
        end
1704
      `OC8051_ANL_C : begin
1705
          ram_rd_sel = `OC8051_RRS_DC;
1706
          ram_wr_sel = `OC8051_RWS_ACC;
1707
          src_sel1 = `OC8051_ASS_IMM;
1708
          src_sel2 = `OC8051_ASS_ACC;
1709
          alu_op = `OC8051_ALU_AND;
1710
          wr = 1'b1;
1711
          psw_set = `OC8051_PS_NOT;
1712
          cy_sel = `OC8051_CY_0;
1713
          pc_wr = `OC8051_PCW_N;
1714
          pc_sel = `OC8051_PIS_DC;
1715
          imm_sel = `OC8051_IDS_OP2;
1716
          src_sel3 = `OC8051_AS3_DC;
1717
          comp_sel = `OC8051_CSS_DC;
1718
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1719
          wad2 = `OC8051_WAD_N;
1720
          rom_addr_sel = `OC8051_RAS_PC;
1721
 
1722
        end
1723
      `OC8051_ANL_DD : begin
1724
          ram_rd_sel = `OC8051_RRS_D;
1725
          ram_wr_sel = `OC8051_RWS_D;
1726
          src_sel1 = `OC8051_ASS_ACC;
1727
          src_sel2 = `OC8051_ASS_RAM;
1728
          alu_op = `OC8051_ALU_AND;
1729
          wr = 1'b1;
1730
          psw_set = `OC8051_PS_NOT;
1731
          cy_sel = `OC8051_CY_0;
1732
          pc_wr = `OC8051_PCW_N;
1733
          pc_sel = `OC8051_PIS_DC;
1734
          imm_sel = `OC8051_IDS_DC;
1735
          src_sel3 = `OC8051_AS3_DC;
1736
          comp_sel = `OC8051_CSS_DC;
1737
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1738
          wad2 = `OC8051_WAD_N;
1739
          rom_addr_sel = `OC8051_RAS_PC;
1740
 
1741
        end
1742
      `OC8051_ANL_DC : begin
1743
          ram_rd_sel = `OC8051_RRS_D;
1744
          ram_wr_sel = `OC8051_RWS_D;
1745
          src_sel1 = `OC8051_ASS_IMM;
1746
          src_sel2 = `OC8051_ASS_RAM;
1747
          alu_op = `OC8051_ALU_AND;
1748
          wr = 1'b1;
1749
          psw_set = `OC8051_PS_NOT;
1750
          cy_sel = `OC8051_CY_0;
1751
          pc_wr = `OC8051_PCW_N;
1752
          pc_sel = `OC8051_PIS_DC;
1753
          imm_sel = `OC8051_IDS_OP3;
1754
          src_sel3 = `OC8051_AS3_DC;
1755
          comp_sel = `OC8051_CSS_DC;
1756
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1757
          wad2 = `OC8051_WAD_N;
1758
          rom_addr_sel = `OC8051_RAS_PC;
1759
 
1760
        end
1761
      `OC8051_ANL_B : begin
1762
          ram_rd_sel = `OC8051_RRS_D;
1763
          ram_wr_sel = `OC8051_RWS_DC;
1764
          src_sel1 = `OC8051_ASS_DC;
1765
          src_sel2 = `OC8051_ASS_DC;
1766
          alu_op = `OC8051_ALU_AND;
1767
          wr = 1'b0;
1768
          psw_set = `OC8051_PS_CY;
1769
          cy_sel = `OC8051_CY_PSW;
1770
          pc_wr = `OC8051_PCW_N;
1771
          pc_sel = `OC8051_PIS_DC;
1772
          imm_sel = `OC8051_IDS_DC;
1773
          src_sel3 = `OC8051_AS3_DC;
1774
          comp_sel = `OC8051_CSS_DC;
1775
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
1776
          wad2 = `OC8051_WAD_N;
1777
          rom_addr_sel = `OC8051_RAS_PC;
1778
 
1779
        end
1780
      `OC8051_ANL_NB : begin
1781
          ram_rd_sel = `OC8051_RRS_D;
1782
          ram_wr_sel = `OC8051_RWS_DC;
1783
          src_sel1 = `OC8051_ASS_DC;
1784
          src_sel2 = `OC8051_ASS_DC;
1785
          alu_op = `OC8051_ALU_RR;
1786
          wr = 1'b0;
1787
          psw_set = `OC8051_PS_CY;
1788
          cy_sel = `OC8051_CY_PSW;
1789
          pc_wr = `OC8051_PCW_N;
1790
          pc_sel = `OC8051_PIS_DC;
1791
          imm_sel = `OC8051_IDS_DC;
1792
          src_sel3 = `OC8051_AS3_DC;
1793
          comp_sel = `OC8051_CSS_DC;
1794
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
1795
          wad2 = `OC8051_WAD_N;
1796
          rom_addr_sel = `OC8051_RAS_PC;
1797
 
1798
        end
1799
      `OC8051_CJNE_D : begin
1800
          ram_rd_sel = `OC8051_RRS_D;
1801
          ram_wr_sel = `OC8051_RWS_DC;
1802
          src_sel1 = `OC8051_ASS_ACC;
1803
          src_sel2 = `OC8051_ASS_RAM;
1804
          alu_op = `OC8051_ALU_SUB;
1805
          wr = 1'b0;
1806
          psw_set = `OC8051_PS_CY;
1807
          cy_sel = `OC8051_CY_0;
1808
          pc_wr = `OC8051_PCW_N;
1809
          pc_sel = `OC8051_PIS_DC;
1810
          imm_sel = `OC8051_IDS_DC;
1811
          src_sel3 = `OC8051_AS3_DC;
1812
          comp_sel = `OC8051_CSS_DC;
1813
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1814
          wad2 = `OC8051_WAD_N;
1815
          rom_addr_sel = `OC8051_RAS_PC;
1816
 
1817
        end
1818
      `OC8051_CJNE_C : begin
1819
          ram_rd_sel = `OC8051_RRS_DC;
1820
          ram_wr_sel = `OC8051_RWS_DC;
1821
          src_sel1 = `OC8051_ASS_ACC;
1822
          src_sel2 = `OC8051_ASS_IMM;
1823
          alu_op = `OC8051_ALU_SUB;
1824
          wr = 1'b0;
1825
          psw_set = `OC8051_PS_CY;
1826
          cy_sel = `OC8051_CY_0;
1827
          pc_wr = `OC8051_PCW_N;
1828
          pc_sel = `OC8051_PIS_DC;
1829
          imm_sel = `OC8051_IDS_OP2;
1830
          src_sel3 = `OC8051_AS3_DC;
1831
          comp_sel = `OC8051_CSS_DC;
1832
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1833
          wad2 = `OC8051_WAD_N;
1834
          rom_addr_sel = `OC8051_RAS_PC;
1835
 
1836
        end
1837
      `OC8051_CLR_A : begin
1838
          ram_rd_sel = `OC8051_RRS_DC;
1839
          ram_wr_sel = `OC8051_RWS_ACC;
1840
          src_sel1 = `OC8051_ASS_ACC;
1841
          src_sel2 = `OC8051_ASS_ACC;
1842
          alu_op = `OC8051_ALU_SUB;
1843
          wr = 1'b1;
1844
          psw_set = `OC8051_PS_NOT;
1845
          cy_sel = `OC8051_CY_0;
1846
          pc_wr = `OC8051_PCW_N;
1847
          pc_sel = `OC8051_PIS_DC;
1848
          imm_sel = `OC8051_IDS_DC;
1849
          src_sel3 = `OC8051_AS3_PC;
1850
          comp_sel = `OC8051_CSS_DC;
1851
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1852
          wad2 = `OC8051_WAD_N;
1853
          rom_addr_sel = `OC8051_RAS_PC;
1854
 
1855
        end
1856
      `OC8051_CLR_C : begin
1857
          ram_rd_sel = `OC8051_RRS_DC;
1858
          ram_wr_sel = `OC8051_RWS_DC;
1859
          src_sel1 = `OC8051_ASS_DC;
1860
          src_sel2 = `OC8051_ASS_DC;
1861
          alu_op = `OC8051_ALU_NOP;
1862
          wr = 1'b0;
1863
          psw_set = `OC8051_PS_CY;
1864
          cy_sel = `OC8051_CY_0;
1865
          pc_wr = `OC8051_PCW_N;
1866
          pc_sel = `OC8051_PIS_DC;
1867
          imm_sel = `OC8051_IDS_DC;
1868
          src_sel3 = `OC8051_AS3_PC;
1869
          comp_sel = `OC8051_CSS_DC;
1870
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1871
          wad2 = `OC8051_WAD_N;
1872
          rom_addr_sel = `OC8051_RAS_PC;
1873
 
1874
        end
1875
      `OC8051_CLR_B : begin
1876
          ram_rd_sel = `OC8051_RRS_D;
1877
          ram_wr_sel = `OC8051_RWS_D;
1878
          src_sel1 = `OC8051_ASS_DC;
1879
          src_sel2 = `OC8051_ASS_DC;
1880
          alu_op = `OC8051_ALU_NOP;
1881
          wr = 1'b1;
1882
          psw_set = `OC8051_PS_NOT;
1883
          cy_sel = `OC8051_CY_0;
1884
          pc_wr = `OC8051_PCW_N;
1885
          pc_sel = `OC8051_PIS_DC;
1886
          imm_sel = `OC8051_IDS_DC;
1887
          src_sel3 = `OC8051_AS3_PC;
1888
          comp_sel = `OC8051_CSS_DC;
1889
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
1890
          wad2 = `OC8051_WAD_N;
1891
          rom_addr_sel = `OC8051_RAS_PC;
1892
 
1893
        end
1894
      `OC8051_CPL_A : begin
1895
          ram_rd_sel = `OC8051_RRS_DC;
1896
          ram_wr_sel = `OC8051_RWS_ACC;
1897
          src_sel1 = `OC8051_ASS_ACC;
1898
          src_sel2 = `OC8051_ASS_DC;
1899
          alu_op = `OC8051_ALU_NOT;
1900
          wr = 1'b1;
1901
          psw_set = `OC8051_PS_NOT;
1902
          cy_sel = `OC8051_CY_0;
1903
          pc_wr = `OC8051_PCW_N;
1904
          pc_sel = `OC8051_PIS_DC;
1905
          imm_sel = `OC8051_IDS_OP3;   ///****
1906
          src_sel3 = `OC8051_AS3_DC;
1907
          comp_sel = `OC8051_CSS_DC;
1908
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1909
          wad2 = `OC8051_WAD_N;
1910
          rom_addr_sel = `OC8051_RAS_PC;
1911
 
1912
        end
1913
      `OC8051_CPL_C : begin
1914
          ram_rd_sel = `OC8051_RRS_DC;
1915
          ram_wr_sel = `OC8051_RWS_DC;
1916
          src_sel1 = `OC8051_ASS_DC;
1917
          src_sel2 = `OC8051_ASS_DC;
1918
          alu_op = `OC8051_ALU_NOT;
1919
          wr = 1'b0;
1920
          psw_set = `OC8051_PS_CY;
1921
          cy_sel = `OC8051_CY_PSW;
1922
          pc_wr = `OC8051_PCW_N;
1923
          pc_sel = `OC8051_PIS_DC;
1924
          imm_sel = `OC8051_IDS_OP3;  ///*****
1925
          src_sel3 = `OC8051_AS3_DC;
1926
          comp_sel = `OC8051_CSS_DC;
1927
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1928
          wad2 = `OC8051_WAD_N;
1929
          rom_addr_sel = `OC8051_RAS_PC;
1930
 
1931
        end
1932
      `OC8051_CPL_B : begin
1933
          ram_rd_sel = `OC8051_RRS_D;
1934
          ram_wr_sel = `OC8051_RWS_D;
1935
          src_sel1 = `OC8051_ASS_DC;
1936
          src_sel2 = `OC8051_ASS_DC;
1937
          alu_op = `OC8051_ALU_NOT;
1938
          wr = 1'b1;
1939
          psw_set = `OC8051_PS_NOT;
1940
          cy_sel = `OC8051_CY_RAM;
1941
          pc_wr = `OC8051_PCW_N;
1942
          pc_sel = `OC8051_PIS_DC;
1943
          imm_sel = `OC8051_IDS_OP3;  ///***
1944
          src_sel3 = `OC8051_AS3_DC;
1945
          comp_sel = `OC8051_CSS_DC;
1946
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
1947
          wad2 = `OC8051_WAD_N;
1948
          rom_addr_sel = `OC8051_RAS_PC;
1949
 
1950
        end
1951
      `OC8051_DA : begin
1952
          ram_rd_sel = `OC8051_RRS_DC;
1953
          ram_wr_sel = `OC8051_RWS_ACC;
1954
          src_sel1 = `OC8051_ASS_ACC;
1955
          src_sel2 = `OC8051_ASS_DC;
1956
          alu_op = `OC8051_ALU_DA;
1957
          wr = 1'b1;
1958
          psw_set = `OC8051_PS_CY;
1959
          cy_sel = `OC8051_CY_PSW;
1960
          pc_wr = `OC8051_PCW_N;
1961
          pc_sel = `OC8051_PIS_DC;
1962
          imm_sel = `OC8051_IDS_DC;
1963
          src_sel3 = `OC8051_AS3_DC;
1964
          comp_sel = `OC8051_CSS_DC;
1965
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1966
          wad2 = `OC8051_WAD_N;
1967
          rom_addr_sel = `OC8051_RAS_PC;
1968
 
1969
        end
1970
      `OC8051_DEC_A : begin
1971
          ram_rd_sel = `OC8051_RRS_DC;
1972
          ram_wr_sel = `OC8051_RWS_ACC;
1973
          src_sel1 = `OC8051_ASS_ACC;
1974
          src_sel2 = `OC8051_ASS_ZERO;
1975
          alu_op = `OC8051_ALU_SUB;
1976
          wr = 1'b1;
1977
          psw_set = `OC8051_PS_NOT;
1978
          cy_sel = `OC8051_CY_1;
1979
          pc_wr = `OC8051_PCW_N;
1980
          pc_sel = `OC8051_PIS_DC;
1981
          imm_sel = `OC8051_IDS_DC;
1982
          src_sel3 = `OC8051_AS3_DC;
1983
          comp_sel = `OC8051_CSS_DC;
1984
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1985
          wad2 = `OC8051_WAD_N;
1986
          rom_addr_sel = `OC8051_RAS_PC;
1987
 
1988
        end
1989
      `OC8051_DEC_D : begin
1990
          ram_rd_sel = `OC8051_RRS_D;
1991
          ram_wr_sel = `OC8051_RWS_D;
1992
          src_sel1 = `OC8051_ASS_RAM;
1993
          src_sel2 = `OC8051_ASS_ZERO;
1994
          alu_op = `OC8051_ALU_SUB;
1995
          wr = 1'b1;
1996
          psw_set = `OC8051_PS_NOT;
1997
          cy_sel = `OC8051_CY_1;
1998
          pc_wr = `OC8051_PCW_N;
1999
          pc_sel = `OC8051_PIS_DC;
2000
          imm_sel = `OC8051_IDS_DC;
2001
          src_sel3 = `OC8051_AS3_DC;
2002
          comp_sel = `OC8051_CSS_DC;
2003
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2004
          wad2 = `OC8051_WAD_N;
2005
          rom_addr_sel = `OC8051_RAS_PC;
2006
 
2007
        end
2008
      `OC8051_DIV : begin
2009
          ram_rd_sel = `OC8051_RRS_D;
2010
          ram_wr_sel = `OC8051_RWS_B;
2011
          src_sel1 = `OC8051_ASS_ACC;
2012
          src_sel2 = `OC8051_ASS_RAM;
2013
          alu_op = `OC8051_ALU_DIV;
2014
          wr = 1'b0;
2015
          psw_set = `OC8051_PS_OV;
2016
          cy_sel = `OC8051_CY_0;
2017
          pc_wr = `OC8051_PCW_N;
2018
          pc_sel = `OC8051_PIS_DC;
2019
          imm_sel = `OC8051_IDS_DC;
2020
          src_sel3 = `OC8051_AS3_DC;
2021
          comp_sel = `OC8051_CSS_DC;
2022
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2023
          wad2 = `OC8051_WAD_N;
2024
          rom_addr_sel = `OC8051_RAS_PC;
2025
 
2026
        end
2027
      `OC8051_DJNZ_D : begin
2028
          ram_rd_sel = `OC8051_RRS_D;
2029
          ram_wr_sel = `OC8051_RWS_D;
2030
          src_sel1 = `OC8051_ASS_RAM;
2031
          src_sel2 = `OC8051_ASS_ZERO;
2032
          alu_op = `OC8051_ALU_SUB;
2033
          wr = 1'b1;
2034
          psw_set = `OC8051_PS_NOT;
2035
          cy_sel = `OC8051_CY_1;
2036
          pc_wr = `OC8051_PCW_N;
2037
          pc_sel = `OC8051_PIS_DC;
2038
          imm_sel = `OC8051_IDS_DC;
2039
          src_sel3 = `OC8051_AS3_DC;
2040
          comp_sel = `OC8051_CSS_DC;
2041
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2042
          wad2 = `OC8051_WAD_N;
2043
          rom_addr_sel = `OC8051_RAS_PC;
2044
 
2045
        end
2046
      `OC8051_INC_A : begin
2047
          ram_rd_sel = `OC8051_RRS_DC;
2048
          ram_wr_sel = `OC8051_RWS_ACC;
2049
          src_sel1 = `OC8051_ASS_ACC;
2050
          src_sel2 = `OC8051_ASS_ZERO;
2051
          alu_op = `OC8051_ALU_ADD;
2052
          wr = 1'b1;
2053
          psw_set = `OC8051_PS_NOT;
2054
          cy_sel = `OC8051_CY_1;
2055
          pc_wr = `OC8051_PCW_N;
2056
          pc_sel = `OC8051_PIS_DC;
2057
          imm_sel = `OC8051_IDS_DC;
2058
          src_sel3 = `OC8051_AS3_DC;
2059
          comp_sel = `OC8051_CSS_DC;
2060
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2061
          wad2 = `OC8051_WAD_N;
2062
          rom_addr_sel = `OC8051_RAS_PC;
2063
 
2064
        end
2065
      `OC8051_INC_D : begin
2066
          ram_rd_sel = `OC8051_RRS_D;
2067
          ram_wr_sel = `OC8051_RWS_D;
2068
          src_sel1 = `OC8051_ASS_RAM;
2069
          src_sel2 = `OC8051_ASS_ZERO;
2070
          alu_op = `OC8051_ALU_ADD;
2071
          wr = 1'b1;
2072
          psw_set = `OC8051_PS_NOT;
2073
          cy_sel = `OC8051_CY_1;
2074
          pc_wr = `OC8051_PCW_N;
2075
          pc_sel = `OC8051_PIS_DC;
2076
          imm_sel = `OC8051_IDS_DC;
2077
          src_sel3 = `OC8051_AS3_DC;
2078
          comp_sel = `OC8051_CSS_DC;
2079
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2080
          wad2 = `OC8051_WAD_N;
2081
          rom_addr_sel = `OC8051_RAS_PC;
2082
 
2083
        end
2084
      `OC8051_INC_DP : begin
2085
          ram_rd_sel = `OC8051_RRS_D;
2086
          ram_wr_sel = `OC8051_RWS_DPTR;
2087
          src_sel1 = `OC8051_ASS_RAM;
2088
          src_sel2 = `OC8051_ASS_ZERO;
2089
          alu_op = `OC8051_ALU_ADD;
2090
          wr = 1'b1;
2091
          psw_set = `OC8051_PS_NOT;
2092
          cy_sel = `OC8051_CY_1;
2093
          pc_wr = `OC8051_PCW_N;
2094
          pc_sel = `OC8051_PIS_DC;
2095
          imm_sel = `OC8051_IDS_DC;
2096
          src_sel3 = `OC8051_AS3_DP;
2097
          comp_sel = `OC8051_CSS_DC;
2098
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2099
          wad2 = `OC8051_WAD_N;
2100
          rom_addr_sel = `OC8051_RAS_PC;
2101
 
2102
        end
2103
      `OC8051_JB : begin
2104
          ram_rd_sel = `OC8051_RRS_D;
2105
          ram_wr_sel = `OC8051_RWS_DC;
2106
          src_sel1 = `OC8051_ASS_IMM;
2107
          src_sel2 = `OC8051_ASS_IMM;
2108
          alu_op = `OC8051_ALU_PCS;
2109
          wr = 1'b0;
2110
          psw_set = `OC8051_PS_NOT;
2111
          cy_sel = `OC8051_CY_0;
2112
          pc_wr = `OC8051_PCW_N;
2113
          pc_sel = `OC8051_PIS_DC;
2114
          imm_sel = `OC8051_IDS_OP3_PCL;
2115
          src_sel3 = `OC8051_AS3_PC;
2116
          comp_sel = `OC8051_CSS_BIT;
2117
          rmw = `OC8051_RMW_N;        bit_addr = 1'b1;
2118
          wad2 = `OC8051_WAD_N;
2119
          rom_addr_sel = `OC8051_RAS_PC;
2120
 
2121
        end
2122
      `OC8051_JBC :begin
2123
          ram_rd_sel = `OC8051_RRS_D;
2124
          ram_wr_sel = `OC8051_RWS_DC;
2125
          src_sel1 = `OC8051_ASS_IMM;
2126
          src_sel2 = `OC8051_ASS_IMM;
2127
          alu_op = `OC8051_ALU_PCS;
2128
          wr = 1'b0;
2129
          psw_set = `OC8051_PS_NOT;
2130
          cy_sel = `OC8051_CY_0;
2131
          pc_wr = `OC8051_PCW_N;
2132
          pc_sel = `OC8051_PIS_DC;
2133
          imm_sel = `OC8051_IDS_OP3_PCL;
2134
          src_sel3 = `OC8051_AS3_PC;
2135
          comp_sel = `OC8051_CSS_BIT;
2136
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
2137
          wad2 = `OC8051_WAD_N;
2138
          rom_addr_sel = `OC8051_RAS_PC;
2139
 
2140
        end
2141
      `OC8051_JC : begin
2142
          ram_rd_sel = `OC8051_RRS_DC;
2143
          ram_wr_sel = `OC8051_RWS_DC;
2144
          src_sel1 = `OC8051_ASS_IMM;
2145
          src_sel2 = `OC8051_ASS_IMM;
2146
          alu_op = `OC8051_ALU_PCS;
2147
          wr = 1'b0;
2148
          psw_set = `OC8051_PS_NOT;
2149
          cy_sel = `OC8051_CY_0;
2150
          pc_wr = `OC8051_PCW_N;
2151
          pc_sel = `OC8051_PIS_DC;
2152
          imm_sel = `OC8051_IDS_OP2_PCL;
2153
          src_sel3 = `OC8051_AS3_PC;
2154
          comp_sel = `OC8051_CSS_CY;
2155
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2156
          wad2 = `OC8051_WAD_N;
2157
          rom_addr_sel = `OC8051_RAS_PC;
2158
 
2159
        end
2160
      `OC8051_JMP : begin
2161
          ram_rd_sel = `OC8051_RRS_D;
2162
          ram_wr_sel = `OC8051_RWS_DC;
2163
          src_sel1 = `OC8051_ASS_ACC;
2164
          src_sel2 = `OC8051_ASS_RAM;
2165
          alu_op = `OC8051_ALU_ADD;
2166
          wr = 1'b0;
2167
          psw_set = `OC8051_PS_NOT;
2168
          cy_sel = `OC8051_CY_0;
2169
          pc_wr = `OC8051_PCW_N;
2170
          pc_sel = `OC8051_PIS_DC;
2171
          imm_sel = `OC8051_IDS_DC;
2172
          src_sel3 = `OC8051_AS3_DP;
2173
          comp_sel = `OC8051_CSS_BIT;
2174
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2175
          wad2 = `OC8051_WAD_N;
2176
          rom_addr_sel = `OC8051_RAS_PC;
2177
 
2178
        end
2179
      `OC8051_JNB : begin
2180
          ram_rd_sel = `OC8051_RRS_D;
2181
          ram_wr_sel = `OC8051_RWS_DC;
2182
          src_sel1 = `OC8051_ASS_IMM;
2183
          src_sel2 = `OC8051_ASS_IMM;
2184
          alu_op = `OC8051_ALU_PCS;
2185
          wr = 1'b0;
2186
          psw_set = `OC8051_PS_NOT;
2187
          cy_sel = `OC8051_CY_0;
2188
          pc_wr = `OC8051_PCW_N;
2189
          pc_sel = `OC8051_PIS_DC;
2190
          imm_sel = `OC8051_IDS_OP3_PCL;
2191
          src_sel3 = `OC8051_AS3_PC;
2192
          comp_sel = `OC8051_CSS_BIT;
2193
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2194
          wad2 = `OC8051_WAD_N;
2195
          rom_addr_sel = `OC8051_RAS_PC;
2196
 
2197
        end
2198
      `OC8051_JNC : begin
2199
          ram_rd_sel = `OC8051_RRS_DC;
2200
          ram_wr_sel = `OC8051_RWS_DC;
2201
          src_sel1 = `OC8051_ASS_IMM;
2202
          src_sel2 = `OC8051_ASS_IMM;
2203
          alu_op = `OC8051_ALU_PCS;
2204
          wr = 1'b0;
2205
          psw_set = `OC8051_PS_NOT;
2206
          cy_sel = `OC8051_CY_0;
2207
          pc_wr = `OC8051_PCW_N;
2208
          pc_sel = `OC8051_PIS_DC;
2209
          imm_sel = `OC8051_IDS_OP2_PCL;
2210
          src_sel3 = `OC8051_AS3_PC;
2211
          comp_sel = `OC8051_CSS_CY;
2212
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2213
          wad2 = `OC8051_WAD_N;
2214
          rom_addr_sel = `OC8051_RAS_PC;
2215
 
2216
        end
2217
      `OC8051_JNZ :begin
2218
          ram_rd_sel = `OC8051_RRS_DC;
2219
          ram_wr_sel = `OC8051_RWS_DC;
2220
          src_sel1 = `OC8051_ASS_IMM;
2221
          src_sel2 = `OC8051_ASS_IMM;
2222
          alu_op = `OC8051_ALU_PCS;
2223
          wr = 1'b0;
2224
          psw_set = `OC8051_PS_NOT;
2225
          cy_sel = `OC8051_CY_0;
2226
          pc_wr = `OC8051_PCW_N;
2227
          pc_sel = `OC8051_PIS_DC;
2228
          imm_sel = `OC8051_IDS_OP2_PCL;
2229
          src_sel3 = `OC8051_AS3_PC;
2230
          comp_sel = `OC8051_CSS_AZ;
2231
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2232
          wad2 = `OC8051_WAD_N;
2233
          rom_addr_sel = `OC8051_RAS_PC;
2234
 
2235
        end
2236
      `OC8051_JZ : begin
2237
          ram_rd_sel = `OC8051_RRS_DC;
2238
          ram_wr_sel = `OC8051_RWS_DC;
2239
          src_sel1 = `OC8051_ASS_IMM;
2240
          src_sel2 = `OC8051_ASS_IMM;
2241
          alu_op = `OC8051_ALU_PCS;
2242
          wr = 1'b0;
2243
          psw_set = `OC8051_PS_NOT;
2244
          cy_sel = `OC8051_CY_0;
2245
          pc_wr = `OC8051_PCW_N;
2246
          pc_sel = `OC8051_PIS_DC;
2247
          imm_sel = `OC8051_IDS_OP2_PCL;
2248
          src_sel3 = `OC8051_AS3_PC;
2249
          comp_sel = `OC8051_CSS_AZ;
2250
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2251
          wad2 = `OC8051_WAD_N;
2252
          rom_addr_sel = `OC8051_RAS_PC;
2253
 
2254
        end
2255
      `OC8051_LCALL :begin
2256
          ram_rd_sel = `OC8051_RRS_DC;
2257
          ram_wr_sel = `OC8051_RWS_SP;
2258
          src_sel1 = `OC8051_ASS_IMM;
2259
          src_sel2 = `OC8051_ASS_DC;
2260
          alu_op = `OC8051_ALU_NOP;
2261
          imm_sel = `OC8051_IDS_PCL;
2262
          wr = 1'b1;
2263
          psw_set = `OC8051_PS_NOT;
2264
          cy_sel = `OC8051_CY_0;
2265
          pc_wr = `OC8051_PCW_Y;
2266
          pc_sel = `OC8051_PIS_I16;
2267
          src_sel3 = `OC8051_AS3_DC;
2268
          comp_sel = `OC8051_CSS_DC;
2269
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2270
          wad2 = `OC8051_WAD_N;
2271
          rom_addr_sel = `OC8051_RAS_PC;
2272
 
2273
        end
2274
      `OC8051_LJMP : begin
2275
          ram_rd_sel = `OC8051_RRS_DC;
2276
          ram_wr_sel = `OC8051_RWS_DC;
2277
          src_sel1 = `OC8051_ASS_DC;
2278
          src_sel2 = `OC8051_ASS_DC;
2279
          alu_op = `OC8051_ALU_NOP;
2280
          imm_sel = `OC8051_IDS_DC;
2281
          wr = 1'b0;
2282
          psw_set = `OC8051_PS_NOT;
2283
          cy_sel = `OC8051_CY_0;
2284
          pc_wr = `OC8051_PCW_Y;
2285
          pc_sel = `OC8051_PIS_I16;
2286
          src_sel3 = `OC8051_AS3_DC;
2287
          comp_sel = `OC8051_CSS_DC;
2288
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2289
          wad2 = `OC8051_WAD_N;
2290
          rom_addr_sel = `OC8051_RAS_PC;
2291
 
2292
        end
2293
      `OC8051_MOV_D : begin
2294
          ram_rd_sel = `OC8051_RRS_D;
2295
          ram_wr_sel = `OC8051_RWS_ACC;
2296
          src_sel1 = `OC8051_ASS_RAM;
2297
          src_sel2 = `OC8051_ASS_DC;
2298
          alu_op = `OC8051_ALU_NOP;
2299
          wr = 1'b1;
2300
          psw_set = `OC8051_PS_NOT;
2301
          cy_sel = `OC8051_CY_0;
2302
          pc_wr = `OC8051_PCW_N;
2303
          pc_sel = `OC8051_PIS_DC;
2304
          imm_sel = `OC8051_IDS_DC;
2305
          src_sel3 = `OC8051_AS3_DC;
2306
          comp_sel = `OC8051_CSS_DC;
2307
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2308
          wad2 = `OC8051_WAD_N;
2309
          rom_addr_sel = `OC8051_RAS_PC;
2310
 
2311
        end
2312
      `OC8051_MOV_C : begin
2313
          ram_rd_sel = `OC8051_RRS_DC;
2314
          ram_wr_sel = `OC8051_RWS_ACC;
2315
          src_sel1 = `OC8051_ASS_IMM;
2316
          src_sel2 = `OC8051_ASS_DC;
2317
          alu_op = `OC8051_ALU_NOP;
2318
          wr = 1'b1;
2319
          psw_set = `OC8051_PS_NOT;
2320
          cy_sel = `OC8051_CY_0;
2321
          pc_wr = `OC8051_PCW_N;
2322
          pc_sel = `OC8051_PIS_DC;
2323
          imm_sel = `OC8051_IDS_OP2;
2324
          src_sel3 = `OC8051_AS3_DC;
2325
          comp_sel = `OC8051_CSS_DC;
2326
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2327
          wad2 = `OC8051_WAD_N;
2328
          rom_addr_sel = `OC8051_RAS_PC;
2329
 
2330
        end
2331
 
2332
      `OC8051_MOV_DA : begin
2333
          ram_rd_sel = `OC8051_RRS_DC;
2334
          ram_wr_sel = `OC8051_RWS_D;
2335
          src_sel1 = `OC8051_ASS_ACC;
2336
          src_sel2 = `OC8051_ASS_DC;
2337
          alu_op = `OC8051_ALU_NOP;
2338
          wr = 1'b1;
2339
          psw_set = `OC8051_PS_NOT;
2340
          cy_sel = `OC8051_CY_0;
2341
          pc_wr = `OC8051_PCW_N;
2342
          pc_sel = `OC8051_PIS_DC;
2343
          imm_sel = `OC8051_IDS_DC;
2344
          src_sel3 = `OC8051_AS3_DC;
2345
          comp_sel = `OC8051_CSS_DC;
2346
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2347
          wad2 = `OC8051_WAD_N;
2348
          rom_addr_sel = `OC8051_RAS_PC;
2349
 
2350
        end
2351
      `OC8051_MOV_DD : begin
2352
          ram_rd_sel = `OC8051_RRS_D;
2353
          ram_wr_sel = `OC8051_RWS_D3;
2354
          src_sel1 = `OC8051_ASS_RAM;
2355
          src_sel2 = `OC8051_ASS_DC;
2356
          alu_op = `OC8051_ALU_NOP;
2357
          wr = 1'b1;
2358
          psw_set = `OC8051_PS_NOT;
2359
          cy_sel = `OC8051_CY_0;
2360
          pc_wr = `OC8051_PCW_N;
2361
          pc_sel = `OC8051_PIS_DC;
2362
          imm_sel = `OC8051_IDS_OP2;
2363
          src_sel3 = `OC8051_AS3_DC;
2364
          comp_sel = `OC8051_CSS_DC;
2365
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2366
          wad2 = `OC8051_WAD_N;
2367
          rom_addr_sel = `OC8051_RAS_PC;
2368
 
2369
        end
2370
      `OC8051_MOV_CD : begin
2371
          ram_rd_sel = `OC8051_RRS_DC;
2372
          ram_wr_sel = `OC8051_RWS_D;
2373
          src_sel1 = `OC8051_ASS_IMM;
2374
          src_sel2 = `OC8051_ASS_DC;
2375
          alu_op = `OC8051_ALU_NOP;
2376
          wr = 1'b1;
2377
          psw_set = `OC8051_PS_NOT;
2378
          cy_sel = `OC8051_CY_0;
2379
          pc_wr = `OC8051_PCW_N;
2380
          pc_sel = `OC8051_PIS_DC;
2381
          imm_sel = `OC8051_IDS_OP3;
2382
          src_sel3 = `OC8051_AS3_DC;
2383
          comp_sel = `OC8051_CSS_DC;
2384
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2385
          wad2 = `OC8051_WAD_N;
2386
          rom_addr_sel = `OC8051_RAS_PC;
2387
 
2388
        end
2389
      `OC8051_MOV_BC : begin
2390
          ram_rd_sel = `OC8051_RRS_D;
2391
          ram_wr_sel = `OC8051_RWS_DC;
2392
          src_sel1 = `OC8051_ASS_DC;
2393
          src_sel2 = `OC8051_ASS_DC;
2394
          alu_op = `OC8051_ALU_NOP;
2395
          wr = 1'b0;
2396
          psw_set = `OC8051_PS_CY;
2397
          cy_sel = `OC8051_CY_RAM;
2398
          pc_wr = `OC8051_PCW_N;
2399
          pc_sel = `OC8051_PIS_DC;
2400
          imm_sel = `OC8051_IDS_DC;
2401
          src_sel3 = `OC8051_AS3_DC;
2402
          comp_sel = `OC8051_CSS_DC;
2403
          rmw = `OC8051_RMW_N;        bit_addr = 1'b1;
2404
          wad2 = `OC8051_WAD_N;
2405
          rom_addr_sel = `OC8051_RAS_PC;
2406
 
2407
        end
2408
      `OC8051_MOV_CB : begin
2409
          ram_rd_sel = `OC8051_RRS_D;
2410
          ram_wr_sel = `OC8051_RWS_D;
2411
          src_sel1 = `OC8051_ASS_DC;
2412
          src_sel2 = `OC8051_ASS_DC;
2413
          alu_op = `OC8051_ALU_NOP;
2414
          wr = 1'b1;
2415
          psw_set = `OC8051_PS_NOT;
2416
          cy_sel = `OC8051_CY_PSW;
2417
          pc_wr = `OC8051_PCW_N;
2418
          pc_sel = `OC8051_PIS_DC;
2419
          imm_sel = `OC8051_IDS_OP3;
2420
          src_sel3 = `OC8051_AS3_DC;
2421
          comp_sel = `OC8051_CSS_DC;
2422
          rmw = `OC8051_RMW_N;        bit_addr = 1'b1;
2423
          wad2 = `OC8051_WAD_N;
2424
          rom_addr_sel = `OC8051_RAS_PC;
2425
 
2426
        end
2427
      `OC8051_MOV_DP : begin  ///***
2428
          ram_rd_sel = `OC8051_RRS_DC;
2429
          ram_wr_sel = `OC8051_RWS_DPTR;
2430
          src_sel1 = `OC8051_ASS_IMM;
2431
          src_sel2 = `OC8051_ASS_IMM;
2432
          alu_op = `OC8051_ALU_NOP;
2433
          wr = 1'b1;
2434
          psw_set = `OC8051_PS_NOT;
2435
          cy_sel = `OC8051_CY_0;
2436
          pc_wr = `OC8051_PCW_N;
2437
          pc_sel = `OC8051_PIS_DC;
2438
          imm_sel = `OC8051_IDS_OP3_OP2;
2439
          src_sel3 = `OC8051_AS3_DC;
2440
          comp_sel = `OC8051_CSS_DC;
2441
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2442
          wad2 = `OC8051_WAD_N;
2443
          rom_addr_sel = `OC8051_RAS_PC;
2444
 
2445
        end
2446
      `OC8051_MOVC_DP :begin
2447
          ram_rd_sel = `OC8051_RRS_D;
2448
          ram_wr_sel = `OC8051_RWS_DC;
2449
          src_sel1 = `OC8051_ASS_ACC;
2450
          src_sel2 = `OC8051_ASS_RAM;
2451
          alu_op = `OC8051_ALU_ADD;
2452
          wr = 1'b0;
2453
          psw_set = `OC8051_PS_NOT;
2454
          cy_sel = `OC8051_CY_0;
2455
          pc_wr = `OC8051_PCW_N;
2456
          pc_sel = `OC8051_PIS_DC;
2457
          imm_sel = `OC8051_IDS_DC;
2458
          src_sel3 = `OC8051_AS3_DP;
2459
          comp_sel = `OC8051_CSS_DC;
2460
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2461
          wad2 = `OC8051_WAD_N;
2462
          rom_addr_sel = `OC8051_RAS_PC;
2463
 
2464
        end
2465
      `OC8051_MOVC_PC : begin
2466
          ram_rd_sel = `OC8051_RRS_DC;
2467
          ram_wr_sel = `OC8051_RWS_DC;
2468
          src_sel1 = `OC8051_ASS_IMM;
2469
          src_sel2 = `OC8051_ASS_ACC;
2470
          alu_op = `OC8051_ALU_ADD;
2471
          wr = 1'b0;
2472
          psw_set = `OC8051_PS_NOT;
2473
          cy_sel = `OC8051_CY_0;
2474
          pc_wr = `OC8051_PCW_N;
2475
          pc_sel = `OC8051_PIS_DC;
2476
          imm_sel = `OC8051_IDS_PCL;
2477
          src_sel3 = `OC8051_AS3_PC;
2478
          comp_sel = `OC8051_CSS_DC;
2479
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2480
          wad2 = `OC8051_WAD_N;
2481
          rom_addr_sel = `OC8051_RAS_PC;
2482
 
2483
        end
2484
      `OC8051_MOVX_PA : begin
2485
          ram_rd_sel = `OC8051_RRS_DC;
2486
          ram_wr_sel = `OC8051_RWS_ACC;
2487
          src_sel1 = `OC8051_ASS_XRAM;
2488
          src_sel2 = `OC8051_ASS_DC;
2489
          alu_op = `OC8051_ALU_NOP;
2490
          wr = 1'b0;
2491
          psw_set = `OC8051_PS_NOT;
2492
          cy_sel = `OC8051_CY_0;
2493
          pc_wr = `OC8051_PCW_N;
2494
          pc_sel = `OC8051_PIS_DC;
2495
          imm_sel = `OC8051_IDS_OP2;
2496
          src_sel3 = `OC8051_AS3_DC;
2497
          comp_sel = `OC8051_CSS_DC;
2498
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2499
          wad2 = `OC8051_WAD_N;
2500
          rom_addr_sel = `OC8051_RAS_PC;
2501
        end
2502
      `OC8051_MOVX_AP : begin
2503
          ram_rd_sel = `OC8051_RRS_DC;
2504
          ram_wr_sel = `OC8051_RWS_DC;
2505
          src_sel1 = `OC8051_ASS_XRAM;
2506
          src_sel2 = `OC8051_ASS_DC;
2507
          alu_op = `OC8051_ALU_NOP;
2508
          wr = 1'b0;
2509
          psw_set = `OC8051_PS_NOT;
2510
          cy_sel = `OC8051_CY_0;
2511
          pc_wr = `OC8051_PCW_N;
2512
          pc_sel = `OC8051_PIS_DC;
2513
          imm_sel = `OC8051_IDS_DC;
2514
          src_sel3 = `OC8051_AS3_DC;
2515
          comp_sel = `OC8051_CSS_DC;
2516
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2517
          wad2 = `OC8051_WAD_N;
2518
          rom_addr_sel = `OC8051_RAS_PC;
2519
        end
2520
      `OC8051_MUL : begin
2521
          ram_rd_sel = `OC8051_RRS_D;
2522
          ram_wr_sel = `OC8051_RWS_B;
2523
          src_sel1 = `OC8051_ASS_ACC;
2524
          src_sel2 = `OC8051_ASS_RAM;
2525
          alu_op = `OC8051_ALU_MUL;
2526
          wr = 1'b0;
2527
          psw_set = `OC8051_PS_OV;
2528
          cy_sel = `OC8051_CY_0;
2529
          pc_wr = `OC8051_PCW_N;
2530
          pc_sel = `OC8051_PIS_DC;
2531
          imm_sel = `OC8051_IDS_DC;
2532
          src_sel3 = `OC8051_AS3_DC;
2533
          comp_sel = `OC8051_CSS_DC;
2534
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2535
          wad2 = `OC8051_WAD_N;
2536
          rom_addr_sel = `OC8051_RAS_PC;
2537
 
2538
        end
2539
      `OC8051_ORL_D : begin
2540
          ram_rd_sel = `OC8051_RRS_D;
2541
          ram_wr_sel = `OC8051_RWS_ACC;
2542
          src_sel1 = `OC8051_ASS_RAM;
2543
          src_sel2 = `OC8051_ASS_ACC;
2544
          alu_op = `OC8051_ALU_OR;
2545
          wr = 1'b1;
2546
          psw_set = `OC8051_PS_NOT;
2547
          cy_sel = `OC8051_CY_0;
2548
          pc_wr = `OC8051_PCW_N;
2549
          pc_sel = `OC8051_PIS_DC;
2550
          imm_sel = `OC8051_IDS_DC;
2551
          src_sel3 = `OC8051_AS3_DC;
2552
          comp_sel = `OC8051_CSS_DC;
2553
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2554
          wad2 = `OC8051_WAD_N;
2555
          rom_addr_sel = `OC8051_RAS_PC;
2556
 
2557
        end
2558
      `OC8051_ORL_C : begin
2559
          ram_rd_sel = `OC8051_RRS_DC;
2560
          ram_wr_sel = `OC8051_RWS_ACC;
2561
          src_sel1 = `OC8051_ASS_IMM;
2562
          src_sel2 = `OC8051_ASS_ACC;
2563
          alu_op = `OC8051_ALU_OR;
2564
          wr = 1'b1;
2565
          psw_set = `OC8051_PS_NOT;
2566
          cy_sel = `OC8051_CY_0;
2567
          pc_wr = `OC8051_PCW_N;
2568
          pc_sel = `OC8051_PIS_DC;
2569
          imm_sel = `OC8051_IDS_OP2;
2570
          src_sel3 = `OC8051_AS3_DC;
2571
          comp_sel = `OC8051_CSS_DC;
2572
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2573
          wad2 = `OC8051_WAD_N;
2574
          rom_addr_sel = `OC8051_RAS_PC;
2575
 
2576
        end
2577
      `OC8051_ORL_AD : begin
2578
          ram_rd_sel = `OC8051_RRS_D;
2579
          ram_wr_sel = `OC8051_RWS_D;
2580
          src_sel1 = `OC8051_ASS_RAM;
2581
          src_sel2 = `OC8051_ASS_ACC;
2582
          alu_op = `OC8051_ALU_OR;
2583
          wr = 1'b1;
2584
          psw_set = `OC8051_PS_NOT;
2585
          cy_sel = `OC8051_CY_0;
2586
          pc_wr = `OC8051_PCW_N;
2587
          pc_sel = `OC8051_PIS_DC;
2588
          imm_sel = `OC8051_IDS_DC;
2589
          src_sel3 = `OC8051_AS3_DC;
2590
          comp_sel = `OC8051_CSS_DC;
2591
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2592
          wad2 = `OC8051_WAD_N;
2593
          rom_addr_sel = `OC8051_RAS_PC;
2594
 
2595
        end
2596
      `OC8051_ORL_CD : begin
2597
          ram_rd_sel = `OC8051_RRS_D;
2598
          ram_wr_sel = `OC8051_RWS_D;
2599
          src_sel1 = `OC8051_ASS_IMM;
2600
          src_sel2 = `OC8051_ASS_RAM;
2601
          alu_op = `OC8051_ALU_OR;
2602
          wr = 1'b1;
2603
          psw_set = `OC8051_PS_NOT;
2604
          cy_sel = `OC8051_CY_0;
2605
          pc_wr = `OC8051_PCW_N;
2606
          pc_sel = `OC8051_PIS_DC;
2607
          imm_sel = `OC8051_IDS_OP3;
2608
          src_sel3 = `OC8051_AS3_DC;
2609
          comp_sel = `OC8051_CSS_DC;
2610
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2611
          wad2 = `OC8051_WAD_N;
2612
          rom_addr_sel = `OC8051_RAS_PC;
2613
 
2614
        end
2615
      `OC8051_ORL_B : begin
2616
          ram_rd_sel = `OC8051_RRS_D;
2617
          ram_wr_sel = `OC8051_RWS_DC;
2618
          src_sel1 = `OC8051_ASS_DC;
2619
          src_sel2 = `OC8051_ASS_DC;
2620
          alu_op = `OC8051_ALU_OR;
2621
          wr = 1'b0;
2622
          psw_set = `OC8051_PS_CY;
2623
          cy_sel = `OC8051_CY_PSW;
2624
          pc_wr = `OC8051_PCW_N;
2625
          pc_sel = `OC8051_PIS_DC;
2626
          imm_sel = `OC8051_IDS_DC;
2627
          src_sel3 = `OC8051_AS3_DC;
2628
          comp_sel = `OC8051_CSS_DC;
2629
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
2630
          wad2 = `OC8051_WAD_N;
2631
          rom_addr_sel = `OC8051_RAS_PC;
2632
 
2633
        end
2634
      `OC8051_ORL_NB : begin
2635
          ram_rd_sel = `OC8051_RRS_D;
2636
          ram_wr_sel = `OC8051_RWS_DC;
2637
          src_sel1 = `OC8051_ASS_DC;
2638
          src_sel2 = `OC8051_ASS_DC;
2639
          alu_op = `OC8051_ALU_RL;
2640
          wr = 1'b0;
2641
          psw_set = `OC8051_PS_CY;
2642
          cy_sel = `OC8051_CY_PSW;
2643
          pc_wr = `OC8051_PCW_N;
2644
          pc_sel = `OC8051_PIS_DC;
2645
          imm_sel = `OC8051_IDS_DC;
2646
          src_sel3 = `OC8051_AS3_DC;
2647
          comp_sel = `OC8051_CSS_DC;
2648
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
2649
          wad2 = `OC8051_WAD_N;
2650
          rom_addr_sel = `OC8051_RAS_PC;
2651
 
2652
        end
2653
      `OC8051_POP : begin
2654
          ram_rd_sel = `OC8051_RRS_SP;
2655
          ram_wr_sel = `OC8051_RWS_D;
2656
          src_sel1 = `OC8051_ASS_RAM;
2657
          src_sel2 = `OC8051_ASS_DC;
2658
          alu_op = `OC8051_ALU_NOP;
2659
          wr = 1'b1;
2660
          psw_set = `OC8051_PS_NOT;
2661
          cy_sel = `OC8051_CY_0;
2662
          pc_wr = `OC8051_PCW_N;
2663
          pc_sel = `OC8051_PIS_DC;
2664
          imm_sel = `OC8051_IDS_DC;
2665
          src_sel3 = `OC8051_AS3_DC;
2666
          comp_sel = `OC8051_CSS_DC;
2667
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2668
          wad2 = `OC8051_WAD_N;
2669
          rom_addr_sel = `OC8051_RAS_PC;
2670
 
2671
        end
2672
      `OC8051_PUSH : begin
2673
          ram_rd_sel = `OC8051_RRS_D;
2674
          ram_wr_sel = `OC8051_RWS_SP;
2675
          src_sel1 = `OC8051_ASS_RAM;
2676
          src_sel2 = `OC8051_ASS_DC;
2677
          alu_op = `OC8051_ALU_NOP;
2678
          wr = 1'b1;
2679
          psw_set = `OC8051_PS_NOT;
2680
          cy_sel = `OC8051_CY_0;
2681
          pc_wr = `OC8051_PCW_N;
2682
          pc_sel = `OC8051_PIS_DC;
2683
          imm_sel = `OC8051_IDS_DC;
2684
          src_sel3 = `OC8051_AS3_DC;
2685
          comp_sel = `OC8051_CSS_DC;
2686
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2687
          wad2 = `OC8051_WAD_N;
2688
          rom_addr_sel = `OC8051_RAS_PC;
2689
 
2690
        end
2691
      `OC8051_RET : begin
2692
          ram_rd_sel = `OC8051_RRS_SP;
2693
          ram_wr_sel = `OC8051_RWS_DC;
2694
          src_sel1 = `OC8051_ASS_RAM;
2695
          src_sel2 = `OC8051_ASS_DC;
2696
          alu_op = `OC8051_ALU_NOP;
2697
          wr = 1'b0;
2698
          psw_set = `OC8051_PS_NOT;
2699
          cy_sel = `OC8051_CY_0;
2700
          pc_wr = `OC8051_PCW_N;
2701
          pc_sel = `OC8051_PIS_DC;
2702
          imm_sel = `OC8051_IDS_DC;
2703
          src_sel3 = `OC8051_AS3_DC;
2704
          comp_sel = `OC8051_CSS_DC;
2705
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2706
          wad2 = `OC8051_WAD_N;
2707
          rom_addr_sel = `OC8051_RAS_PC;
2708
 
2709
        end
2710
      `OC8051_RETI : begin
2711
          ram_rd_sel = `OC8051_RRS_SP;
2712
          ram_wr_sel = `OC8051_RWS_DC;
2713
          src_sel1 = `OC8051_ASS_RAM;
2714
          src_sel2 = `OC8051_ASS_DC;
2715
          alu_op = `OC8051_ALU_NOP;
2716
          wr = 1'b0;
2717
          psw_set = `OC8051_PS_NOT;
2718
          cy_sel = `OC8051_CY_0;
2719
          pc_wr = `OC8051_PCW_N;
2720
          pc_sel = `OC8051_PIS_DC;
2721
          imm_sel = `OC8051_IDS_DC;
2722
          src_sel3 = `OC8051_AS3_DC;
2723
          comp_sel = `OC8051_CSS_DC;
2724
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2725
          wad2 = `OC8051_WAD_N;
2726
          rom_addr_sel = `OC8051_RAS_PC;
2727
 
2728
        end
2729
      `OC8051_RL : begin
2730
          ram_rd_sel = `OC8051_RRS_DC;
2731
          ram_wr_sel = `OC8051_RWS_ACC;
2732
          src_sel1 = `OC8051_ASS_ACC;
2733
          src_sel2 = `OC8051_ASS_DC;
2734
          alu_op = `OC8051_ALU_RL;
2735
          wr = 1'b1;
2736
          psw_set = `OC8051_PS_NOT;
2737
          cy_sel = `OC8051_CY_0;
2738
          pc_wr = `OC8051_PCW_N;
2739
          pc_sel = `OC8051_PIS_DC;
2740
          imm_sel = `OC8051_IDS_DC;
2741
          src_sel3 = `OC8051_AS3_DC;
2742
          comp_sel = `OC8051_CSS_DC;
2743
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2744
          wad2 = `OC8051_WAD_N;
2745
          rom_addr_sel = `OC8051_RAS_PC;
2746
 
2747
        end
2748
      `OC8051_RLC : begin
2749
          ram_rd_sel = `OC8051_RRS_DC;
2750
          ram_wr_sel = `OC8051_RWS_ACC;
2751
          src_sel1 = `OC8051_ASS_ACC;
2752
          src_sel2 = `OC8051_ASS_DC;
2753
          alu_op = `OC8051_ALU_RLC;
2754
          wr = 1'b1;
2755
          psw_set = `OC8051_PS_CY;
2756
          cy_sel = `OC8051_CY_PSW;
2757
          pc_wr = `OC8051_PCW_N;
2758
          pc_sel = `OC8051_PIS_DC;
2759
          imm_sel = `OC8051_IDS_DC;
2760
          src_sel3 = `OC8051_AS3_DC;
2761
          comp_sel = `OC8051_CSS_DC;
2762
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2763
          wad2 = `OC8051_WAD_N;
2764
          rom_addr_sel = `OC8051_RAS_PC;
2765
 
2766
        end
2767
      `OC8051_RR : begin
2768
          ram_rd_sel = `OC8051_RRS_DC;
2769
          ram_wr_sel = `OC8051_RWS_ACC;
2770
          src_sel1 = `OC8051_ASS_ACC;
2771
          src_sel2 = `OC8051_ASS_DC;
2772
          alu_op = `OC8051_ALU_RR;
2773
          wr = 1'b1;
2774
          psw_set = `OC8051_PS_NOT;
2775
          cy_sel = `OC8051_CY_0;
2776
          pc_wr = `OC8051_PCW_N;
2777
          pc_sel = `OC8051_PIS_DC;
2778
          imm_sel = `OC8051_IDS_DC;
2779
          src_sel3 = `OC8051_AS3_DC;
2780
          comp_sel = `OC8051_CSS_DC;
2781
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2782
          wad2 = `OC8051_WAD_N;
2783
          rom_addr_sel = `OC8051_RAS_PC;
2784
 
2785
        end
2786
      `OC8051_RRC : begin
2787
          ram_rd_sel = `OC8051_RRS_DC;
2788
          ram_wr_sel = `OC8051_RWS_ACC;
2789
          src_sel1 = `OC8051_ASS_ACC;
2790
          src_sel2 = `OC8051_ASS_DC;
2791
          alu_op = `OC8051_ALU_RRC;
2792
          wr = 1'b1;
2793
          psw_set = `OC8051_PS_CY;
2794
          cy_sel = `OC8051_CY_PSW;
2795
          pc_wr = `OC8051_PCW_N;
2796
          pc_sel = `OC8051_PIS_DC;
2797
          imm_sel = `OC8051_IDS_DC;
2798
          src_sel3 = `OC8051_AS3_DC;
2799
          comp_sel = `OC8051_CSS_DC;
2800
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2801
          wad2 = `OC8051_WAD_N;
2802
          rom_addr_sel = `OC8051_RAS_PC;
2803
 
2804
        end
2805
      `OC8051_SETB_C : begin
2806
          ram_rd_sel = `OC8051_RRS_DC;
2807
          ram_wr_sel = `OC8051_RWS_DC;
2808
          src_sel1 = `OC8051_ASS_DC;
2809
          src_sel2 = `OC8051_ASS_DC;
2810
          alu_op = `OC8051_ALU_NOP;
2811
          wr = 1'b0;
2812
          psw_set = `OC8051_PS_CY;
2813
          cy_sel = `OC8051_CY_1;
2814
          pc_wr = `OC8051_PCW_N;
2815
          pc_sel = `OC8051_PIS_DC;
2816
          imm_sel = `OC8051_IDS_DC;
2817
          src_sel3 = `OC8051_AS3_PC;
2818
          comp_sel = `OC8051_CSS_DC;
2819
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2820
          wad2 = `OC8051_WAD_N;
2821
          rom_addr_sel = `OC8051_RAS_PC;
2822
 
2823
        end
2824
      `OC8051_SETB_B : begin
2825
          ram_rd_sel = `OC8051_RRS_D;
2826
          ram_wr_sel = `OC8051_RWS_D;
2827
          src_sel1 = `OC8051_ASS_DC;
2828
          src_sel2 = `OC8051_ASS_DC;
2829
          alu_op = `OC8051_ALU_NOP;
2830
          wr = 1'b1;
2831
          psw_set = `OC8051_PS_NOT;
2832
          cy_sel = `OC8051_CY_1;
2833
          pc_wr = `OC8051_PCW_N;
2834
          pc_sel = `OC8051_PIS_DC;
2835
          imm_sel = `OC8051_IDS_DC;
2836
          src_sel3 = `OC8051_AS3_PC;
2837
          comp_sel = `OC8051_CSS_DC;
2838
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
2839
          wad2 = `OC8051_WAD_N;
2840
          rom_addr_sel = `OC8051_RAS_PC;
2841
 
2842
        end
2843
      `OC8051_SJMP : begin
2844
          ram_rd_sel = `OC8051_RRS_DC;
2845
          ram_wr_sel = `OC8051_RWS_DC;
2846
          src_sel1 = `OC8051_ASS_IMM;
2847
          src_sel2 = `OC8051_ASS_IMM;
2848
          alu_op = `OC8051_ALU_PCS;
2849
          wr = 1'b0;
2850
          psw_set = `OC8051_PS_NOT;
2851
          cy_sel = `OC8051_CY_0;
2852
          pc_wr = `OC8051_PCW_N;
2853
          pc_sel = `OC8051_PIS_DC;
2854
          imm_sel = `OC8051_IDS_OP2_PCL;
2855
          src_sel3 = `OC8051_AS3_PC;
2856
          comp_sel = `OC8051_CSS_DC;
2857
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2858
          wad2 = `OC8051_WAD_N;
2859
          rom_addr_sel = `OC8051_RAS_PC;
2860
 
2861
        end
2862
      `OC8051_SUBB_D : begin
2863
          ram_rd_sel = `OC8051_RRS_D;
2864
          ram_wr_sel = `OC8051_RWS_ACC;
2865
          src_sel1 = `OC8051_ASS_ACC;
2866
          src_sel2 = `OC8051_ASS_RAM;
2867
          alu_op = `OC8051_ALU_SUB;
2868
          wr = 1'b1;
2869
          psw_set = `OC8051_PS_AC;
2870
          cy_sel = `OC8051_CY_PSW;
2871
          pc_wr = `OC8051_PCW_N;
2872
          pc_sel = `OC8051_PIS_DC;
2873
          imm_sel = `OC8051_IDS_DC;
2874
          src_sel3 = `OC8051_AS3_DC;
2875
          comp_sel = `OC8051_CSS_DC;
2876
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2877
          wad2 = `OC8051_WAD_N;
2878
          rom_addr_sel = `OC8051_RAS_PC;
2879
 
2880
        end
2881
      `OC8051_SUBB_C : begin
2882
          ram_rd_sel = `OC8051_RRS_DC;
2883
          ram_wr_sel = `OC8051_RWS_ACC;
2884
          src_sel1 = `OC8051_ASS_ACC;
2885
          src_sel2 = `OC8051_ASS_IMM;
2886
          alu_op = `OC8051_ALU_SUB;
2887
          wr = 1'b1;
2888
          psw_set = `OC8051_PS_AC;
2889
          cy_sel = `OC8051_CY_PSW;
2890
          pc_wr = `OC8051_PCW_N;
2891
          pc_sel = `OC8051_PIS_DC;
2892
          imm_sel = `OC8051_IDS_OP2;
2893
          src_sel3 = `OC8051_AS3_DC;
2894
          comp_sel = `OC8051_CSS_DC;
2895
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2896
          wad2 = `OC8051_WAD_N;
2897
          rom_addr_sel = `OC8051_RAS_PC;
2898
 
2899
        end
2900
      `OC8051_SWAP : begin
2901
          ram_rd_sel = `OC8051_RRS_DC;
2902
          ram_wr_sel = `OC8051_RWS_DC;
2903
          src_sel1 = `OC8051_ASS_ACC;
2904
          src_sel2 = `OC8051_ASS_DC;
2905
          alu_op = `OC8051_ALU_RLC;
2906
          wr = 1'b0;
2907
          psw_set = `OC8051_PS_NOT;
2908
          cy_sel = `OC8051_CY_0;
2909
          pc_wr = `OC8051_PCW_N;
2910
          pc_sel = `OC8051_PIS_DC;
2911
          imm_sel = `OC8051_IDS_DC;
2912
          src_sel3 = `OC8051_AS3_DC;
2913
          comp_sel = `OC8051_CSS_DC;
2914
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2915
          wad2 = `OC8051_WAD_Y;
2916
          rom_addr_sel = `OC8051_RAS_PC;
2917
 
2918
        end
2919
      `OC8051_XCH_D : begin
2920
          ram_rd_sel = `OC8051_RRS_D;
2921
          ram_wr_sel = `OC8051_RWS_D;
2922
          src_sel1 = `OC8051_ASS_RAM;
2923
          src_sel2 = `OC8051_ASS_ACC;
2924
          alu_op = `OC8051_ALU_XCH;
2925
          wr = 1'b1;
2926
          psw_set = `OC8051_PS_NOT;
2927
          cy_sel = `OC8051_CY_1;
2928
          pc_wr = `OC8051_PCW_N;
2929
          pc_sel = `OC8051_PIS_DC;
2930
          imm_sel = `OC8051_IDS_DC;
2931
          src_sel3 = `OC8051_AS3_DC;
2932
          comp_sel = `OC8051_CSS_DC;
2933
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2934
          wad2 = `OC8051_WAD_Y;
2935
          rom_addr_sel = `OC8051_RAS_PC;
2936
 
2937
        end
2938
      `OC8051_XRL_D : begin
2939
          ram_rd_sel = `OC8051_RRS_D;
2940
          ram_wr_sel = `OC8051_RWS_ACC;
2941
          src_sel1 = `OC8051_ASS_RAM;
2942
          src_sel2 = `OC8051_ASS_ACC;
2943
          alu_op = `OC8051_ALU_XOR;
2944
          wr = 1'b1;
2945
          psw_set = `OC8051_PS_NOT;
2946
          cy_sel = `OC8051_CY_0;
2947
          pc_wr = `OC8051_PCW_N;
2948
          pc_sel = `OC8051_PIS_DC;
2949
          imm_sel = `OC8051_IDS_DC;
2950
          src_sel3 = `OC8051_AS3_DC;
2951
          comp_sel = `OC8051_CSS_DC;
2952
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2953
          wad2 = `OC8051_WAD_N;
2954
          rom_addr_sel = `OC8051_RAS_PC;
2955
 
2956
        end
2957
      `OC8051_XRL_C : begin
2958
          ram_rd_sel = `OC8051_RRS_DC;
2959
          ram_wr_sel = `OC8051_RWS_ACC;
2960
          src_sel1 = `OC8051_ASS_IMM;
2961
          src_sel2 = `OC8051_ASS_ACC;
2962
          alu_op = `OC8051_ALU_XOR;
2963
          wr = 1'b1;
2964
          psw_set = `OC8051_PS_NOT;
2965
          cy_sel = `OC8051_CY_0;
2966
          pc_wr = `OC8051_PCW_N;
2967
          pc_sel = `OC8051_PIS_DC;
2968
          imm_sel = `OC8051_IDS_OP2;
2969
          src_sel3 = `OC8051_AS3_DC;
2970
          comp_sel = `OC8051_CSS_DC;
2971
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2972
          wad2 = `OC8051_WAD_N;
2973
          rom_addr_sel = `OC8051_RAS_PC;
2974
 
2975
        end
2976
      `OC8051_XRL_AD : begin
2977
          ram_rd_sel = `OC8051_RRS_D;
2978
          ram_wr_sel = `OC8051_RWS_D;
2979
          src_sel1 = `OC8051_ASS_RAM;
2980
          src_sel2 = `OC8051_ASS_ACC;
2981
          alu_op = `OC8051_ALU_XOR;
2982
          wr = 1'b1;
2983
          psw_set = `OC8051_PS_NOT;
2984
          cy_sel = `OC8051_CY_0;
2985
          pc_wr = `OC8051_PCW_N;
2986
          pc_sel = `OC8051_PIS_DC;
2987
          imm_sel = `OC8051_IDS_DC;
2988
          src_sel3 = `OC8051_AS3_DC;
2989
          comp_sel = `OC8051_CSS_DC;
2990
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2991
          wad2 = `OC8051_WAD_N;
2992
          rom_addr_sel = `OC8051_RAS_PC;
2993
 
2994
        end
2995
      `OC8051_XRL_CD : begin
2996
          ram_rd_sel = `OC8051_RRS_D;
2997
          ram_wr_sel = `OC8051_RWS_D;
2998
          src_sel1 = `OC8051_ASS_IMM;
2999
          src_sel2 = `OC8051_ASS_RAM;
3000
          alu_op = `OC8051_ALU_XOR;
3001
          wr = 1'b1;
3002
          psw_set = `OC8051_PS_NOT;
3003
          cy_sel = `OC8051_CY_0;
3004
          pc_wr = `OC8051_PCW_N;
3005
          pc_sel = `OC8051_PIS_DC;
3006
          imm_sel = `OC8051_IDS_OP3;
3007
          src_sel3 = `OC8051_AS3_DC;
3008
          comp_sel = `OC8051_CSS_DC;
3009
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
3010
          wad2 = `OC8051_WAD_N;
3011
          rom_addr_sel = `OC8051_RAS_PC;
3012
 
3013
        end
3014
      default: begin
3015
          ram_rd_sel = `OC8051_RRS_DC;
3016
          ram_wr_sel = `OC8051_RWS_DC;
3017
          src_sel1 = `OC8051_ASS_DC;
3018
          src_sel2 = `OC8051_ASS_DC;
3019
          alu_op = `OC8051_ALU_NOP;
3020
          imm_sel = `OC8051_IDS_DC;
3021
          wr = 1'b0;
3022
          psw_set = `OC8051_PS_NOT;
3023
          cy_sel = `OC8051_CY_0;
3024
          pc_wr = `OC8051_PCW_N;
3025
          pc_sel = `OC8051_PIS_DC;
3026
          src_sel3 = `OC8051_AS3_DC;
3027
          comp_sel = `OC8051_CSS_DC;
3028
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
3029
          wad2 = `OC8051_WAD_N;
3030
          rom_addr_sel = `OC8051_RAS_PC;
3031
 
3032
       end
3033
 
3034
    endcase
3035
    end
3036
    endcase
3037
  end
3038
end
3039
 
3040
//
3041
// remember current instruction
3042
always @(posedge clk or posedge rst)
3043
  if (rst) op <= #1 2'b00;
3044
  else if (state==2'b00) op <= #1 op_in;
3045
 
3046
//
3047
// in case of instructions that needs more than one clock set state
3048
always @(posedge clk or posedge rst)
3049
begin
3050
  if (rst)
3051
    state <= #1 2'b01;
3052
  else begin
3053
    case (state)
3054
      2'b10: state <= #1 2'b01;
3055
      2'b11: state <= #1 2'b10;
3056
      2'b00:
3057
        casex (op_in)
3058
          `OC8051_ACALL :state <= #1 2'b01;
3059
          `OC8051_AJMP : state <= #1 2'b01;
3060
          `OC8051_CJNE_R :state <= #1 2'b11;
3061
          `OC8051_CJNE_I :state <= #1 2'b11;
3062
          `OC8051_CJNE_D : state <= #1 2'b11;
3063
          `OC8051_CJNE_C : state <= #1 2'b11;
3064
          `OC8051_LJMP : state <= #1 2'b01;
3065
          `OC8051_DJNZ_R :state <= #1 2'b11;
3066
          `OC8051_DJNZ_D :state <= #1 2'b11;
3067
          `OC8051_LCALL :state <= #1 2'b01;
3068
          `OC8051_MOVC_DP :state <= #1 2'b10;
3069
          `OC8051_MOVC_PC :state <= #1 2'b10;
3070
          `OC8051_RET : state <= #1 2'b11;
3071
          `OC8051_RETI : state <= #1 2'b11;
3072
          `OC8051_SJMP : state <= #1 2'b10;
3073
          `OC8051_JB : state <= #1 2'b10;
3074
          `OC8051_JBC : state <= #1 2'b10;
3075
          `OC8051_JC : state <= #1 2'b10;
3076
          `OC8051_JMP : state <= #1 2'b10;
3077
          `OC8051_JNC : state <= #1 2'b10;
3078
          `OC8051_JNB : state <= #1 2'b10;
3079
          `OC8051_JNZ : state <= #1 2'b10;
3080
          `OC8051_JZ : state <= #1 2'b10;
3081
          `OC8051_DIV : state <= #1 2'b11;
3082
          `OC8051_MUL : state <= #1 2'b11;
3083
          default: state <= #1 2'b00;
3084
        endcase
3085
      default: state <= #1 2'b00;
3086
    endcase
3087
  end
3088
end
3089
 
3090
//
3091
//in case of reti
3092
always @(posedge clk or posedge rst)
3093
  if (rst) reti <= #1 1'b0;
3094
  else if (op==`OC8051_RETI) reti <= #1 1'b1;
3095
  else reti <= #1 1'b0;
3096
 
3097
//
3098
//in case of writing to external ram
3099
always @(op_in or rd)
3100
begin
3101
  if (rd)
3102
  begin
3103
    casex (op_in)
3104
      `OC8051_MOVX_AI : begin
3105
        stb = 1'b0;
3106
        write_x = 1'b1;
3107
      end
3108
      `OC8051_MOVX_AP : begin
3109
        stb = 1'b0;
3110
        write_x = 1'b1;
3111
      end
3112
      `OC8051_MOVX_IA : begin
3113
        stb = 1'b1;
3114
        write_x = 1'b0;
3115
      end
3116
      `OC8051_MOVX_PA : begin
3117
        stb = 1'b1;
3118
        write_x = 1'b0;
3119
      end
3120
      default : begin
3121
        stb = 1'b0;
3122
        write_x = 1'b0;
3123
      end
3124
    endcase
3125
  end else begin
3126
    write_x = 1'b0;
3127
    stb =1'b0;
3128
  end
3129
end
3130
 
3131
always @(op_in)
3132
begin
3133
  casex (op_in)
3134
    `OC8051_MOVX_AI : begin
3135
      ext_addr_sel = `OC8051_EAS_RI;
3136
      wr_xaddr = 1'b1;
3137
    end
3138
    `OC8051_MOVX_AP : begin
3139
      ext_addr_sel =  `OC8051_EAS_DPTR;
3140
      wr_xaddr = 1'b1;
3141
    end
3142
    `OC8051_MOVX_IA : begin
3143
      ext_addr_sel = `OC8051_EAS_RI;
3144
      wr_xaddr = 1'b1;
3145
    end
3146
    `OC8051_MOVX_PA : begin
3147
      ext_addr_sel = `OC8051_EAS_DPTR;
3148
      wr_xaddr = 1'b1;
3149
    end
3150
    default: begin
3151
      wr_xaddr = 1'b0;
3152
      ext_addr_sel = `OC8051_EAS_DPTR;
3153
    end
3154
  endcase
3155
end
3156
 
3157
 
3158
 
3159
always @(posedge clk or posedge rst)
3160
begin
3161
  if (rst) begin
3162
    stbw <= #1 1'b0;
3163
  end else
3164
    stbw <= #1 write_x;
3165
end
3166
 
3167
 
3168
always @(posedge clk or posedge rst)
3169
begin
3170
  if (rst) begin
3171
    stb_buff <= #1 1'b0;
3172
    we_buff <= #1 1'b0;
3173
  end else if (ack_i) begin
3174
    stb_buff <= #1 1'b0;
3175
    we_buff <= #1 1'b0;
3176
  end else if (stb || stbw) begin
3177
    stb_buff <= #1 1'b1;
3178
  end else if (write_x) begin
3179
    we_buff <= #1 1'b1;
3180
  end
3181
end
3182
 
3183
 
3184
endmodule
3185
 
3186
 

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