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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 instruction cache                                      ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////  8051 instruction cache                                      ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2003/01/21 14:08:18  simont
// fix bugs
//
// Revision 1.3  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.2  2002/10/24 13:34:02  simont
// add parameters for instruction cache
//
// Revision 1.1  2002/10/23 16:55:36  simont
// fix bugs in instruction interface
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
 
module oc8051_icache (rst, clk, adr_i, dat_o,stb_i, ack_o, cyc_i,
        dat_i, cyc_o, adr_o, ack_i, stb_o);
//
// rst           (in)  reset - pin
// clk           (in)  clock - pini
input rst, clk;
 
//
// interface to oc8051 cpu
//
// adr_i    (in)  address
// dat_o    (out) data output
// stb_i    (in)  strobe
// ack_o    (out) acknowledge
// cyc_i    (in)  cycle
input stb_i, cyc_i;
input [15:0] adr_i;
output ack_o;
output [31:0] dat_o;
reg [31:0] dat_o;
 
//
// interface to instruction rom
//
// adr_o    (out) address
// dat_i    (in)  data input
// stb_o    (out) strobe
// ack_i    (in) acknowledge
// cyc_o    (out)  cycle
input ack_i;
input [31:0] dat_i;
output stb_o, cyc_o;
output [15:0] adr_o;
//reg [15:0] adr_o;
reg stb_o, cyc_o;
 
parameter ADR_WIDTH = 6; // cache address wihth
parameter LINE_WIDTH = 2; // line address width (2 => 4x32)
parameter BL_WIDTH = ADR_WIDTH - LINE_WIDTH; // block address width
parameter BL_NUM = 15; // number of blocks (2^BL_WIDTH-1)
parameter CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)
 
//
// internal buffers adn wires
//
// con_buf control buffer, contains upper addresses [15:ADDR_WIDTH1] in cache
reg [13-ADR_WIDTH:0] con_buf [BL_NUM:0];
// valid[x]=1 if block x is valid;
reg [BL_NUM:0] valid;
// con0, con2 contain temporal control information of current address and corrent address+2
// part of con_buf memory
reg [14-ADR_WIDTH:0] con0, con2;
//current upper address,
reg [13-ADR_WIDTH:0] cadr0, cadr2;
reg stb_b;
// byte_select in 32 bit line (adr_i[1:0])
reg [1:0] byte_sel;
// read cycle
reg [LINE_WIDTH-1:0] cyc;
// data input from cache ram
reg [31:0] data1_i;
// temporaly data from ram
reg [15:0] tmp_data1;
reg wr1, wr1_t, stb_it;
 
wire [31:0] data0, data1_o;
wire cy, cy1;
wire [BL_WIDTH-1:0] adr_i2;
wire hit, hit_l, hit_h;
wire [ADR_WIDTH-1:0] adr_r, addr1;
reg [ADR_WIDTH-1:0] adr_w;
reg [15:0] mis_adr;
wire [15:0] data1;
wire [LINE_WIDTH-1:0] adr_r1;
 
 
assign cy = &adr_i[LINE_WIDTH+1:1];
assign {cy1, adr_i2} = {1'b0, adr_i[ADR_WIDTH+1:LINE_WIDTH+2]}+cy;
assign hit_l =(con0=={cadr0,1'b1});
assign hit_h =(con2=={cadr2,1'b1});
assign hit = hit_l && hit_h;
 
assign adr_r = adr_i[ADR_WIDTH+1:2] + adr_i[1];
assign addr1 = wr1 ? adr_w : adr_r;
assign adr_r1 = adr_r[LINE_WIDTH-1:0] + 2'b01;
//assign ack_o = hit;
assign ack_o = hit && stb_it;
 
assign data1 = wr1_t ? tmp_data1 : data1_o[31:16];
 
assign adr_o = {mis_adr[15:LINE_WIDTH+2], cyc, 2'b00};
 
 
oc8051_cache_ram oc8051_cache_ram1(.clk(clk), .rst(rst), .addr0(adr_i[ADR_WIDTH+1:2]),
       .addr1(addr1), .data0(data0), .data1_o(data1_o), .data1_i(data1_i),
       .wr1(wr1));
 
defparam oc8051_cache_ram1.ADR_WIDTH = ADR_WIDTH;
defparam oc8051_cache_ram1.CACHE_RAM = CACHE_RAM;
 
always @(stb_b or data0 or data1 or byte_sel)
begin
  if (stb_b) begin
    case (byte_sel)
      2'b00  : dat_o = data0;
      2'b01  : dat_o = {data0[23:0], data1[15:8]};
      2'b10  : dat_o = {data0[15:0], data1};
      default: dat_o = {data0[ 7:0], data1, 8'h00};
    endcase
  end else begin
    dat_o = 32'h0;
  end
end
 
always @(posedge clk or posedge rst)
begin
  if (rst)
    begin
        con0 <= #1 9'h0;
        con2 <= #1 9'h0;
    end
  else
    begin
        con0 <= #1 {con_buf[adr_i[ADR_WIDTH+1:LINE_WIDTH+2]], valid[adr_i[ADR_WIDTH+1:LINE_WIDTH+2]]};
        con2 <= #1 {con_buf[adr_i2], valid[adr_i2]};
    end
end
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    cadr0 <= #1 8'h00;
    cadr2 <= #1 8'h00;
  end else begin
    cadr0 <= #1 adr_i[15:ADR_WIDTH+2];
    cadr2 <= #1 adr_i[15:ADR_WIDTH+2]+ cy1;
  end
end
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    stb_b <= #1 1'b0;
    byte_sel <= #1 2'b00;
  end else begin
    stb_b <= #1 stb_i;
    byte_sel <= #1 adr_i[1:0];
  end
end
 
always @(posedge clk or posedge rst)
begin
  if (rst)
    begin
        cyc    <= #1 2'b00;
        cyc_o  <= #1 1'b0;
        stb_o  <= #1 1'b0;
        data1_i<= #1 32'h0;
        wr1    <= #1 1'b0;
        adr_w  <= #1 6'h0;
        valid  <= #1 16'h0;
    end
  else if (stb_b && !hit && !stb_o && !wr1)
    begin
        cyc     <= #1 2'b00;
        cyc_o   <= #1 1'b1;
        stb_o   <= #1 1'b1;
        data1_i <= #1 32'h0;
        wr1     <= #1 1'b0;
    end
  else if (stb_o && ack_i)
    begin
        data1_i<= #1 dat_i;
        wr1    <= #1 1'b1;
        adr_w  <= #1 adr_o[ADR_WIDTH+1:2];
 
        if (&cyc)
          begin
              cyc   <= #1 2'b00;
              cyc_o <= #1 1'b0;
              stb_o <= #1 1'b0;
//              con_buf[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 mis_adr[15:ADR_WIDTH+2];
              valid[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 1'b1;
          end
        else
          begin
              cyc   <= #1 cyc + 1'b1;
              cyc_o <= #1 1'b1;
              stb_o <= #1 1'b1;
          end
 
 
/*    case (cyc)
      2'b00: begin
        cyc <= #1 2'b01;
        cyc_o <= #1 1'b1;
        stb_o <= #1 1'b1;
      end
      2'b01: begin
        cyc <= #1 2'b10;
        cyc_o <= #1 1'b1;
        stb_o <= #1 1'b1;
      end
      2'b10: begin
        cyc <= #1 2'b11;
        cyc_o <= #1 1'b1;
        stb_o <= #1 1'b1;
      end
      default: begin
        cyc <= #1 2'b00;
        cyc_o <= #1 1'b0;
        stb_o <= #1 1'b0;
        con_buf[mis_adr[7:4]] <= #1 mis_adr[15:8];
        valid[mis_adr[7:4]] <= #1 1'b1;
      end
    endcase*/
    end
  else
    wr1 <= #1 1'b0;
end
 
//rih
always @(posedge clk)
  if ( ~(stb_b && !hit && !stb_o && !wr1) & (stb_o && ack_i && cyc) )
    con_buf[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 mis_adr[15:ADR_WIDTH+2];
 
 
always @(posedge clk or posedge rst)
begin
  if (rst)
    mis_adr <= #1 1'b0;
  else if (!hit_l)
    mis_adr <= #1 adr_i;
  else if (!hit_h)
    mis_adr <= #1 adr_i+'d2;
end
 
always @(posedge clk or posedge rst)
begin
  if (rst)
    tmp_data1 <= #1 1'b0;
  else if (!hit_h && wr1 && (cyc==adr_r1))
    tmp_data1 <= #1 dat_i[31:16];
  else if (!hit_l && hit_h && wr1)
    tmp_data1 <= #1 data1_o[31:16];
end
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    wr1_t <= #1 1'b0;
    stb_it <= #1 1'b0;
  end else begin
    wr1_t <= #1 wr1;
    stb_it <= #1 stb_i;
  end
end
 
endmodule
 

Line No.	Rev	Author	Line
1	67	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 instruction cache ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 8051 instruction cache ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43	62	simont	`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	94	simont	`// Revision 1.4 2003/01/21 14:08:18 simont`
48			`// fix bugs`
49			`//`
50	88	simont	`// Revision 1.3 2003/01/13 14:14:41 simont`
51			`// replace some modules`
52			`//`
53	82	simont	`// Revision 1.2 2002/10/24 13:34:02 simont`
54			`// add parameters for instruction cache`
55			`//`
56	67	simont	`// Revision 1.1 2002/10/23 16:55:36 simont`
57			`// fix bugs in instruction interface`
58	62	simont	`//`
59	67	simont	`//`
60	62	simont
61			`// synopsys translate_off`
62			`include "oc8051_timescale.v"
63			`// synopsys translate_on`
64
65
66			`module oc8051_icache (rst, clk, adr_i, dat_o,stb_i, ack_o, cyc_i,`
67			`dat_i, cyc_o, adr_o, ack_i, stb_o);`
68			`//`
69			`// rst (in) reset - pin`
70			`// clk (in) clock - pini`
71			`input rst, clk;`
72
73			`//`
74			`// interface to oc8051 cpu`
75			`//`
76			`// adr_i (in) address`
77			`// dat_o (out) data output`
78			`// stb_i (in) strobe`
79			`// ack_o (out) acknowledge`
80			`// cyc_i (in) cycle`
81			`input stb_i, cyc_i;`
82			`input [15:0] adr_i;`
83			`output ack_o;`
84			`output [31:0] dat_o;`
85			`reg [31:0] dat_o;`
86
87			`//`
88			`// interface to instruction rom`
89			`//`
90			`// adr_o (out) address`
91			`// dat_i (in) data input`
92			`// stb_o (out) strobe`
93			`// ack_i (in) acknowledge`
94			`// cyc_o (out) cycle`
95			`input ack_i;`
96			`input [31:0] dat_i;`
97			`output stb_o, cyc_o;`
98			`output [15:0] adr_o;`
99	67	simont	`//reg [15:0] adr_o;`
100	62	simont	`reg stb_o, cyc_o;`
101
102	67	simont	`parameter ADR_WIDTH = 6; // cache address wihth`
103			`parameter LINE_WIDTH = 2; // line address width (2 => 4x32)`
104			`parameter BL_WIDTH = ADR_WIDTH - LINE_WIDTH; // block address width`
105			`parameter BL_NUM = 15; // number of blocks (2^BL_WIDTH-1)`
106			`parameter CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)`
107
108	62	simont	`//`
109			`// internal buffers adn wires`
110			`//`
111	67	simont	`// con_buf control buffer, contains upper addresses [15:ADDR_WIDTH1] in cache`
112			`reg [13-ADR_WIDTH:0] con_buf [BL_NUM:0];`
113	88	simont	`// valid[x]=1 if block x is valid;`
114			`reg [BL_NUM:0] valid;`
115	62	simont	`// con0, con2 contain temporal control information of current address and corrent address+2`
116	67	simont	`// part of con_buf memory`
117			`reg [14-ADR_WIDTH:0] con0, con2;`
118			`//current upper address,`
119			`reg [13-ADR_WIDTH:0] cadr0, cadr2;`
120	62	simont	`reg stb_b;`
121	67	simont	`// byte_select in 32 bit line (adr_i[1:0])`
122	62	simont	`reg [1:0] byte_sel;`
123	67	simont	`// read cycle`
124			`reg [LINE_WIDTH-1:0] cyc;`
125			`// data input from cache ram`
126	62	simont	`reg [31:0] data1_i;`
127	67	simont	`// temporaly data from ram`
128	62	simont	`reg [15:0] tmp_data1;`
129			`reg wr1, wr1_t, stb_it;`
130
131			`wire [31:0] data0, data1_o;`
132			`wire cy, cy1;`
133	67	simont	`wire [BL_WIDTH-1:0] adr_i2;`
134	62	simont	`wire hit, hit_l, hit_h;`
135	67	simont	`wire [ADR_WIDTH-1:0] adr_r, addr1;`
136			`reg [ADR_WIDTH-1:0] adr_w;`
137	62	simont	`reg [15:0] mis_adr;`
138			`wire [15:0] data1;`
139	67	simont	`wire [LINE_WIDTH-1:0] adr_r1;`
140	62	simont
141	67	simont
142			`assign cy = &adr_i[LINE_WIDTH+1:1];`
143			`assign {cy1, adr_i2} = {1'b0, adr_i[ADR_WIDTH+1:LINE_WIDTH+2]}+cy;`
144	62	simont	`assign hit_l =(con0=={cadr0,1'b1});`
145			`assign hit_h =(con2=={cadr2,1'b1});`
146			`assign hit = hit_l && hit_h;`
147
148	67	simont	`assign adr_r = adr_i[ADR_WIDTH+1:2] + adr_i[1];`
149	62	simont	`assign addr1 = wr1 ? adr_w : adr_r;`
150	67	simont	`assign adr_r1 = adr_r[LINE_WIDTH-1:0] + 2'b01;`
151	62	simont	`//assign ack_o = hit;`
152			`assign ack_o = hit && stb_it;`
153
154			`assign data1 = wr1_t ? tmp_data1 : data1_o[31:16];`
155
156	67	simont	`assign adr_o = {mis_adr[15:LINE_WIDTH+2], cyc, 2'b00};`
157
158
159			`oc8051_cache_ram oc8051_cache_ram1(.clk(clk), .rst(rst), .addr0(adr_i[ADR_WIDTH+1:2]),`
160			`.addr1(addr1), .data0(data0), .data1_o(data1_o), .data1_i(data1_i),`
161	62	simont	`.wr1(wr1));`
162
163	67	simont	`defparam oc8051_cache_ram1.ADR_WIDTH = ADR_WIDTH;`
164			`defparam oc8051_cache_ram1.CACHE_RAM = CACHE_RAM;`
165
166	62	simont	`always @(stb_b or data0 or data1 or byte_sel)`
167			`begin`
168			`if (stb_b) begin`
169			`case (byte_sel)`
170	88	simont	`2'b00 : dat_o = data0;`
171			`2'b01 : dat_o = {data0[23:0], data1[15:8]};`
172			`2'b10 : dat_o = {data0[15:0], data1};`
173			`default: dat_o = {data0[ 7:0], data1, 8'h00};`
174	62	simont	`endcase`
175	67	simont	`end else begin`
176	62	simont	`dat_o = 32'h0;`
177			`end`
178			`end`
179
180			`always @(posedge clk or posedge rst)`
181			`begin`
182	88	simont	`if (rst)`
183			`begin`
184			`con0 <= #1 9'h0;`
185			`con2 <= #1 9'h0;`
186			`end`
187			`else`
188			`begin`
189			`con0 <= #1 {con_buf[adr_i[ADR_WIDTH+1:LINE_WIDTH+2]], valid[adr_i[ADR_WIDTH+1:LINE_WIDTH+2]]};`
190			`con2 <= #1 {con_buf[adr_i2], valid[adr_i2]};`
191			`end`
192	62	simont	`end`
193
194			`always @(posedge clk or posedge rst)`
195			`begin`
196			`if (rst) begin`
197			`cadr0 <= #1 8'h00;`
198			`cadr2 <= #1 8'h00;`
199			`end else begin`
200	67	simont	`cadr0 <= #1 adr_i[15:ADR_WIDTH+2];`
201			`cadr2 <= #1 adr_i[15:ADR_WIDTH+2]+ cy1;`
202	62	simont	`end`
203			`end`
204
205			`always @(posedge clk or posedge rst)`
206			`begin`
207			`if (rst) begin`
208			`stb_b <= #1 1'b0;`
209	67	simont	`byte_sel <= #1 2'b00;`
210	62	simont	`end else begin`
211			`stb_b <= #1 stb_i;`
212			`byte_sel <= #1 adr_i[1:0];`
213			`end`
214			`end`
215
216			`always @(posedge clk or posedge rst)`
217			`begin`
218	88	simont	`if (rst)`
219			`begin`
220			`cyc <= #1 2'b00;`
221			`cyc_o <= #1 1'b0;`
222			`stb_o <= #1 1'b0;`
223			`data1_i<= #1 32'h0;`
224			`wr1 <= #1 1'b0;`
225			`adr_w <= #1 6'h0;`
226			`valid <= #1 16'h0;`
227			`end`
228			`else if (stb_b && !hit && !stb_o && !wr1)`
229			`begin`
230			`cyc <= #1 2'b00;`
231			`cyc_o <= #1 1'b1;`
232			`stb_o <= #1 1'b1;`
233			`data1_i <= #1 32'h0;`
234			`wr1 <= #1 1'b0;`
235			`end`
236			`else if (stb_o && ack_i)`
237			`begin`
238			`data1_i<= #1 dat_i;`
239			`wr1 <= #1 1'b1;`
240			`adr_w <= #1 adr_o[ADR_WIDTH+1:2];`
241
242			`if (&cyc)`
243			`begin`
244			`cyc <= #1 2'b00;`
245			`cyc_o <= #1 1'b0;`
246			`stb_o <= #1 1'b0;`
247			`// con_buf[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 mis_adr[15:ADR_WIDTH+2];`
248			`valid[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 1'b1;`
249			`end`
250			`else`
251			`begin`
252			`cyc <= #1 cyc + 1'b1;`
253			`cyc_o <= #1 1'b1;`
254			`stb_o <= #1 1'b1;`
255			`end`
256
257
258			`/* case (cyc)`
259			`2'b00: begin`
260			`cyc <= #1 2'b01;`
261			`cyc_o <= #1 1'b1;`
262			`stb_o <= #1 1'b1;`
263			`end`
264			`2'b01: begin`
265			`cyc <= #1 2'b10;`
266			`cyc_o <= #1 1'b1;`
267			`stb_o <= #1 1'b1;`
268			`end`
269			`2'b10: begin`
270			`cyc <= #1 2'b11;`
271			`cyc_o <= #1 1'b1;`
272			`stb_o <= #1 1'b1;`
273			`end`
274			`default: begin`
275	67	simont	`cyc <= #1 2'b00;`
276			`cyc_o <= #1 1'b0;`
277			`stb_o <= #1 1'b0;`
278	88	simont	`con_buf[mis_adr[7:4]] <= #1 mis_adr[15:8];`
279			`valid[mis_adr[7:4]] <= #1 1'b1;`
280			`end`
281			`endcase*/`
282	67	simont	`end`
283	88	simont	`else`
284	62	simont	`wr1 <= #1 1'b0;`
285			`end`
286
287	88	simont	`//rih`
288			`always @(posedge clk)`
289	94	simont	`if ( ~(stb_b && !hit && !stb_o && !wr1) & (stb_o && ack_i && cyc) )`
290	88	simont	`con_buf[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 mis_adr[15:ADR_WIDTH+2];`
291
292
293	62	simont	`always @(posedge clk or posedge rst)`
294			`begin`
295			`if (rst)`
296	88	simont	`mis_adr <= #1 1'b0;`
297	62	simont	`else if (!hit_l)`
298			`mis_adr <= #1 adr_i;`
299			`else if (!hit_h)`
300	67	simont	`mis_adr <= #1 adr_i+'d2;`
301			`end`
302	62	simont
303			`always @(posedge clk or posedge rst)`
304			`begin`
305			`if (rst)`
306	88	simont	`tmp_data1 <= #1 1'b0;`
307	62	simont	`else if (!hit_h && wr1 && (cyc==adr_r1))`
308			`tmp_data1 <= #1 dat_i[31:16];`
309			`else if (!hit_l && hit_h && wr1)`
310			`tmp_data1 <= #1 data1_o[31:16];`
311	67	simont	`end`
312	62	simont
313			`always @(posedge clk or posedge rst)`
314			`begin`
315			`if (rst) begin`
316			`wr1_t <= #1 1'b0;`
317			`stb_it <= #1 1'b0;`
318			`end else begin`
319			`wr1_t <= #1 wr1;`
320	67	simont	`stb_it <= #1 stb_i;`
321	62	simont	`end`
322			`end`
323
324			`endmodule`
325	88	simont

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