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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_indi_addr.v] - Blame information for rev 186

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 indirect address                                       ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   Contains ragister 0 and register 1. used for indirrect     ////
////   addressing.                                                ////
////                                                              ////
////  To Do:                                                      ////
////   nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6  2003/05/05 15:46:37  simont
// add aditional alu destination to solve critical path.
//
// Revision 1.5  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.4  2002/09/30 17:33:59  simont
// prepared header
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
 
module oc8051_indi_addr (clk, rst, wr_addr, data_in, wr, wr_bit, ri_out, sel, bank);
//
 
 
input        clk,       // clock
             rst,       // reset
             wr,        // write
             sel,       // select register
             wr_bit;    // write bit addressable
input  [1:0] bank;       // select register bank
input  [7:0] data_in;    // data input
input  [7:0] wr_addr;    // write address
 
output [7:0] ri_out;
 
//reg [7:0] buff [31:0];
reg wr_bit_r;
 
 
reg [7:0] buff [0:7];
 
//
//write to buffer
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    buff[3'b000] <= #1 8'h00;
    buff[3'b001] <= #1 8'h00;
    buff[3'b010] <= #1 8'h00;
    buff[3'b011] <= #1 8'h00;
    buff[3'b100] <= #1 8'h00;
    buff[3'b101] <= #1 8'h00;
    buff[3'b110] <= #1 8'h00;
    buff[3'b111] <= #1 8'h00;
  end else begin
    if ((wr) & !(wr_bit_r)) begin
      case (wr_addr) /* synopsys full_case parallel_case */
        8'h00: buff[3'b000] <= #1 data_in;
        8'h01: buff[3'b001] <= #1 data_in;
        8'h08: buff[3'b010] <= #1 data_in;
        8'h09: buff[3'b011] <= #1 data_in;
        8'h10: buff[3'b100] <= #1 data_in;
        8'h11: buff[3'b101] <= #1 data_in;
        8'h18: buff[3'b110] <= #1 data_in;
        8'h19: buff[3'b111] <= #1 data_in;
      endcase
    end
  end
end
 
//
//read from buffer
 
assign ri_out = (({3'b000, bank, 2'b00, sel}==wr_addr) & (wr) & !wr_bit_r) ?
                 data_in : buff[{bank, sel}];
 
 
 
always @(posedge clk or posedge rst)
  if (rst) begin
    wr_bit_r <= #1 1'b0;
  end else begin
    wr_bit_r <= #1 wr_bit;
  end
 
endmodule

Line No.	Rev	Author	Line
1	82	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 indirect address ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Contains ragister 0 and register 1. used for indirrect ////`
10			`//// addressing. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// nothing ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Simon Teran, simont@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48	179	simont	`// Revision 1.6 2003/05/05 15:46:37 simont`
49			`// add aditional alu destination to solve critical path.`
50			`//`
51	139	simont	`// Revision 1.5 2003/01/13 14:14:41 simont`
52			`// replace some modules`
53			`//`
54	82	simont	`// Revision 1.4 2002/09/30 17:33:59 simont`
55			`// prepared header`
56			`//`
57			`//`
58
59			`// synopsys translate_off`
60			`include "oc8051_timescale.v"
61			`// synopsys translate_on`
62
63
64	139	simont	`module oc8051_indi_addr (clk, rst, wr_addr, data_in, wr, wr_bit, ri_out, sel, bank);`
65	82	simont	`//`
66
67
68	139	simont	`input clk, // clock`
69			`rst, // reset`
70			`wr, // write`
71			`sel, // select register`
72			`wr_bit; // write bit addressable`
73			`input [1:0] bank; // select register bank`
74			`input [7:0] data_in; // data input`
75			`input [7:0] wr_addr; // write address`
76	82	simont
77	139	simont	`output [7:0] ri_out;`
78	82	simont
79	139	simont	`//reg [7:0] buff [31:0];`
80	82	simont	`reg wr_bit_r;`
81
82
83	139	simont	`reg [7:0] buff [0:7];`
84
85	82	simont	`//`
86			`//write to buffer`
87			`always @(posedge clk or posedge rst)`
88			`begin`
89			`if (rst) begin`
90	139	simont	`buff[3'b000] <= #1 8'h00;`
91			`buff[3'b001] <= #1 8'h00;`
92			`buff[3'b010] <= #1 8'h00;`
93			`buff[3'b011] <= #1 8'h00;`
94			`buff[3'b100] <= #1 8'h00;`
95			`buff[3'b101] <= #1 8'h00;`
96			`buff[3'b110] <= #1 8'h00;`
97			`buff[3'b111] <= #1 8'h00;`
98			`end else begin`
99			`if ((wr) & !(wr_bit_r)) begin`
100	179	simont	`case (wr_addr) /* synopsys full_case parallel_case */`
101	139	simont	`8'h00: buff[3'b000] <= #1 data_in;`
102			`8'h01: buff[3'b001] <= #1 data_in;`
103			`8'h08: buff[3'b010] <= #1 data_in;`
104			`8'h09: buff[3'b011] <= #1 data_in;`
105			`8'h10: buff[3'b100] <= #1 data_in;`
106			`8'h11: buff[3'b101] <= #1 data_in;`
107			`8'h18: buff[3'b110] <= #1 data_in;`
108			`8'h19: buff[3'b111] <= #1 data_in;`
109			`endcase`
110			`end`
111	82	simont	`end`
112			`end`
113
114			`//`
115			`//read from buffer`
116
117	139	simont	`assign ri_out = (({3'b000, bank, 2'b00, sel}==wr_addr) & (wr) & !wr_bit_r) ?`
118			`data_in : buff[{bank, sel}];`
119	82	simont
120
121	139	simont
122	82	simont	`always @(posedge clk or posedge rst)`
123			`if (rst) begin`
124			`wr_bit_r <= #1 1'b0;`
125			`end else begin`
126			`wr_bit_r <= #1 wr_bit;`
127			`end`
128
129			`endmodule`

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_indi_addr.v] - Blame information for rev 186