| 1 |
2 |
simont |
//////////////////////////////////////////////////////////////////////
|
| 2 |
|
|
//// ////
|
| 3 |
|
|
//// 8051 indirect address ////
|
| 4 |
|
|
//// ////
|
| 5 |
|
|
//// This file is part of the 8051 cores project ////
|
| 6 |
|
|
//// http://www.opencores.org/cores/8051/ ////
|
| 7 |
|
|
//// ////
|
| 8 |
|
|
//// Description ////
|
| 9 |
|
|
//// Contains ragister 0 and register 1. used for indirrect ////
|
| 10 |
|
|
//// addressing. ////
|
| 11 |
|
|
//// ////
|
| 12 |
|
|
//// To Do: ////
|
| 13 |
|
|
//// nothing ////
|
| 14 |
|
|
//// ////
|
| 15 |
|
|
//// Author(s): ////
|
| 16 |
|
|
//// - Simon Teran, simont@opencores.org ////
|
| 17 |
|
|
//// ////
|
| 18 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 19 |
|
|
//// ////
|
| 20 |
|
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
| 21 |
|
|
//// ////
|
| 22 |
|
|
//// This source file may be used and distributed without ////
|
| 23 |
|
|
//// restriction provided that this copyright statement is not ////
|
| 24 |
|
|
//// removed from the file and that any derivative work contains ////
|
| 25 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
| 26 |
|
|
//// ////
|
| 27 |
|
|
//// This source file is free software; you can redistribute it ////
|
| 28 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
| 29 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
| 30 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
| 31 |
|
|
//// later version. ////
|
| 32 |
|
|
//// ////
|
| 33 |
|
|
//// This source is distributed in the hope that it will be ////
|
| 34 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
| 35 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
| 36 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
| 37 |
|
|
//// details. ////
|
| 38 |
|
|
//// ////
|
| 39 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
| 40 |
|
|
//// Public License along with this source; if not, download it ////
|
| 41 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
| 42 |
|
|
//// ////
|
| 43 |
|
|
//////////////////////////////////////////////////////////////////////
|
| 44 |
|
|
//
|
| 45 |
|
|
// ver: 1
|
| 46 |
|
|
//
|
| 47 |
|
|
|
| 48 |
|
|
// synopsys translate_off
|
| 49 |
|
|
`include "oc8051_timescale.v"
|
| 50 |
|
|
// synopsys translate_on
|
| 51 |
|
|
|
| 52 |
|
|
|
| 53 |
|
|
module oc8051_indi_addr (clk, rst, addr, data_in, wr, wr_bit, data_out, sel, bank);
|
| 54 |
|
|
//
|
| 55 |
|
|
// clk (in) clock
|
| 56 |
|
|
// rst (in) reset
|
| 57 |
|
|
// addr (in) write address [oc8051_ram_wr_sel.out]
|
| 58 |
|
|
// data_in (in) data input (alu destination1) [oc8051_alu.des1]
|
| 59 |
|
|
// wr (in) write [oc8051_decoder.wr -r]
|
| 60 |
|
|
// wr_bit (in) write bit addresable [oc8051_decoder.bit_addr -r]
|
| 61 |
|
|
// data_out (out) data output [oc8051_ram_rd_sel.ri, oc8051_ram_wr_sel.ri -r]
|
| 62 |
|
|
// sel (in) select register [oc8051_op_select.op1_out[0] ]
|
| 63 |
|
|
// bank (in) select register bank: [oc8051_psw.data_out[4:3] ]
|
| 64 |
|
|
//
|
| 65 |
|
|
|
| 66 |
|
|
|
| 67 |
|
|
input clk, rst, wr, sel, wr_bit;
|
| 68 |
|
|
input [1:0] bank;
|
| 69 |
|
|
input [7:0] addr, data_in;
|
| 70 |
|
|
|
| 71 |
|
|
output [7:0] data_out;
|
| 72 |
|
|
reg [7:0] data_out;
|
| 73 |
|
|
|
| 74 |
|
|
reg [7:0] buff [7:0];
|
| 75 |
|
|
|
| 76 |
|
|
//
|
| 77 |
|
|
//write to buffer
|
| 78 |
|
|
always @(posedge clk or posedge rst)
|
| 79 |
|
|
begin
|
| 80 |
|
|
if (rst) begin
|
| 81 |
|
|
buff[3'b000] <= #1 8'h00;
|
| 82 |
|
|
buff[3'b001] <= #1 8'h00;
|
| 83 |
|
|
buff[3'b010] <= #1 8'h00;
|
| 84 |
|
|
buff[3'b011] <= #1 8'h00;
|
| 85 |
|
|
buff[3'b100] <= #1 8'h00;
|
| 86 |
|
|
buff[3'b101] <= #1 8'h00;
|
| 87 |
|
|
buff[3'b110] <= #1 8'h00;
|
| 88 |
|
|
buff[3'b111] <= #1 8'h00;
|
| 89 |
|
|
end else begin
|
| 90 |
|
|
if ((wr) & !(wr_bit)) begin
|
| 91 |
|
|
case (addr)
|
| 92 |
|
|
8'h00: buff[3'b000] <= #1 data_in;
|
| 93 |
|
|
8'h01: buff[3'b001] <= #1 data_in;
|
| 94 |
|
|
8'h08: buff[3'b010] <= #1 data_in;
|
| 95 |
|
|
8'h09: buff[3'b011] <= #1 data_in;
|
| 96 |
|
|
8'h10: buff[3'b100] <= #1 data_in;
|
| 97 |
|
|
8'h11: buff[3'b101] <= #1 data_in;
|
| 98 |
|
|
8'h18: buff[3'b110] <= #1 data_in;
|
| 99 |
|
|
8'h19: buff[3'b111] <= #1 data_in;
|
| 100 |
|
|
endcase
|
| 101 |
|
|
end
|
| 102 |
|
|
end
|
| 103 |
|
|
end
|
| 104 |
|
|
|
| 105 |
|
|
//
|
| 106 |
|
|
//read from buffer
|
| 107 |
|
|
//always @(sel or bank or data_in or wr or addr or wr or buff)
|
| 108 |
|
|
always @(sel or bank or data_in or wr or addr or wr)
|
| 109 |
|
|
begin
|
| 110 |
|
|
if (({3'b000, bank, 2'b00, sel}==addr) & (wr))
|
| 111 |
|
|
data_out = data_in;
|
| 112 |
|
|
else
|
| 113 |
|
|
data_out = buff[{bank, sel}];
|
| 114 |
|
|
end
|
| 115 |
|
|
|
| 116 |
|
|
endmodule
|
