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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_int.v] - Blame information for rev 90

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores interrupt control module                         ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   contains sfr's: tcon, ip, ie;                              ////
////   interrupt handling                                         ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////      - Jaka Simsic, jakas@opencores.org                      ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.5  2002/09/30 17:33:59  simont
// prepared header
//
//
 
 
`include "oc8051_defines.v"
 
//synopsys translate_off
`include "oc8051_timescale.v"
//synopsys translate_on
 
 
 
module oc8051_int (clk, rst, wr_addr, rd_addr, data_in, bit_in, data_out, bit_out, wr, wr_bit,
//timer interrupts
        tf0, tf1, t2_int,
        tr0, tr1,
//external interrupts
        ie0, ie1,
//uart interrupts
        uart_int,
//to cpu
        intr, reti, int_vec, ack);
 
input [7:0] wr_addr, data_in, rd_addr;
input wr, tf0, tf1, t2_int, ie0, ie1, clk, rst, reti, wr_bit, bit_in, ack, uart_int;
 
output tr0, tr1, intr, bit_out;
output [7:0] int_vec, data_out;
 
reg [7:0] ip, ie, int_vec, data_out;
 
reg [3:0] tcon_s;
reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0, bit_out;
wire [7:0] tcon;
 
//
// isrc         processing interrupt sources
// int_dept
wire [2:0] isrc_cur;
reg [2:0] isrc [1:0];
reg int_dept;
wire int_dept_1;
reg int_proc;
reg [1:0] int_lev [1:0];
wire cur_lev;
 
assign isrc_cur = int_proc ? isrc[int_dept_1] : 2'h0;
assign int_dept_1 = int_dept - 1'b1;
assign cur_lev = int_lev[int_dept_1];
 
//
// contains witch level of interrupts is running
//reg [1:0] int_levl, int_levl_w;
 
//
// int_ln       waiting interrupts on level n
// ip_ln        interrupts on level n
// int_src      interrupt sources
wire [5:0] int_l0, int_l1;
wire [5:0] ip_l0, ip_l1;
wire [5:0] int_src;
wire il0, il1;
 
 
reg tf0_buff, tf1_buff, ie0_buff, ie1_buff;
 
//
//interrupt priority
assign ip_l0 = ~ip[5:0];
assign ip_l1 = ip[5:0];
 
assign int_src = {t2_int, uart_int, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};
 
//
// waiting interrupts
assign int_l0 = ip_l0 & {ie[5:0]} & int_src;
assign int_l1 = ip_l1 & {ie[5:0]} & int_src;
assign il0 = |int_l0;
assign il1 = |int_l1;
 
//
// TCON
assign tcon = {tcon_tf1, tcon_s[3], tcon_tf0, tcon_s[2], tcon_ie1, tcon_s[1], tcon_ie0, tcon_s[0]};
assign tr0 = tcon_s[2];
assign tr1 = tcon_s[3];
assign intr = |int_vec;
 
 
//
// IP
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   ip <=#1 `OC8051_RST_IP;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin
   ip <= #1 data_in;
 end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IP))
   ip[wr_addr[2:0]] <= #1 bit_in;
end
 
//
// IE
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   ie <=#1 `OC8051_RST_IE;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin
   ie <= #1 data_in;
 end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IE))
   ie[wr_addr[2:0]] <= #1 bit_in;
end
 
//
// tcon_s
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tcon_s <=#1 4'b0000;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};
 end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
   case (wr_addr[2:0])
     3'b000: tcon_s[0] <= #1 bit_in;
     3'b010: tcon_s[1] <= #1 bit_in;
     3'b100: tcon_s[2] <= #1 bit_in;
     3'b110: tcon_s[3] <= #1 bit_in;
   endcase
 end
end
 
//
// tf1 (tmod.7)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tcon_tf1 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_tf1 <= #1 data_in[7];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b111})) begin
   tcon_tf1 <= #1 bit_in;
 end else if (!(tf1_buff) & (tf1)) begin
   tcon_tf1 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_TF1)) begin
   tcon_tf1 <= #1 1'b0;
 end
end
 
//
// tf0 (tmod.5)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tcon_tf0 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_tf0 <= #1 data_in[5];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b101})) begin
   tcon_tf0 <= #1 bit_in;
 end else if (!(tf0_buff) & (tf0)) begin
   tcon_tf0 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_TF0)) begin
   tcon_tf0 <= #1 1'b0;
 end
end
 
 
//
// ie0 (tmod.1)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tcon_ie0 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_ie0 <= #1 data_in[1];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b001})) begin
   tcon_ie0 <= #1 bit_in;
 end else if (((tcon_s[0]) & (ie0_buff) & !(ie0)) | (!(tcon_s[0]) & !(ie0))) begin
   tcon_ie0 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_IE0) & (tcon_s[0])) begin
   tcon_ie0 <= #1 1'b0;
 end else if (!(tcon_s[0]) & (ie0)) begin
   tcon_ie0 <= #1 1'b0;
 end
end
 
 
//
// ie1 (tmod.3)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
//   tcon_ie1 <=#1 `OC8051_RST_TCON[3];
   tcon_ie1 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_ie1 <= #1 data_in[3];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b011})) begin
   tcon_ie1 <= #1 bit_in;
 end else if (((tcon_s[1]) & (ie1_buff) & !(ie1)) | (!(tcon_s[1]) & !(ie1))) begin
   tcon_ie1 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_IE1) & (tcon_s[1])) begin
   tcon_ie1 <= #1 1'b0;
 end else if (!(tcon_s[1]) & (ie1)) begin
   tcon_ie1 <= #1 1'b0;
 end
end
 
//
// interrupt processing
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   int_vec <= #1 8'h00;
   int_dept <= #1 1'b0;
   isrc[0] <= #1 3'h0;
   isrc[1] <= #1 3'h0;
   int_proc <= #1 1'b0;
   int_lev[0] <= #1 1'b0;
   int_lev[1] <= #1 1'b0;
 end else if (reti) begin  // return from interrupt
   if (int_dept==2'b01)
     int_proc <= #1 1'b0;
   int_dept <= #1 int_dept - 2'b01;
  end else if (((ie[7]) & (!cur_lev) || !int_proc) & il1) begin  // interrupt on level 1
   int_proc <= #1 1'b1;
   int_lev[int_dept] <= #1 `OC8051_ILEV_L1;
   int_dept <= #1 int_dept + 2'b01;
   if (int_l1[0]) begin
     int_vec <= #1 `OC8051_INT_X0;
     isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
   end else if (int_l1[1]) begin
     int_vec <= #1 `OC8051_INT_T0;
     isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
   end else if (int_l1[2]) begin
     int_vec <= #1 `OC8051_INT_X1;
     isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
   end else if (int_l1[3]) begin
     int_vec <= #1 `OC8051_INT_T1;
     isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
   end else if (int_l1[4]) begin
     int_vec <= #1 `OC8051_INT_UART;
     isrc[int_dept] <= #1 `OC8051_ISRC_UART;
   end else if (int_l1[5]) begin
     int_vec <= #1 `OC8051_INT_T2;
     isrc[int_dept] <= #1 `OC8051_ISRC_T2;
   end
 
 end else if ((ie[7]) & !int_proc & il0) begin  // interrupt on level 0
   int_proc <= #1 1'b1;
   int_lev[int_dept] <= #1 `OC8051_ILEV_L0;
   int_dept <= #1 int_dept + 2'b01;
   if (int_l0[0]) begin
     int_vec <= #1 `OC8051_INT_X0;
     isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
   end else if (int_l0[1]) begin
     int_vec <= #1 `OC8051_INT_T0;
     isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
   end else if (int_l0[2]) begin
     int_vec <= #1 `OC8051_INT_X1;
     isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
   end else if (int_l0[3]) begin
     int_vec <= #1 `OC8051_INT_T1;
     isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
   end else if (int_l0[4]) begin
     int_vec <= #1 `OC8051_INT_UART;
     isrc[int_dept] <= #1 `OC8051_ISRC_UART;
   end else if (int_l0[5]) begin
     int_vec <= #1 `OC8051_INT_T2;
     isrc[int_dept] <= #1 `OC8051_ISRC_T2;
   end
 end else begin
   int_vec <= #1 8'h00;
 end
end
 
 
always @(posedge clk or posedge rst)
begin
  if (rst) data_out <= #1 8'h0;
  else if (wr & !wr_bit & (wr_addr==rd_addr) & (
     (wr_addr==`OC8051_SFR_IP) | (wr_addr==`OC8051_SFR_IE) | (wr_addr==`OC8051_SFR_TCON))) begin
    data_out <= #1 data_in;
  end else begin
    case (rd_addr)
      `OC8051_SFR_IP: data_out <= #1 ip;
      `OC8051_SFR_IE: data_out <= #1 ie0;
      default: data_out <= #1 tcon;
    endcase
  end
end
 
always @(posedge clk or posedge rst)
  if (rst) begin
    tf0_buff <= #1 1'b0;
    tf1_buff <= #1 1'b0;
    ie0_buff <= #1 1'b0;
    ie1_buff <= #1 1'b0;
  end else begin
    tf0_buff <= #1 tf0;
    tf1_buff <= #1 tf1;
    ie0_buff <= #1 ie0;
    ie1_buff <= #1 ie1;
  end
 
always @(posedge clk or posedge rst)
begin
  if (rst) bit_out <= #1 1'b0;
  else if (wr & wr_bit & (wr_addr==rd_addr)) begin
    bit_out <= #1 bit_in;
  end else if ((rd_addr[7:3]==wr_addr[7:3]) & wr & !wr_bit) begin
    bit_out <= #1 data_in[rd_addr[2:0]];
  end else begin
    case (rd_addr[7:3])
      `OC8051_SFR_B_IP: bit_out <= #1 ip[rd_addr[2:0]];
      `OC8051_SFR_B_IE: bit_out <= #1 ie[rd_addr[2:0]];
      default: bit_out <= #1 tcon[rd_addr[2:0]];
    endcase
  end
end
 
 
endmodule

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_int.v] - Blame information for rev 90

Line No.	Rev	Author	Line
1	82	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores interrupt control module ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// contains sfr's: tcon, ip, ie; ////`
10			`//// interrupt handling ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// Nothing ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Simon Teran, simont@opencores.org ////`
17			`//// - Jaka Simsic, jakas@opencores.org ////`
18			`//// ////`
19			`//////////////////////////////////////////////////////////////////////`
20			`//// ////`
21			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
22			`//// ////`
23			`//// This source file may be used and distributed without ////`
24			`//// restriction provided that this copyright statement is not ////`
25			`//// removed from the file and that any derivative work contains ////`
26			`//// the original copyright notice and the associated disclaimer. ////`
27			`//// ////`
28			`//// This source file is free software; you can redistribute it ////`
29			`//// and/or modify it under the terms of the GNU Lesser General ////`
30			`//// Public License as published by the Free Software Foundation; ////`
31			`//// either version 2.1 of the License, or (at your option) any ////`
32			`//// later version. ////`
33			`//// ////`
34			`//// This source is distributed in the hope that it will be ////`
35			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
36			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
37			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
38			`//// details. ////`
39			`//// ////`
40			`//// You should have received a copy of the GNU Lesser General ////`
41			`//// Public License along with this source; if not, download it ////`
42			`//// from http://www.opencores.org/lgpl.shtml ////`
43			`//// ////`
44			`//////////////////////////////////////////////////////////////////////`
45			`//`
46			`// CVS Revision History`
47			`//`
48			`// $Log: not supported by cvs2svn $`
49	90	simont	`// Revision 1.6 2003/01/13 14:14:41 simont`
50			`// replace some modules`
51			`//`
52	82	simont	`// Revision 1.5 2002/09/30 17:33:59 simont`
53			`// prepared header`
54			`//`
55			`//`
56
57
58			`include "oc8051_defines.v"
59
60			`//synopsys translate_off`
61			`include "oc8051_timescale.v"
62			`//synopsys translate_on`
63
64
65
66	90	simont	`module oc8051_int (clk, rst, wr_addr, rd_addr, data_in, bit_in, data_out, bit_out, wr, wr_bit,`
67	82	simont	`//timer interrupts`
68			`tf0, tf1, t2_int,`
69			`tr0, tr1,`
70			`//external interrupts`
71			`ie0, ie1,`
72			`//uart interrupts`
73			`uart_int,`
74			`//to cpu`
75			`intr, reti, int_vec, ack);`
76
77			`input [7:0] wr_addr, data_in, rd_addr;`
78			`input wr, tf0, tf1, t2_int, ie0, ie1, clk, rst, reti, wr_bit, bit_in, ack, uart_int;`
79
80			`output tr0, tr1, intr, bit_out;`
81			`output [7:0] int_vec, data_out;`
82
83			`reg [7:0] ip, ie, int_vec, data_out;`
84
85			`reg [3:0] tcon_s;`
86			`reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0, bit_out;`
87			`wire [7:0] tcon;`
88
89			`//`
90			`// isrc processing interrupt sources`
91			`// int_dept`
92			`wire [2:0] isrc_cur;`
93			`reg [2:0] isrc [1:0];`
94			`reg int_dept;`
95			`wire int_dept_1;`
96			`reg int_proc;`
97			`reg [1:0] int_lev [1:0];`
98			`wire cur_lev;`
99
100			`assign isrc_cur = int_proc ? isrc[int_dept_1] : 2'h0;`
101			`assign int_dept_1 = int_dept - 1'b1;`
102			`assign cur_lev = int_lev[int_dept_1];`
103
104			`//`
105			`// contains witch level of interrupts is running`
106			`//reg [1:0] int_levl, int_levl_w;`
107
108			`//`
109			`// int_ln waiting interrupts on level n`
110			`// ip_ln interrupts on level n`
111			`// int_src interrupt sources`
112			`wire [5:0] int_l0, int_l1;`
113			`wire [5:0] ip_l0, ip_l1;`
114			`wire [5:0] int_src;`
115			`wire il0, il1;`
116
117
118			`reg tf0_buff, tf1_buff, ie0_buff, ie1_buff;`
119
120			`//`
121			`//interrupt priority`
122			`assign ip_l0 = ~ip[5:0];`
123			`assign ip_l1 = ip[5:0];`
124
125			`assign int_src = {t2_int, uart_int, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};`
126
127			`//`
128			`// waiting interrupts`
129			`assign int_l0 = ip_l0 & {ie[5:0]} & int_src;`
130			`assign int_l1 = ip_l1 & {ie[5:0]} & int_src;`
131			`assign il0 = \|int_l0;`
132			`assign il1 = \|int_l1;`
133
134			`//`
135			`// TCON`
136			`assign tcon = {tcon_tf1, tcon_s[3], tcon_tf0, tcon_s[2], tcon_ie1, tcon_s[1], tcon_ie0, tcon_s[0]};`
137			`assign tr0 = tcon_s[2];`
138			`assign tr1 = tcon_s[3];`
139			`assign intr = \|int_vec;`
140
141
142			`//`
143			`// IP`
144			`always @(posedge clk or posedge rst)`
145			`begin`
146			`if (rst) begin`
147			ip <=#1 `OC8051_RST_IP;
148			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin
149			`ip <= #1 data_in;`
150			end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IP))
151			`ip[wr_addr[2:0]] <= #1 bit_in;`
152			`end`
153
154			`//`
155			`// IE`
156			`always @(posedge clk or posedge rst)`
157			`begin`
158			`if (rst) begin`
159			ie <=#1 `OC8051_RST_IE;
160			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin
161			`ie <= #1 data_in;`
162			end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IE))
163			`ie[wr_addr[2:0]] <= #1 bit_in;`
164			`end`
165
166			`//`
167			`// tcon_s`
168			`//`
169			`always @(posedge clk or posedge rst)`
170			`begin`
171			`if (rst) begin`
172			`tcon_s <=#1 4'b0000;`
173			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
174			`tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};`
175			end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
176			`case (wr_addr[2:0])`
177			`3'b000: tcon_s[0] <= #1 bit_in;`
178			`3'b010: tcon_s[1] <= #1 bit_in;`
179			`3'b100: tcon_s[2] <= #1 bit_in;`
180			`3'b110: tcon_s[3] <= #1 bit_in;`
181			`endcase`
182			`end`
183			`end`
184
185			`//`
186			`// tf1 (tmod.7)`
187			`//`
188			`always @(posedge clk or posedge rst)`
189			`begin`
190			`if (rst) begin`
191			`tcon_tf1 <=#1 1'b0;`
192			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
193			`tcon_tf1 <= #1 data_in[7];`
194			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b111})) begin
195			`tcon_tf1 <= #1 bit_in;`
196			`end else if (!(tf1_buff) & (tf1)) begin`
197			`tcon_tf1 <= #1 1'b1;`
198			end else if (ack & (isrc_cur==`OC8051_ISRC_TF1)) begin
199			`tcon_tf1 <= #1 1'b0;`
200			`end`
201			`end`
202
203			`//`
204			`// tf0 (tmod.5)`
205			`//`
206			`always @(posedge clk or posedge rst)`
207			`begin`
208			`if (rst) begin`
209			`tcon_tf0 <=#1 1'b0;`
210			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
211			`tcon_tf0 <= #1 data_in[5];`
212			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b101})) begin
213			`tcon_tf0 <= #1 bit_in;`
214			`end else if (!(tf0_buff) & (tf0)) begin`
215			`tcon_tf0 <= #1 1'b1;`
216			end else if (ack & (isrc_cur==`OC8051_ISRC_TF0)) begin
217			`tcon_tf0 <= #1 1'b0;`
218			`end`
219			`end`
220
221
222			`//`
223			`// ie0 (tmod.1)`
224			`//`
225			`always @(posedge clk or posedge rst)`
226			`begin`
227			`if (rst) begin`
228			`tcon_ie0 <=#1 1'b0;`
229			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
230			`tcon_ie0 <= #1 data_in[1];`
231			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b001})) begin
232			`tcon_ie0 <= #1 bit_in;`
233			`end else if (((tcon_s[0]) & (ie0_buff) & !(ie0)) \| (!(tcon_s[0]) & !(ie0))) begin`
234			`tcon_ie0 <= #1 1'b1;`
235			end else if (ack & (isrc_cur==`OC8051_ISRC_IE0) & (tcon_s[0])) begin
236			`tcon_ie0 <= #1 1'b0;`
237			`end else if (!(tcon_s[0]) & (ie0)) begin`
238			`tcon_ie0 <= #1 1'b0;`
239			`end`
240			`end`
241
242
243			`//`
244			`// ie1 (tmod.3)`
245			`//`
246			`always @(posedge clk or posedge rst)`
247			`begin`
248			`if (rst) begin`
249			// tcon_ie1 <=#1 `OC8051_RST_TCON[3];
250			`tcon_ie1 <=#1 1'b0;`
251			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
252			`tcon_ie1 <= #1 data_in[3];`
253			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b011})) begin
254			`tcon_ie1 <= #1 bit_in;`
255			`end else if (((tcon_s[1]) & (ie1_buff) & !(ie1)) \| (!(tcon_s[1]) & !(ie1))) begin`
256			`tcon_ie1 <= #1 1'b1;`
257			end else if (ack & (isrc_cur==`OC8051_ISRC_IE1) & (tcon_s[1])) begin
258			`tcon_ie1 <= #1 1'b0;`
259			`end else if (!(tcon_s[1]) & (ie1)) begin`
260			`tcon_ie1 <= #1 1'b0;`
261			`end`
262			`end`
263
264			`//`
265			`// interrupt processing`
266			`always @(posedge clk or posedge rst)`
267			`begin`
268			`if (rst) begin`
269			`int_vec <= #1 8'h00;`
270			`int_dept <= #1 1'b0;`
271			`isrc[0] <= #1 3'h0;`
272			`isrc[1] <= #1 3'h0;`
273			`int_proc <= #1 1'b0;`
274			`int_lev[0] <= #1 1'b0;`
275			`int_lev[1] <= #1 1'b0;`
276			`end else if (reti) begin // return from interrupt`
277			`if (int_dept==2'b01)`
278			`int_proc <= #1 1'b0;`
279			`int_dept <= #1 int_dept - 2'b01;`
280			`end else if (((ie[7]) & (!cur_lev) \|\| !int_proc) & il1) begin // interrupt on level 1`
281			`int_proc <= #1 1'b1;`
282			int_lev[int_dept] <= #1 `OC8051_ILEV_L1;
283			`int_dept <= #1 int_dept + 2'b01;`
284			`if (int_l1[0]) begin`
285			int_vec <= #1 `OC8051_INT_X0;
286			isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
287			`end else if (int_l1[1]) begin`
288			int_vec <= #1 `OC8051_INT_T0;
289			isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
290			`end else if (int_l1[2]) begin`
291			int_vec <= #1 `OC8051_INT_X1;
292			isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
293			`end else if (int_l1[3]) begin`
294			int_vec <= #1 `OC8051_INT_T1;
295			isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
296			`end else if (int_l1[4]) begin`
297			int_vec <= #1 `OC8051_INT_UART;
298			isrc[int_dept] <= #1 `OC8051_ISRC_UART;
299			`end else if (int_l1[5]) begin`
300			int_vec <= #1 `OC8051_INT_T2;
301			isrc[int_dept] <= #1 `OC8051_ISRC_T2;
302			`end`
303
304			`end else if ((ie[7]) & !int_proc & il0) begin // interrupt on level 0`
305			`int_proc <= #1 1'b1;`
306			int_lev[int_dept] <= #1 `OC8051_ILEV_L0;
307			`int_dept <= #1 int_dept + 2'b01;`
308			`if (int_l0[0]) begin`
309			int_vec <= #1 `OC8051_INT_X0;
310			isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
311			`end else if (int_l0[1]) begin`
312			int_vec <= #1 `OC8051_INT_T0;
313			isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
314			`end else if (int_l0[2]) begin`
315			int_vec <= #1 `OC8051_INT_X1;
316			isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
317			`end else if (int_l0[3]) begin`
318			int_vec <= #1 `OC8051_INT_T1;
319			isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
320			`end else if (int_l0[4]) begin`
321			int_vec <= #1 `OC8051_INT_UART;
322			isrc[int_dept] <= #1 `OC8051_ISRC_UART;
323			`end else if (int_l0[5]) begin`
324			int_vec <= #1 `OC8051_INT_T2;
325			isrc[int_dept] <= #1 `OC8051_ISRC_T2;
326			`end`
327			`end else begin`
328			`int_vec <= #1 8'h00;`
329			`end`
330			`end`
331
332
333			`always @(posedge clk or posedge rst)`
334			`begin`
335			`if (rst) data_out <= #1 8'h0;`
336			`else if (wr & !wr_bit & (wr_addr==rd_addr) & (`
337			(wr_addr==`OC8051_SFR_IP) \| (wr_addr==`OC8051_SFR_IE) \| (wr_addr==`OC8051_SFR_TCON))) begin
338			`data_out <= #1 data_in;`
339			`end else begin`
340			`case (rd_addr)`
341			`OC8051_SFR_IP: data_out <= #1 ip;
342			`OC8051_SFR_IE: data_out <= #1 ie0;
343			`default: data_out <= #1 tcon;`
344			`endcase`
345			`end`
346			`end`
347
348			`always @(posedge clk or posedge rst)`
349			`if (rst) begin`
350			`tf0_buff <= #1 1'b0;`
351			`tf1_buff <= #1 1'b0;`
352			`ie0_buff <= #1 1'b0;`
353			`ie1_buff <= #1 1'b0;`
354			`end else begin`
355			`tf0_buff <= #1 tf0;`
356			`tf1_buff <= #1 tf1;`
357			`ie0_buff <= #1 ie0;`
358			`ie1_buff <= #1 ie1;`
359			`end`
360
361			`always @(posedge clk or posedge rst)`
362			`begin`
363			`if (rst) bit_out <= #1 1'b0;`
364			`else if (wr & wr_bit & (wr_addr==rd_addr)) begin`
365			`bit_out <= #1 bit_in;`
366			`end else if ((rd_addr[7:3]==wr_addr[7:3]) & wr & !wr_bit) begin`
367			`bit_out <= #1 data_in[rd_addr[2:0]];`
368			`end else begin`
369			`case (rd_addr[7:3])`
370			`OC8051_SFR_B_IP: bit_out <= #1 ip[rd_addr[2:0]];
371			`OC8051_SFR_B_IE: bit_out <= #1 ie[rd_addr[2:0]];
372			`default: bit_out <= #1 tcon[rd_addr[2:0]];`
373			`endcase`
374			`end`
375			`end`
376
377
378			`endmodule`