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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_memory_interface.v] - Blame information for rev 118

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 memory interface                                       ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   comunication betwen cpu and memory                         ////
////                                                              ////
////  To Do:                                                      ////
////   nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2003/01/13 14:13:12  simont
// initial import
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
module oc8051_memory_interface (clk, rst,
//decoder
  wr_i, wr_bit_i, rd_sel, wr_sel,
  pc_wr_sel, pc_wr, pc, rd,
  mem_wait, mem_act, istb,
//internal ram
  wr_o, wr_bit_o, rd_addr, wr_addr, rd_ind, wr_ind, wr_dat,
 
  bit_in, in_ram, sfr, sfr_bit, bit_out, iram_out,
 
//program rom
  iadr_o, ea, ea_int,
  op1_out, op2_out, op3_out,
//internal
  op1_i, op2_i, op3_i,
//external
  iack_i, istb_o, idat_i,
 
//external data ram
  dadr_o, dwe_o, dstb_o, dack_i, ddat_i, ddat_o,
//interrupt interface
  intr, int_v, int_ack,
 
//alu
  des1, des2,
 
//sfr's
  dptr, ri, rn_mem, sp,  sp_w, rn, acc, reti);
 
input bit_in, sfr_bit, dack_i;
input [2:0] mem_act;
input [7:0] in_ram, sfr, acc, sp_w;
input [31:0] idat_i;
 
output bit_out, mem_wait, reti;
output [7:0] iram_out, wr_dat;
 
reg bit_out, reti;
reg [7:0] iram_out, sp_r;
reg [2:0] rd_addr_r;
input clk, rst, wr_i, wr_bit_i;
output wr_o, wr_bit_o;
 
//????
reg dack_ir;
reg [7:0] ddat_ir;
reg [23:0] idat_ir;
 
/////////////////////////////
//
//  rom_addr_sel
//
/////////////////////////////
input iack_i;
input [7:0] des1, des2;
output [15:0] iadr_o;
 
wire ea_rom_sel;
 
/////////////////////////////
//
// ext_addr_sel
//
/////////////////////////////
input [7:0] ri, rn_mem, ddat_i;
input [15:0] dptr;
 
output dstb_o, dwe_o;
output [7:0] ddat_o;
output [15:0] dadr_o;
 
/////////////////////////////
//
// ram_adr_sel
//
/////////////////////////////
 
input [2:0] rd_sel, wr_sel;
input [4:0] rn;
input [7:0] sp;
 
output rd_ind, wr_ind;
output [7:0] wr_addr, rd_addr;
reg rd_ind, wr_ind;
reg [7:0] wr_addr, rd_addr;
 
reg [4:0] rn_r;
reg [7:0] ri_r, imm_r, imm2_r, op1_r;
wire [7:0] imm, imm2;
 
/////////////////////////////
//
// op_select
//
/////////////////////////////
 
input intr, rd, ea, ea_int, istb;
input [7:0] op1_i, op2_i, op3_i, int_v;
output int_ack, istb_o;
output [7:0] op1_out, op3_out, op2_out;
 
reg int_ack_t, int_ack, int_ack_buff;
reg [7:0] int_vec_buff;
reg [7:0] op1_out, op2_buff, op3_buff;
reg [7:0] op1_o, op2_o, op3_o;
reg [7:0] op1_xt, op2_xt, op3_xt;
 
wire [7:0] op1, op2, op3, op2_direct;
//wire op_sel;
 
/////////////////////////////
//
//  pc
//
/////////////////////////////
input [2:0] pc_wr_sel;
 
input pc_wr;
output [15:0] pc;
 
 
reg [15:0] pc;
 
//
//pc            program counter register, save current value
reg [15:0] pc_buf;
wire [15:0] alu;
 
//
// wr_lo        write low: used in reti instruction, write only low byte of pc
// ini_buff     interrupt buffer: used to prevent interrupting in the middle of executin instructions
reg int_buff, int_buff1;
 
 
//
//
////////////////////////////
reg istb_t, imem_wait, dstb_o, dwe_o;
//reg [3:0] mem_act_r;
reg [7:0] ddat_o;
reg [15:0] iadr_t, dadr_ot;
reg dmem_wait;
wire pc_wait;
wire [1:0] bank;
//wire pis_l;
wire [15:0] iadr_ot;
wire [7:0] isr_call;
 
assign bank = rn[4:3];
assign imm = op2_out;
assign imm2 = op3_out;
assign alu = {des2,des1};
assign ea_rom_sel = ea && ea_int;
assign wr_o = wr_i;
assign wr_bit_o = wr_bit_i;
 
assign mem_wait = dmem_wait || imem_wait;
//assign istb_o = (istb || istb_t || (!iack_i)) && !dstb_o && !ea_rom_sel;
assign istb_o = (istb || istb_t) && !dstb_o && !ea_rom_sel;
 
assign pc_wait = rd && (ea_rom_sel || (!istb_t && !(istb_o && !iack_i)));
 
assign wr_dat = des1;
 
 
/////////////////////////////
//
//  ram_select
//
/////////////////////////////
always @(rd_addr_r or in_ram or sfr or bit_in or sfr_bit or rn_mem or rd_ind)
begin
  if (rd_addr_r[2] && !rd_ind) begin
    iram_out = sfr;
    bit_out = sfr_bit;
  end else if (~|rd_addr_r[2:0]) begin
    iram_out = rn_mem;
    bit_out = bit_in;
  end else begin
    iram_out = in_ram;
    bit_out = bit_in;
  end
end
 
/////////////////////////////
//
// ram_adr_sel
//
/////////////////////////////
 
always @(rd_sel or sp or ri or rn or imm or op1_out or dadr_o[15:0] or bank)
begin
     case (rd_sel)
      `OC8051_RRS_RN : rd_addr = {3'h0, rn};
      `OC8051_RRS_I : rd_addr = ri;
      `OC8051_RRS_D : rd_addr = imm;
      `OC8051_RRS_SP : rd_addr = sp;
 
      `OC8051_RRS_B : rd_addr = `OC8051_SFR_B;
      `OC8051_RRS_DPTR : rd_addr = `OC8051_SFR_DPTR_LO;
      default : rd_addr = 2'bxx;
    endcase
 
end
 
 
//
//
always @(wr_sel or sp_w or rn_r or imm_r or ri_r or imm2_r or op1_r or dadr_o[15:0])
begin
    case (wr_sel)
      `OC8051_RWS_RN : wr_addr = {3'h0, rn_r};
      `OC8051_RWS_I  : wr_addr = ri_r;
      `OC8051_RWS_D  : wr_addr = imm_r;
      `OC8051_RWS_SP : wr_addr = sp_w;
      `OC8051_RWS_D3 : wr_addr = imm2_r;
      `OC8051_RWS_B  : wr_addr = `OC8051_SFR_B;
      default : wr_addr = 2'bxx;
    endcase
end
 
always @(posedge clk or posedge rst)
  if (rst)
    rd_ind <= #1 1'b0;
  else if ((rd_sel==`OC8051_RRS_I) || (rd_sel==`OC8051_RRS_SP))
    rd_ind <= #1 1'b1;
  else
    rd_ind <= #1 1'b0;
 
always @(wr_sel)
  if ((wr_sel==`OC8051_RWS_I) || (wr_sel==`OC8051_RWS_SP))
    wr_ind = 1'b1;
  else
    wr_ind = 1'b0;
 
 
/////////////////////////////
//
//  rom_addr_sel
//
/////////////////////////////
//
// output address is alu destination
// (instructions MOVC)
 
assign iadr_ot = istb_t ? iadr_t : pc;
assign iadr_o = iadr_ot;
 
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    iadr_t <= #1 23'h0;
    istb_t <= #1 1'b0;
    imem_wait <= #1 1'b0;
    idat_ir <= #1 24'h0;
  end else if (iack_i) begin
    istb_t <= #1 1'b0;
    imem_wait <= #1 1'b0;
    idat_ir <= #1 idat_i [31:8];
  end else if (ea_rom_sel && imem_wait) begin
    imem_wait <= #1 1'b0;
  end else if (ea_rom_sel && !imem_wait && istb_t) begin
    istb_t <= #1 1'b0;
  end else if (mem_act==`OC8051_MAS_CODE) begin
    iadr_t <= #1 {des2, des1};
    istb_t <= #1 1'b1;
    imem_wait <= #1 1'b1;
  end
end
 
/////////////////////////////
//
// ext_addr_sel
//
/////////////////////////////
 
assign dadr_o = dadr_ot;
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    dwe_o <= #1 1'b0;
    dmem_wait <= #1 1'b0;
    dstb_o <= #1 1'b0;
    ddat_o <= #1 8'h00;
    dadr_ot <= #1 23'h0;
  end else if (dack_i) begin
    dwe_o <= #1 1'b0;
    dstb_o <= #1 1'b0;
    dmem_wait <= #1 1'b0;
  end else begin
    case (mem_act)
      `OC8051_MAS_DPTR_R: begin  // read from external rom: acc=(dptr)
        dwe_o <= #1 1'b0;
        dstb_o <= #1 1'b1;
        ddat_o <= #1 8'h00;
        dadr_ot <= #1 {7'h0, dptr};
        dmem_wait <= #1 1'b1;
      end
      `OC8051_MAS_DPTR_W: begin  // write to external rom: (dptr)=acc
        dwe_o <= #1 1'b1;
        dstb_o <= #1 1'b1;
        ddat_o <= #1 acc;
        dadr_ot <= #1 {7'h0, dptr};
        dmem_wait <= #1 1'b1;
      end
      `OC8051_MAS_RI_R:   begin  // read from external rom: acc=(Ri)
        dwe_o <= #1 1'b0;
        dstb_o <= #1 1'b1;
        ddat_o <= #1 8'h00;
        dadr_ot <= #1 {15'h0, ri};
        dmem_wait <= #1 1'b1;
      end
      `OC8051_MAS_RI_W: begin    // write to external rom: (Ri)=acc
        dwe_o <= #1 1'b1;
        dstb_o <= #1 1'b1;
        ddat_o <= #1 acc;
        dadr_ot <= #1 {15'h0, ri};
        dmem_wait <= #1 1'b1;
      end
    endcase
  end
end
 
/////////////////////////////
//
// op_select
//
/////////////////////////////
 
 
assign op1 = ea_rom_sel ? op1_i: op1_xt;
assign op2 = ea_rom_sel ? op2_i: op2_xt;
assign op3 = ea_rom_sel ? op3_i: op3_xt;
 
 
always @(dack_ir or ddat_ir or op1_o or iram_out)
  if (dack_ir)
    op1_out = ddat_ir;
  else
    op1_out = op1_o;
 
assign op3_out = (rd) ? op3_o : op3_buff;
assign op2_out = (rd) ? op2_o : op2_buff;
 
always @(idat_i or iack_i or idat_ir or rd)
begin
  if (iack_i) begin
    op1_xt = idat_i[31:24];
    op2_xt = idat_i[23:16];
    op3_xt = idat_i[15:8];
  end else if (!rd) begin
    op1_xt = idat_ir[23:16];
    op2_xt = idat_ir[15:8];
    op3_xt = idat_ir[7:0];
  end else begin
    op1_xt = 8'h00;
    op2_xt = 8'h00;
    op3_xt = 8'h00;
  end
end
 
 
//
// in case of interrupts
always @(op1 or op2 or op3 or int_ack_t or int_vec_buff or iack_i or ea_rom_sel)
begin
  if (int_ack_t && (iack_i || ea_rom_sel)) begin
    op1_o = `OC8051_LCALL;
    op2_o = 8'h00;
    op3_o = int_vec_buff;
  end else begin
    op1_o = op1;
    op2_o = op2;
    op3_o = op3;
  end
end
 
//
//in case of reti
always @(posedge clk or posedge rst)
  if (rst) reti <= #1 1'b0;
  else if ((op1_o==`OC8051_RETI) & rd) reti <= #1 1'b1;
  else reti <= #1 1'b0;
 
//
// remember inputs
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    op2_buff <= #1 8'h0;
    op3_buff <= #1 8'h0;
  end else if (rd) begin
    op2_buff <= #1 op2_o;
    op3_buff <= #1 op3_o;
  end
end
 
//
// remember interrupt
// we don't want to interrupt instruction in the middle of execution
always @(posedge clk or posedge rst)
 if (rst) begin
   int_ack_t <= #1 1'b0;
   int_vec_buff <= #1 8'h00;
 end else if (intr) begin
   int_ack_t <= #1 1'b1;
   int_vec_buff <= #1 int_v;
 end else if (rd && (ea_rom_sel || iack_i)) int_ack_t <= #1 1'b0;
 
always @(posedge clk or posedge rst)
  if (rst) int_ack_buff <= #1 1'b0;
  else int_ack_buff <= #1 int_ack_t;
 
always @(posedge clk or posedge rst)
  if (rst) int_ack <= #1 1'b0;
  else begin
    if ((int_ack_buff) & !(int_ack_t))
      int_ack <= #1 1'b1;
    else int_ack <= #1 1'b0;
  end
 
 
/////////////////////////////
//
//  pc
//
/////////////////////////////
 
always @(pc_buf or op1_out or pc_wait or int_buff or int_buff1 or alu[7:0] or ea_rom_sel or iack_i)
begin
    if (int_buff || int_buff1) begin
//
//in case of interrupt hold valut, to be written to stack
      pc= pc_buf;
//    end else if (pis_l) begin
//      pc = {pc_buf[22:8], alu[7:0]};
    end else if (pc_wait) begin
        casex (op1_out)
          `OC8051_ACALL : pc= pc_buf + 23'h2;
          `OC8051_AJMP : pc= pc_buf + 23'h2;
 
        //op_code [7:3]
          `OC8051_CJNE_R : pc= pc_buf + 23'h3;
          `OC8051_DJNZ_R : pc= pc_buf + 23'h2;
          `OC8051_MOV_DR : pc= pc_buf + 23'h2;
          `OC8051_MOV_CR : pc= pc_buf + 23'h2;
          `OC8051_MOV_RD : pc= pc_buf + 23'h2;
 
        //op_code [7:1]
          `OC8051_CJNE_I : pc= pc_buf + 23'h3;
          `OC8051_MOV_ID : pc= pc_buf + 23'h2;
          `OC8051_MOV_DI : pc= pc_buf + 23'h2;
          `OC8051_MOV_CI : pc= pc_buf + 23'h2;
 
        //op_code [7:0]
          `OC8051_ADD_D : pc= pc_buf + 23'h2;
          `OC8051_ADD_C : pc= pc_buf + 23'h2;
          `OC8051_ADDC_D : pc= pc_buf + 23'h2;
          `OC8051_ADDC_C : pc= pc_buf + 23'h2;
          `OC8051_ANL_D : pc= pc_buf + 23'h2;
          `OC8051_ANL_C : pc= pc_buf + 23'h2;
          `OC8051_ANL_DD : pc= pc_buf + 23'h2;
          `OC8051_ANL_DC : pc= pc_buf + 23'h3;
          `OC8051_ANL_B : pc= pc_buf + 23'h2;
          `OC8051_ANL_NB : pc= pc_buf + 23'h2;
          `OC8051_CJNE_D : pc= pc_buf + 23'h3;
          `OC8051_CJNE_C : pc= pc_buf + 23'h3;
          `OC8051_CLR_B : pc= pc_buf + 23'h2;
          `OC8051_CPL_B : pc= pc_buf + 23'h2;
          `OC8051_DEC_D : pc= pc_buf + 23'h2;
          `OC8051_DJNZ_D : pc= pc_buf + 23'h3;
          `OC8051_INC_D : pc= pc_buf + 23'h2;
          `OC8051_JB : pc= pc_buf + 23'h3;
          `OC8051_JBC : pc= pc_buf + 23'h3;
          `OC8051_JC : pc= pc_buf + 23'h2;
          `OC8051_JNB : pc= pc_buf + 23'h3;
          `OC8051_JNC : pc= pc_buf + 23'h2;
          `OC8051_JNZ : pc= pc_buf + 23'h2;
          `OC8051_JZ : pc= pc_buf + 23'h2;
          `OC8051_LCALL :pc= pc_buf + 23'h3;
          `OC8051_LJMP : pc= pc_buf + 23'h3;
          `OC8051_MOV_D : pc= pc_buf + 23'h2;
          `OC8051_MOV_C : pc= pc_buf + 23'h2;
          `OC8051_MOV_DA : pc= pc_buf + 23'h2;
          `OC8051_MOV_DD : pc= pc_buf + 23'h3;
          `OC8051_MOV_CD : pc= pc_buf + 23'h3;
          `OC8051_MOV_BC : pc= pc_buf + 23'h2;
          `OC8051_MOV_CB : pc= pc_buf + 23'h2;
          `OC8051_MOV_DP : pc= pc_buf + 23'h3;
          `OC8051_ORL_D : pc= pc_buf + 23'h2;
          `OC8051_ORL_C : pc= pc_buf + 23'h2;
          `OC8051_ORL_AD : pc= pc_buf + 23'h2;
          `OC8051_ORL_CD : pc= pc_buf + 23'h3;
          `OC8051_ORL_B : pc= pc_buf + 23'h2;
          `OC8051_ORL_NB : pc= pc_buf + 23'h2;
          `OC8051_POP : pc= pc_buf + 23'h2;
          `OC8051_PUSH : pc= pc_buf + 23'h2;
          `OC8051_SETB_B : pc= pc_buf + 23'h2;
          `OC8051_SJMP : pc= pc_buf + 23'h2;
          `OC8051_SUBB_D : pc= pc_buf + 23'h2;
          `OC8051_SUBB_C : pc= pc_buf + 23'h2;
          `OC8051_XCH_D : pc= pc_buf + 23'h2;
          `OC8051_XRL_D : pc= pc_buf + 23'h2;
          `OC8051_XRL_C : pc= pc_buf + 23'h2;
          `OC8051_XRL_AD : pc= pc_buf + 23'h2;
          `OC8051_XRL_CD : pc= pc_buf + 23'h3;
          default: pc= pc_buf + 23'h1;
        endcase
//
//in case of instructions that use more than one clock hold current pc
    end else begin
      pc= pc_buf;
   end
end
 
 
//
//interrupt buffer
always @(posedge clk or posedge rst)
  if (rst) begin
    int_buff1 <= #1 1'b0;
  end else begin
    int_buff1 <= #1 int_buff;
  end
 
always @(posedge clk or posedge rst)
  if (rst) begin
    int_buff <= #1 1'b0;
  end else if (intr) begin
    int_buff <= #1 1'b1;
  end else if (pc_wait)
    int_buff <= #1 1'b0;
 
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    pc_buf <= #1 `OC8051_RST_PC;
  end else begin
    if (pc_wr) begin
//
//case of writing new value to pc (jupms)
      case (pc_wr_sel)
        `OC8051_PIS_ALU: pc_buf        <= #1 alu;
        `OC8051_PIS_AL:  pc_buf[7:0]   <= #1 alu[7:0];
        `OC8051_PIS_AH:  pc_buf[15:8]  <= #1 alu[7:0];
        `OC8051_PIS_I11: pc_buf[10:0]  <= #1 {op1_out[7:5], op2_out};
        `OC8051_PIS_I16: pc_buf        <= #1 {op2_out, op3_out};
      endcase
    end else
//
//or just remember current
      pc_buf <= #1 pc;
  end
end
 
 
always @(posedge clk or posedge rst)
  if (rst)
    ddat_ir <= #1 8'h00;
  else if (dack_i)
    ddat_ir <= #1 ddat_i;
 
////////////////////////
always @(posedge clk or posedge rst)
  if (rst) begin
    rn_r <= #1 5'd0;
    ri_r <= #1 8'h00;
    imm_r <= #1 8'h00;
    imm2_r <= #1 8'h00;
    rd_addr_r <= #1 3'h0;
    op1_r <= #1 8'h0;
    dack_ir <= #1 1'b0;
    sp_r <= #1 1'b0;
  end else begin
    rn_r <= #1 rn;
    ri_r <= #1 ri;
    imm_r <= #1 imm;
    imm2_r <= #1 imm2;
    rd_addr_r <= #1 rd_addr[7:5];
    op1_r <= #1 op1_out;
    dack_ir <= #1 dack_i;
    sp_r <= #1 sp;
  end
 
 
endmodule

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_memory_interface.v] - Blame information for rev 118

Line No.	Rev	Author	Line
1	81	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 memory interface ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// comunication betwen cpu and memory ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	118	simont	`// Revision 1.1 2003/01/13 14:13:12 simont`
48			`// initial import`
49	81	simont	`//`
50	118	simont	`//`
51	81	simont
52			`// synopsys translate_off`
53			`include "oc8051_timescale.v"
54			`// synopsys translate_on`
55
56			`include "oc8051_defines.v"
57
58
59			`module oc8051_memory_interface (clk, rst,`
60			`//decoder`
61			`wr_i, wr_bit_i, rd_sel, wr_sel,`
62			`pc_wr_sel, pc_wr, pc, rd,`
63			`mem_wait, mem_act, istb,`
64			`//internal ram`
65			`wr_o, wr_bit_o, rd_addr, wr_addr, rd_ind, wr_ind, wr_dat,`
66
67			`bit_in, in_ram, sfr, sfr_bit, bit_out, iram_out,`
68
69			`//program rom`
70			`iadr_o, ea, ea_int,`
71			`op1_out, op2_out, op3_out,`
72			`//internal`
73			`op1_i, op2_i, op3_i,`
74			`//external`
75			`iack_i, istb_o, idat_i,`
76
77			`//external data ram`
78			`dadr_o, dwe_o, dstb_o, dack_i, ddat_i, ddat_o,`
79			`//interrupt interface`
80			`intr, int_v, int_ack,`
81
82			`//alu`
83			`des1, des2,`
84
85			`//sfr's`
86			`dptr, ri, rn_mem, sp, sp_w, rn, acc, reti);`
87
88			`input bit_in, sfr_bit, dack_i;`
89			`input [2:0] mem_act;`
90			`input [7:0] in_ram, sfr, acc, sp_w;`
91			`input [31:0] idat_i;`
92
93			`output bit_out, mem_wait, reti;`
94			`output [7:0] iram_out, wr_dat;`
95
96			`reg bit_out, reti;`
97			`reg [7:0] iram_out, sp_r;`
98			`reg [2:0] rd_addr_r;`
99			`input clk, rst, wr_i, wr_bit_i;`
100			`output wr_o, wr_bit_o;`
101
102			`//????`
103			`reg dack_ir;`
104			`reg [7:0] ddat_ir;`
105			`reg [23:0] idat_ir;`
106
107			`/////////////////////////////`
108			`//`
109			`// rom_addr_sel`
110			`//`
111			`/////////////////////////////`
112			`input iack_i;`
113			`input [7:0] des1, des2;`
114			`output [15:0] iadr_o;`
115
116			`wire ea_rom_sel;`
117
118			`/////////////////////////////`
119			`//`
120			`// ext_addr_sel`
121			`//`
122			`/////////////////////////////`
123			`input [7:0] ri, rn_mem, ddat_i;`
124			`input [15:0] dptr;`
125
126			`output dstb_o, dwe_o;`
127			`output [7:0] ddat_o;`
128			`output [15:0] dadr_o;`
129
130			`/////////////////////////////`
131			`//`
132			`// ram_adr_sel`
133			`//`
134			`/////////////////////////////`
135
136			`input [2:0] rd_sel, wr_sel;`
137			`input [4:0] rn;`
138			`input [7:0] sp;`
139
140			`output rd_ind, wr_ind;`
141			`output [7:0] wr_addr, rd_addr;`
142			`reg rd_ind, wr_ind;`
143			`reg [7:0] wr_addr, rd_addr;`
144
145			`reg [4:0] rn_r;`
146			`reg [7:0] ri_r, imm_r, imm2_r, op1_r;`
147			`wire [7:0] imm, imm2;`
148
149			`/////////////////////////////`
150			`//`
151			`// op_select`
152			`//`
153			`/////////////////////////////`
154
155			`input intr, rd, ea, ea_int, istb;`
156			`input [7:0] op1_i, op2_i, op3_i, int_v;`
157			`output int_ack, istb_o;`
158			`output [7:0] op1_out, op3_out, op2_out;`
159
160			`reg int_ack_t, int_ack, int_ack_buff;`
161			`reg [7:0] int_vec_buff;`
162			`reg [7:0] op1_out, op2_buff, op3_buff;`
163			`reg [7:0] op1_o, op2_o, op3_o;`
164			`reg [7:0] op1_xt, op2_xt, op3_xt;`
165
166			`wire [7:0] op1, op2, op3, op2_direct;`
167			`//wire op_sel;`
168
169			`/////////////////////////////`
170			`//`
171			`// pc`
172			`//`
173			`/////////////////////////////`
174			`input [2:0] pc_wr_sel;`
175
176			`input pc_wr;`
177			`output [15:0] pc;`
178
179
180			`reg [15:0] pc;`
181
182			`//`
183			`//pc program counter register, save current value`
184			`reg [15:0] pc_buf;`
185			`wire [15:0] alu;`
186
187			`//`
188			`// wr_lo write low: used in reti instruction, write only low byte of pc`
189			`// ini_buff interrupt buffer: used to prevent interrupting in the middle of executin instructions`
190			`reg int_buff, int_buff1;`
191
192
193			`//`
194			`//`
195			`////////////////////////////`
196			`reg istb_t, imem_wait, dstb_o, dwe_o;`
197			`//reg [3:0] mem_act_r;`
198			`reg [7:0] ddat_o;`
199			`reg [15:0] iadr_t, dadr_ot;`
200			`reg dmem_wait;`
201			`wire pc_wait;`
202			`wire [1:0] bank;`
203			`//wire pis_l;`
204			`wire [15:0] iadr_ot;`
205			`wire [7:0] isr_call;`
206
207			`assign bank = rn[4:3];`
208			`assign imm = op2_out;`
209			`assign imm2 = op3_out;`
210			`assign alu = {des2,des1};`
211			`assign ea_rom_sel = ea && ea_int;`
212			`assign wr_o = wr_i;`
213			`assign wr_bit_o = wr_bit_i;`
214
215			`assign mem_wait = dmem_wait \|\| imem_wait;`
216			`//assign istb_o = (istb \|\| istb_t \|\| (!iack_i)) && !dstb_o && !ea_rom_sel;`
217			`assign istb_o = (istb \|\| istb_t) && !dstb_o && !ea_rom_sel;`
218
219			`assign pc_wait = rd && (ea_rom_sel \|\| (!istb_t && !(istb_o && !iack_i)));`
220
221			`assign wr_dat = des1;`
222
223
224			`/////////////////////////////`
225			`//`
226			`// ram_select`
227			`//`
228			`/////////////////////////////`
229			`always @(rd_addr_r or in_ram or sfr or bit_in or sfr_bit or rn_mem or rd_ind)`
230			`begin`
231			`if (rd_addr_r[2] && !rd_ind) begin`
232			`iram_out = sfr;`
233			`bit_out = sfr_bit;`
234			`end else if (~\|rd_addr_r[2:0]) begin`
235			`iram_out = rn_mem;`
236			`bit_out = bit_in;`
237			`end else begin`
238			`iram_out = in_ram;`
239			`bit_out = bit_in;`
240			`end`
241			`end`
242
243			`/////////////////////////////`
244			`//`
245			`// ram_adr_sel`
246			`//`
247			`/////////////////////////////`
248
249			`always @(rd_sel or sp or ri or rn or imm or op1_out or dadr_o[15:0] or bank)`
250			`begin`
251			`case (rd_sel)`
252			`OC8051_RRS_RN : rd_addr = {3'h0, rn};
253			`OC8051_RRS_I : rd_addr = ri;
254			`OC8051_RRS_D : rd_addr = imm;
255			`OC8051_RRS_SP : rd_addr = sp;
256
257			`OC8051_RRS_B : rd_addr = `OC8051_SFR_B;
258			`OC8051_RRS_DPTR : rd_addr = `OC8051_SFR_DPTR_LO;
259			`default : rd_addr = 2'bxx;`
260			`endcase`
261
262			`end`
263
264
265			`//`
266			`//`
267			`always @(wr_sel or sp_w or rn_r or imm_r or ri_r or imm2_r or op1_r or dadr_o[15:0])`
268			`begin`
269			`case (wr_sel)`
270			`OC8051_RWS_RN : wr_addr = {3'h0, rn_r};
271	118	simont	`OC8051_RWS_I : wr_addr = ri_r;
272			`OC8051_RWS_D : wr_addr = imm_r;
273	81	simont	`OC8051_RWS_SP : wr_addr = sp_w;
274			`OC8051_RWS_D3 : wr_addr = imm2_r;
275	118	simont	`OC8051_RWS_B : wr_addr = `OC8051_SFR_B;
276	81	simont	`default : wr_addr = 2'bxx;`
277			`endcase`
278			`end`
279
280			`always @(posedge clk or posedge rst)`
281			`if (rst)`
282			`rd_ind <= #1 1'b0;`
283			else if ((rd_sel==`OC8051_RRS_I) \|\| (rd_sel==`OC8051_RRS_SP))
284			`rd_ind <= #1 1'b1;`
285			`else`
286			`rd_ind <= #1 1'b0;`
287
288			`always @(wr_sel)`
289			if ((wr_sel==`OC8051_RWS_I) \|\| (wr_sel==`OC8051_RWS_SP))
290			`wr_ind = 1'b1;`
291			`else`
292			`wr_ind = 1'b0;`
293
294
295			`/////////////////////////////`
296			`//`
297			`// rom_addr_sel`
298			`//`
299			`/////////////////////////////`
300			`//`
301			`// output address is alu destination`
302			`// (instructions MOVC)`
303
304			`assign iadr_ot = istb_t ? iadr_t : pc;`
305			`assign iadr_o = iadr_ot;`
306
307
308			`always @(posedge clk or posedge rst)`
309			`begin`
310			`if (rst) begin`
311			`iadr_t <= #1 23'h0;`
312			`istb_t <= #1 1'b0;`
313			`imem_wait <= #1 1'b0;`
314			`idat_ir <= #1 24'h0;`
315			`end else if (iack_i) begin`
316			`istb_t <= #1 1'b0;`
317			`imem_wait <= #1 1'b0;`
318			`idat_ir <= #1 idat_i [31:8];`
319			`end else if (ea_rom_sel && imem_wait) begin`
320			`imem_wait <= #1 1'b0;`
321			`end else if (ea_rom_sel && !imem_wait && istb_t) begin`
322			`istb_t <= #1 1'b0;`
323			end else if (mem_act==`OC8051_MAS_CODE) begin
324			`iadr_t <= #1 {des2, des1};`
325			`istb_t <= #1 1'b1;`
326			`imem_wait <= #1 1'b1;`
327			`end`
328			`end`
329
330			`/////////////////////////////`
331			`//`
332			`// ext_addr_sel`
333			`//`
334			`/////////////////////////////`
335
336			`assign dadr_o = dadr_ot;`
337
338			`always @(posedge clk or posedge rst)`
339			`begin`
340			`if (rst) begin`
341			`dwe_o <= #1 1'b0;`
342			`dmem_wait <= #1 1'b0;`
343			`dstb_o <= #1 1'b0;`
344			`ddat_o <= #1 8'h00;`
345			`dadr_ot <= #1 23'h0;`
346			`end else if (dack_i) begin`
347			`dwe_o <= #1 1'b0;`
348			`dstb_o <= #1 1'b0;`
349			`dmem_wait <= #1 1'b0;`
350			`end else begin`
351			`case (mem_act)`
352			`OC8051_MAS_DPTR_R: begin // read from external rom: acc=(dptr)
353			`dwe_o <= #1 1'b0;`
354			`dstb_o <= #1 1'b1;`
355			`ddat_o <= #1 8'h00;`
356			`dadr_ot <= #1 {7'h0, dptr};`
357			`dmem_wait <= #1 1'b1;`
358			`end`
359			`OC8051_MAS_DPTR_W: begin // write to external rom: (dptr)=acc
360			`dwe_o <= #1 1'b1;`
361			`dstb_o <= #1 1'b1;`
362			`ddat_o <= #1 acc;`
363			`dadr_ot <= #1 {7'h0, dptr};`
364			`dmem_wait <= #1 1'b1;`
365			`end`
366			`OC8051_MAS_RI_R: begin // read from external rom: acc=(Ri)
367			`dwe_o <= #1 1'b0;`
368			`dstb_o <= #1 1'b1;`
369			`ddat_o <= #1 8'h00;`
370			`dadr_ot <= #1 {15'h0, ri};`
371			`dmem_wait <= #1 1'b1;`
372			`end`
373			`OC8051_MAS_RI_W: begin // write to external rom: (Ri)=acc
374			`dwe_o <= #1 1'b1;`
375			`dstb_o <= #1 1'b1;`
376			`ddat_o <= #1 acc;`
377			`dadr_ot <= #1 {15'h0, ri};`
378			`dmem_wait <= #1 1'b1;`
379			`end`
380			`endcase`
381			`end`
382			`end`
383
384			`/////////////////////////////`
385			`//`
386			`// op_select`
387			`//`
388			`/////////////////////////////`
389
390
391			`assign op1 = ea_rom_sel ? op1_i: op1_xt;`
392			`assign op2 = ea_rom_sel ? op2_i: op2_xt;`
393			`assign op3 = ea_rom_sel ? op3_i: op3_xt;`
394
395
396			`always @(dack_ir or ddat_ir or op1_o or iram_out)`
397			`if (dack_ir)`
398			`op1_out = ddat_ir;`
399			`else`
400			`op1_out = op1_o;`
401
402			`assign op3_out = (rd) ? op3_o : op3_buff;`
403			`assign op2_out = (rd) ? op2_o : op2_buff;`
404
405			`always @(idat_i or iack_i or idat_ir or rd)`
406			`begin`
407			`if (iack_i) begin`
408			`op1_xt = idat_i[31:24];`
409			`op2_xt = idat_i[23:16];`
410			`op3_xt = idat_i[15:8];`
411			`end else if (!rd) begin`
412			`op1_xt = idat_ir[23:16];`
413			`op2_xt = idat_ir[15:8];`
414			`op3_xt = idat_ir[7:0];`
415			`end else begin`
416			`op1_xt = 8'h00;`
417			`op2_xt = 8'h00;`
418			`op3_xt = 8'h00;`
419			`end`
420			`end`
421
422
423			`//`
424			`// in case of interrupts`
425			`always @(op1 or op2 or op3 or int_ack_t or int_vec_buff or iack_i or ea_rom_sel)`
426			`begin`
427			`if (int_ack_t && (iack_i \|\| ea_rom_sel)) begin`
428			op1_o = `OC8051_LCALL;
429			`op2_o = 8'h00;`
430			`op3_o = int_vec_buff;`
431			`end else begin`
432			`op1_o = op1;`
433			`op2_o = op2;`
434			`op3_o = op3;`
435			`end`
436			`end`
437
438			`//`
439			`//in case of reti`
440			`always @(posedge clk or posedge rst)`
441			`if (rst) reti <= #1 1'b0;`
442			else if ((op1_o==`OC8051_RETI) & rd) reti <= #1 1'b1;
443			`else reti <= #1 1'b0;`
444
445			`//`
446			`// remember inputs`
447			`always @(posedge clk or posedge rst)`
448			`begin`
449			`if (rst) begin`
450			`op2_buff <= #1 8'h0;`
451			`op3_buff <= #1 8'h0;`
452			`end else if (rd) begin`
453			`op2_buff <= #1 op2_o;`
454			`op3_buff <= #1 op3_o;`
455			`end`
456			`end`
457
458			`//`
459			`// remember interrupt`
460			`// we don't want to interrupt instruction in the middle of execution`
461			`always @(posedge clk or posedge rst)`
462			`if (rst) begin`
463			`int_ack_t <= #1 1'b0;`
464			`int_vec_buff <= #1 8'h00;`
465			`end else if (intr) begin`
466			`int_ack_t <= #1 1'b1;`
467			`int_vec_buff <= #1 int_v;`
468			`end else if (rd && (ea_rom_sel \|\| iack_i)) int_ack_t <= #1 1'b0;`
469
470			`always @(posedge clk or posedge rst)`
471			`if (rst) int_ack_buff <= #1 1'b0;`
472			`else int_ack_buff <= #1 int_ack_t;`
473
474			`always @(posedge clk or posedge rst)`
475			`if (rst) int_ack <= #1 1'b0;`
476			`else begin`
477			`if ((int_ack_buff) & !(int_ack_t))`
478			`int_ack <= #1 1'b1;`
479			`else int_ack <= #1 1'b0;`
480			`end`
481
482
483			`/////////////////////////////`
484			`//`
485			`// pc`
486			`//`
487			`/////////////////////////////`
488
489			`always @(pc_buf or op1_out or pc_wait or int_buff or int_buff1 or alu[7:0] or ea_rom_sel or iack_i)`
490			`begin`
491			`if (int_buff \|\| int_buff1) begin`
492			`//`
493			`//in case of interrupt hold valut, to be written to stack`
494			`pc= pc_buf;`
495			`// end else if (pis_l) begin`
496			`// pc = {pc_buf[22:8], alu[7:0]};`
497			`end else if (pc_wait) begin`
498			`casex (op1_out)`
499			`OC8051_ACALL : pc= pc_buf + 23'h2;
500			`OC8051_AJMP : pc= pc_buf + 23'h2;
501
502			`//op_code [7:3]`
503			`OC8051_CJNE_R : pc= pc_buf + 23'h3;
504			`OC8051_DJNZ_R : pc= pc_buf + 23'h2;
505			`OC8051_MOV_DR : pc= pc_buf + 23'h2;
506			`OC8051_MOV_CR : pc= pc_buf + 23'h2;
507			`OC8051_MOV_RD : pc= pc_buf + 23'h2;
508
509			`//op_code [7:1]`
510			`OC8051_CJNE_I : pc= pc_buf + 23'h3;
511			`OC8051_MOV_ID : pc= pc_buf + 23'h2;
512			`OC8051_MOV_DI : pc= pc_buf + 23'h2;
513			`OC8051_MOV_CI : pc= pc_buf + 23'h2;
514
515			`//op_code [7:0]`
516			`OC8051_ADD_D : pc= pc_buf + 23'h2;
517			`OC8051_ADD_C : pc= pc_buf + 23'h2;
518			`OC8051_ADDC_D : pc= pc_buf + 23'h2;
519			`OC8051_ADDC_C : pc= pc_buf + 23'h2;
520			`OC8051_ANL_D : pc= pc_buf + 23'h2;
521			`OC8051_ANL_C : pc= pc_buf + 23'h2;
522			`OC8051_ANL_DD : pc= pc_buf + 23'h2;
523			`OC8051_ANL_DC : pc= pc_buf + 23'h3;
524			`OC8051_ANL_B : pc= pc_buf + 23'h2;
525			`OC8051_ANL_NB : pc= pc_buf + 23'h2;
526			`OC8051_CJNE_D : pc= pc_buf + 23'h3;
527			`OC8051_CJNE_C : pc= pc_buf + 23'h3;
528			`OC8051_CLR_B : pc= pc_buf + 23'h2;
529			`OC8051_CPL_B : pc= pc_buf + 23'h2;
530			`OC8051_DEC_D : pc= pc_buf + 23'h2;
531			`OC8051_DJNZ_D : pc= pc_buf + 23'h3;
532			`OC8051_INC_D : pc= pc_buf + 23'h2;
533			`OC8051_JB : pc= pc_buf + 23'h3;
534			`OC8051_JBC : pc= pc_buf + 23'h3;
535			`OC8051_JC : pc= pc_buf + 23'h2;
536			`OC8051_JNB : pc= pc_buf + 23'h3;
537			`OC8051_JNC : pc= pc_buf + 23'h2;
538			`OC8051_JNZ : pc= pc_buf + 23'h2;
539			`OC8051_JZ : pc= pc_buf + 23'h2;
540			`OC8051_LCALL :pc= pc_buf + 23'h3;
541			`OC8051_LJMP : pc= pc_buf + 23'h3;
542			`OC8051_MOV_D : pc= pc_buf + 23'h2;
543			`OC8051_MOV_C : pc= pc_buf + 23'h2;
544			`OC8051_MOV_DA : pc= pc_buf + 23'h2;
545			`OC8051_MOV_DD : pc= pc_buf + 23'h3;
546			`OC8051_MOV_CD : pc= pc_buf + 23'h3;
547			`OC8051_MOV_BC : pc= pc_buf + 23'h2;
548			`OC8051_MOV_CB : pc= pc_buf + 23'h2;
549			`OC8051_MOV_DP : pc= pc_buf + 23'h3;
550			`OC8051_ORL_D : pc= pc_buf + 23'h2;
551			`OC8051_ORL_C : pc= pc_buf + 23'h2;
552			`OC8051_ORL_AD : pc= pc_buf + 23'h2;
553			`OC8051_ORL_CD : pc= pc_buf + 23'h3;
554			`OC8051_ORL_B : pc= pc_buf + 23'h2;
555			`OC8051_ORL_NB : pc= pc_buf + 23'h2;
556			`OC8051_POP : pc= pc_buf + 23'h2;
557			`OC8051_PUSH : pc= pc_buf + 23'h2;
558			`OC8051_SETB_B : pc= pc_buf + 23'h2;
559			`OC8051_SJMP : pc= pc_buf + 23'h2;
560			`OC8051_SUBB_D : pc= pc_buf + 23'h2;
561			`OC8051_SUBB_C : pc= pc_buf + 23'h2;
562			`OC8051_XCH_D : pc= pc_buf + 23'h2;
563			`OC8051_XRL_D : pc= pc_buf + 23'h2;
564			`OC8051_XRL_C : pc= pc_buf + 23'h2;
565			`OC8051_XRL_AD : pc= pc_buf + 23'h2;
566			`OC8051_XRL_CD : pc= pc_buf + 23'h3;
567			`default: pc= pc_buf + 23'h1;`
568			`endcase`
569			`//`
570			`//in case of instructions that use more than one clock hold current pc`
571			`end else begin`
572			`pc= pc_buf;`
573			`end`
574			`end`
575
576
577			`//`
578			`//interrupt buffer`
579			`always @(posedge clk or posedge rst)`
580			`if (rst) begin`
581			`int_buff1 <= #1 1'b0;`
582			`end else begin`
583			`int_buff1 <= #1 int_buff;`
584			`end`
585
586			`always @(posedge clk or posedge rst)`
587			`if (rst) begin`
588			`int_buff <= #1 1'b0;`
589			`end else if (intr) begin`
590			`int_buff <= #1 1'b1;`
591			`end else if (pc_wait)`
592			`int_buff <= #1 1'b0;`
593
594
595			`always @(posedge clk or posedge rst)`
596			`begin`
597			`if (rst) begin`
598			pc_buf <= #1 `OC8051_RST_PC;
599			`end else begin`
600			`if (pc_wr) begin`
601			`//`
602			`//case of writing new value to pc (jupms)`
603			`case (pc_wr_sel)`
604			`OC8051_PIS_ALU: pc_buf <= #1 alu;
605			`OC8051_PIS_AL: pc_buf[7:0] <= #1 alu[7:0];
606			`OC8051_PIS_AH: pc_buf[15:8] <= #1 alu[7:0];
607			`OC8051_PIS_I11: pc_buf[10:0] <= #1 {op1_out[7:5], op2_out};
608			`OC8051_PIS_I16: pc_buf <= #1 {op2_out, op3_out};
609			`endcase`
610			`end else`
611			`//`
612			`//or just remember current`
613			`pc_buf <= #1 pc;`
614			`end`
615			`end`
616
617
618			`always @(posedge clk or posedge rst)`
619			`if (rst)`
620			`ddat_ir <= #1 8'h00;`
621			`else if (dack_i)`
622			`ddat_ir <= #1 ddat_i;`
623
624			`////////////////////////`
625			`always @(posedge clk or posedge rst)`
626			`if (rst) begin`
627			`rn_r <= #1 5'd0;`
628			`ri_r <= #1 8'h00;`
629			`imm_r <= #1 8'h00;`
630			`imm2_r <= #1 8'h00;`
631			`rd_addr_r <= #1 3'h0;`
632			`op1_r <= #1 8'h0;`
633			`dack_ir <= #1 1'b0;`
634			`sp_r <= #1 1'b0;`
635			`end else begin`
636			`rn_r <= #1 rn;`
637			`ri_r <= #1 ri;`
638			`imm_r <= #1 imm;`
639			`imm2_r <= #1 imm2;`
640			`rd_addr_r <= #1 rd_addr[7:5];`
641			`op1_r <= #1 op1_out;`
642			`dack_ir <= #1 dack_i;`
643			`sp_r <= #1 sp;`
644			`end`
645
646
647			`endmodule`