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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_memory_interface.v] - Blame information for rev 121

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 memory interface                                       ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   comunication betwen cpu and memory                         ////
////                                                              ////
////  To Do:                                                      ////
////   nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2003/04/09 16:24:03  simont
// change wr_sft to 2 bit wire.
//
// Revision 1.1  2003/01/13 14:13:12  simont
// initial import
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
module oc8051_memory_interface (clk, rst,
//decoder
  wr_i, wr_bit_i, rd_sel, wr_sel,
  pc_wr_sel, pc_wr, pc, rd,
  mem_wait, mem_act, istb,
//internal ram
  wr_o, wr_bit_o, rd_addr, wr_addr, rd_ind, wr_ind, wr_dat,
 
  bit_in, in_ram, sfr, sfr_bit, bit_out, iram_out,
 
//program rom
  iadr_o, ea, ea_int,
  op1_out, op2_out, op3_out,
//internal
  op1_i, op2_i, op3_i,
//external
  iack_i, istb_o, idat_i,
 
//external data ram
  dadr_o, dwe_o, dstb_o, dack_i, ddat_i, ddat_o,
//interrupt interface
  intr, int_v, int_ack,
 
//alu
  des1, des2,
 
//sfr's
  dptr, ri, rn_mem, sp,  sp_w, rn, acc, reti);
 
input bit_in, sfr_bit, dack_i;
input [2:0] mem_act;
input [7:0] in_ram, sfr, acc, sp_w;
input [31:0] idat_i;
 
output bit_out, mem_wait, reti;
output [7:0] iram_out, wr_dat;
 
reg bit_out, reti;
reg [7:0] iram_out, sp_r;
reg [2:0] rd_addr_r;
input clk, rst, wr_i, wr_bit_i;
output wr_o, wr_bit_o;
 
//????
reg dack_ir;
reg [7:0] ddat_ir;
reg [23:0] idat_ir;
 
/////////////////////////////
//
//  rom_addr_sel
//
/////////////////////////////
input iack_i;
input [7:0] des1, des2;
output [15:0] iadr_o;
 
wire ea_rom_sel;
 
/////////////////////////////
//
// ext_addr_sel
//
/////////////////////////////
input [7:0] ri, rn_mem, ddat_i;
input [15:0] dptr;
 
output dstb_o, dwe_o;
output [7:0] ddat_o;
output [15:0] dadr_o;
 
/////////////////////////////
//
// ram_adr_sel
//
/////////////////////////////
 
input [2:0] rd_sel, wr_sel;
input [4:0] rn;
input [7:0] sp;
 
output rd_ind, wr_ind;
output [7:0] wr_addr, rd_addr;
reg rd_ind, wr_ind;
reg [7:0] wr_addr, rd_addr;
 
reg [4:0] rn_r;
reg [7:0] ri_r, imm_r, imm2_r, op1_r;
wire [7:0] imm, imm2;
 
/////////////////////////////
//
// op_select
//
/////////////////////////////
 
input intr, rd, ea, ea_int, istb;
input [7:0] op1_i, op2_i, op3_i, int_v;
output int_ack, istb_o;
output [7:0] op1_out, op3_out, op2_out;
 
reg int_ack_t, int_ack, int_ack_buff;
reg [7:0] int_vec_buff;
reg [7:0] op1_out, op2_buff, op3_buff;
reg [7:0] op1_o, op2_o, op3_o;
reg [7:0] op1_xt, op2_xt, op3_xt;
 
wire [7:0] op1, op2, op3, op2_direct;
//wire op_sel;
 
/////////////////////////////
//
//  pc
//
/////////////////////////////
input [2:0] pc_wr_sel;
 
input pc_wr;
output [15:0] pc;
 
 
reg [15:0] pc;
 
//
//pc            program counter register, save current value
reg [15:0] pc_buf;
wire [15:0] alu;
 
//
// wr_lo        write low: used in reti instruction, write only low byte of pc
// ini_buff     interrupt buffer: used to prevent interrupting in the middle of executin instructions
reg int_buff, int_buff1;
 
 
//
//
////////////////////////////
reg istb_t, imem_wait, dstb_o, dwe_o;
//reg [3:0] mem_act_r;
reg [7:0] ddat_o;
reg [15:0] iadr_t, dadr_ot;
reg dmem_wait;
wire pc_wait;
wire [1:0] bank;
//wire pis_l;
wire [15:0] iadr_ot;
wire [7:0] isr_call;
 
assign bank = rn[4:3];
assign imm = op2_out;
assign imm2 = op3_out;
assign alu = {des2,des1};
assign ea_rom_sel = ea && ea_int;
assign wr_o = wr_i;
assign wr_bit_o = wr_bit_i;
 
assign mem_wait = dmem_wait || imem_wait;
//assign istb_o = (istb || istb_t || (!iack_i)) && !dstb_o && !ea_rom_sel;
assign istb_o = (istb || istb_t) && !dstb_o && !ea_rom_sel;
 
assign pc_wait = rd && (ea_rom_sel || (!istb_t && !(istb_o && !iack_i)));
 
assign wr_dat = des1;
 
 
/////////////////////////////
//
//  ram_select
//
/////////////////////////////
always @(rd_addr_r or in_ram or sfr or bit_in or sfr_bit or rn_mem or rd_ind)
begin
  if (rd_addr_r[2] && !rd_ind) begin
    iram_out = sfr;
    bit_out = sfr_bit;
  end else if (~|rd_addr_r[2:0]) begin
    iram_out = rn_mem;
    bit_out = bit_in;
  end else begin
    iram_out = in_ram;
    bit_out = bit_in;
  end
end
 
/////////////////////////////
//
// ram_adr_sel
//
/////////////////////////////
 
always @(rd_sel or sp or ri or rn or imm or op1_out or dadr_o[15:0] or bank)
begin
     case (rd_sel)
      `OC8051_RRS_RN : rd_addr = {3'h0, rn};
      `OC8051_RRS_I : rd_addr = ri;
      `OC8051_RRS_D : rd_addr = imm;
      `OC8051_RRS_SP : rd_addr = sp;
 
      `OC8051_RRS_B : rd_addr = `OC8051_SFR_B;
      `OC8051_RRS_DPTR : rd_addr = `OC8051_SFR_DPTR_LO;
      default : rd_addr = 2'bxx;
    endcase
 
end
 
 
//
//
always @(wr_sel or sp_w or rn_r or imm_r or ri_r or imm2_r or op1_r or dadr_o[15:0])
begin
    case (wr_sel)
      `OC8051_RWS_RN : wr_addr = {3'h0, rn_r};
      `OC8051_RWS_I  : wr_addr = ri_r;
      `OC8051_RWS_D  : wr_addr = imm_r;
      `OC8051_RWS_SP : wr_addr = sp_w;
      `OC8051_RWS_D3 : wr_addr = imm2_r;
      `OC8051_RWS_B  : wr_addr = `OC8051_SFR_B;
      default : wr_addr = 2'bxx;
    endcase
end
 
always @(posedge clk or posedge rst)
  if (rst)
    rd_ind <= #1 1'b0;
  else if ((rd_sel==`OC8051_RRS_I) || (rd_sel==`OC8051_RRS_SP))
    rd_ind <= #1 1'b1;
  else
    rd_ind <= #1 1'b0;
 
always @(wr_sel)
  if ((wr_sel==`OC8051_RWS_I) || (wr_sel==`OC8051_RWS_SP))
    wr_ind = 1'b1;
  else
    wr_ind = 1'b0;
 
 
/////////////////////////////
//
//  rom_addr_sel
//
/////////////////////////////
//
// output address is alu destination
// (instructions MOVC)
 
assign iadr_ot = istb_t ? iadr_t : pc;
assign iadr_o = iadr_ot;
 
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    iadr_t <= #1 23'h0;
    istb_t <= #1 1'b0;
    imem_wait <= #1 1'b0;
    idat_ir <= #1 24'h0;
  end else if (iack_i) begin
    istb_t <= #1 1'b0;
    imem_wait <= #1 1'b0;
    idat_ir <= #1 idat_i [31:8];
  end else if (ea_rom_sel && imem_wait) begin
    imem_wait <= #1 1'b0;
  end else if (ea_rom_sel && !imem_wait && istb_t) begin
    istb_t <= #1 1'b0;
  end else if (mem_act==`OC8051_MAS_CODE) begin
    iadr_t <= #1 {des2, des1};
    istb_t <= #1 1'b1;
    imem_wait <= #1 1'b1;
  end
end
 
/////////////////////////////
//
// ext_addr_sel
//
/////////////////////////////
 
assign dadr_o = dadr_ot;
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    dwe_o <= #1 1'b0;
    dmem_wait <= #1 1'b0;
    dstb_o <= #1 1'b0;
    ddat_o <= #1 8'h00;
    dadr_ot <= #1 23'h0;
  end else if (dack_i) begin
    dwe_o <= #1 1'b0;
    dstb_o <= #1 1'b0;
    dmem_wait <= #1 1'b0;
  end else begin
    case (mem_act)
      `OC8051_MAS_DPTR_R: begin  // read from external rom: acc=(dptr)
        dwe_o <= #1 1'b0;
        dstb_o <= #1 1'b1;
        ddat_o <= #1 8'h00;
        dadr_ot <= #1 {7'h0, dptr};
        dmem_wait <= #1 1'b1;
      end
      `OC8051_MAS_DPTR_W: begin  // write to external rom: (dptr)=acc
        dwe_o <= #1 1'b1;
        dstb_o <= #1 1'b1;
        ddat_o <= #1 acc;
        dadr_ot <= #1 {7'h0, dptr};
        dmem_wait <= #1 1'b1;
      end
      `OC8051_MAS_RI_R:   begin  // read from external rom: acc=(Ri)
        dwe_o <= #1 1'b0;
        dstb_o <= #1 1'b1;
        ddat_o <= #1 8'h00;
        dadr_ot <= #1 {15'h0, ri};
        dmem_wait <= #1 1'b1;
      end
      `OC8051_MAS_RI_W: begin    // write to external rom: (Ri)=acc
        dwe_o <= #1 1'b1;
        dstb_o <= #1 1'b1;
        ddat_o <= #1 acc;
        dadr_ot <= #1 {15'h0, ri};
        dmem_wait <= #1 1'b1;
      end
    endcase
  end
end
 
/////////////////////////////
//
// op_select
//
/////////////////////////////
 
 
assign op1 = ea_rom_sel ? op1_i: op1_xt;
assign op2 = ea_rom_sel ? op2_i: op2_xt;
assign op3 = ea_rom_sel ? op3_i: op3_xt;
 
 
always @(dack_ir or ddat_ir or op1_o or iram_out)
  if (dack_ir)
    op1_out = ddat_ir;
  else
    op1_out = op1_o;
 
assign op3_out = (rd) ? op3_o : op3_buff;
assign op2_out = (rd) ? op2_o : op2_buff;
 
always @(idat_i or iack_i or idat_ir or rd)
begin
  if (iack_i) begin
    op1_xt = idat_i[31:24];
    op2_xt = idat_i[23:16];
    op3_xt = idat_i[15:8];
  end else if (!rd) begin
    op1_xt = idat_ir[23:16];
    op2_xt = idat_ir[15:8];
    op3_xt = idat_ir[7:0];
  end else begin
    op1_xt = 8'h00;
    op2_xt = 8'h00;
    op3_xt = 8'h00;
  end
end
 
 
//
// in case of interrupts
always @(op1 or op2 or op3 or int_ack_t or int_vec_buff or iack_i or ea_rom_sel)
begin
  if (int_ack_t && (iack_i || ea_rom_sel)) begin
    op1_o = `OC8051_LCALL;
    op2_o = 8'h00;
    op3_o = int_vec_buff;
  end else begin
    op1_o = op1;
    op2_o = op2;
    op3_o = op3;
  end
end
 
//
//in case of reti
always @(posedge clk or posedge rst)
  if (rst) reti <= #1 1'b0;
  else if ((op1_o==`OC8051_RETI) & rd) reti <= #1 1'b1;
  else reti <= #1 1'b0;
 
//
// remember inputs
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    op2_buff <= #1 8'h0;
    op3_buff <= #1 8'h0;
  end else if (rd) begin
    op2_buff <= #1 op2_o;
    op3_buff <= #1 op3_o;
  end
end
 
//
// remember interrupt
// we don't want to interrupt instruction in the middle of execution
always @(posedge clk or posedge rst)
 if (rst) begin
   int_ack_t <= #1 1'b0;
   int_vec_buff <= #1 8'h00;
 end else if (intr) begin
   int_ack_t <= #1 1'b1;
   int_vec_buff <= #1 int_v;
 end else if (rd && (ea_rom_sel || iack_i)) int_ack_t <= #1 1'b0;
 
always @(posedge clk or posedge rst)
  if (rst) int_ack_buff <= #1 1'b0;
  else int_ack_buff <= #1 int_ack_t;
 
always @(posedge clk or posedge rst)
  if (rst) int_ack <= #1 1'b0;
  else begin
    if ((int_ack_buff) & !(int_ack_t))
      int_ack <= #1 1'b1;
    else int_ack <= #1 1'b0;
  end
 
 
/////////////////////////////
//
//  pc
//
/////////////////////////////
 
always @(pc_buf or op1_out or pc_wait or int_buff or int_buff1 or alu[7:0] or ea_rom_sel or iack_i)
begin
    if (int_buff || int_buff1) begin
//
//in case of interrupt hold valut, to be written to stack
      pc= pc_buf;
//    end else if (pis_l) begin
//      pc = {pc_buf[22:8], alu[7:0]};
    end else if (pc_wait) begin
        casex (op1_out)
          `OC8051_ACALL :  pc= pc_buf + 16'h2;
          `OC8051_AJMP :   pc= pc_buf + 16'h2;
 
        //op_code [7:3]
          `OC8051_CJNE_R : pc= pc_buf + 16'h3;
          `OC8051_DJNZ_R : pc= pc_buf + 16'h2;
          `OC8051_MOV_DR : pc= pc_buf + 16'h2;
          `OC8051_MOV_CR : pc= pc_buf + 16'h2;
          `OC8051_MOV_RD : pc= pc_buf + 16'h2;
 
        //op_code [7:1]
          `OC8051_CJNE_I : pc= pc_buf + 16'h3;
          `OC8051_MOV_ID : pc= pc_buf + 16'h2;
          `OC8051_MOV_DI : pc= pc_buf + 16'h2;
          `OC8051_MOV_CI : pc= pc_buf + 16'h2;
 
        //op_code [7:0]
          `OC8051_ADD_D :  pc= pc_buf + 16'h2;
          `OC8051_ADD_C :  pc= pc_buf + 16'h2;
          `OC8051_ADDC_D : pc= pc_buf + 16'h2;
          `OC8051_ADDC_C : pc= pc_buf + 16'h2;
          `OC8051_ANL_D :  pc= pc_buf + 16'h2;
          `OC8051_ANL_C :  pc= pc_buf + 16'h2;
          `OC8051_ANL_DD : pc= pc_buf + 16'h2;
          `OC8051_ANL_DC : pc= pc_buf + 16'h3;
          `OC8051_ANL_B :  pc= pc_buf + 16'h2;
          `OC8051_ANL_NB : pc= pc_buf + 16'h2;
          `OC8051_CJNE_D : pc= pc_buf + 16'h3;
          `OC8051_CJNE_C : pc= pc_buf + 16'h3;
          `OC8051_CLR_B :  pc= pc_buf + 16'h2;
          `OC8051_CPL_B :  pc= pc_buf + 16'h2;
          `OC8051_DEC_D :  pc= pc_buf + 16'h2;
          `OC8051_DJNZ_D : pc= pc_buf + 16'h3;
          `OC8051_INC_D :  pc= pc_buf + 16'h2;
          `OC8051_JB :     pc= pc_buf + 16'h3;
          `OC8051_JBC :    pc= pc_buf + 16'h3;
          `OC8051_JC :     pc= pc_buf + 16'h2;
          `OC8051_JNB :    pc= pc_buf + 16'h3;
          `OC8051_JNC :    pc= pc_buf + 16'h2;
          `OC8051_JNZ :    pc= pc_buf + 16'h2;
          `OC8051_JZ :     pc= pc_buf + 16'h2;
          `OC8051_LCALL :  pc= pc_buf + 16'h3;
          `OC8051_LJMP :   pc= pc_buf + 16'h3;
          `OC8051_MOV_D :  pc= pc_buf + 16'h2;
          `OC8051_MOV_C :  pc= pc_buf + 16'h2;
          `OC8051_MOV_DA : pc= pc_buf + 16'h2;
          `OC8051_MOV_DD : pc= pc_buf + 16'h3;
          `OC8051_MOV_CD : pc= pc_buf + 16'h3;
          `OC8051_MOV_BC : pc= pc_buf + 16'h2;
          `OC8051_MOV_CB : pc= pc_buf + 16'h2;
          `OC8051_MOV_DP : pc= pc_buf + 16'h3;
          `OC8051_ORL_D :  pc= pc_buf + 16'h2;
          `OC8051_ORL_C :  pc= pc_buf + 16'h2;
          `OC8051_ORL_AD : pc= pc_buf + 16'h2;
          `OC8051_ORL_CD : pc= pc_buf + 16'h3;
          `OC8051_ORL_B :  pc= pc_buf + 16'h2;
          `OC8051_ORL_NB : pc= pc_buf + 16'h2;
          `OC8051_POP :    pc= pc_buf + 16'h2;
          `OC8051_PUSH :   pc= pc_buf + 16'h2;
          `OC8051_SETB_B : pc= pc_buf + 16'h2;
          `OC8051_SJMP :   pc= pc_buf + 16'h2;
          `OC8051_SUBB_D : pc= pc_buf + 16'h2;
          `OC8051_SUBB_C : pc= pc_buf + 16'h2;
          `OC8051_XCH_D :  pc= pc_buf + 16'h2;
          `OC8051_XRL_D :  pc= pc_buf + 16'h2;
          `OC8051_XRL_C :  pc= pc_buf + 16'h2;
          `OC8051_XRL_AD : pc= pc_buf + 16'h2;
          `OC8051_XRL_CD : pc= pc_buf + 16'h3;
          default:         pc= pc_buf + 16'h1;
        endcase
//
//in case of instructions that use more than one clock hold current pc
    end else begin
      pc= pc_buf;
   end
end
 
 
//
//interrupt buffer
always @(posedge clk or posedge rst)
  if (rst) begin
    int_buff1 <= #1 1'b0;
  end else begin
    int_buff1 <= #1 int_buff;
  end
 
always @(posedge clk or posedge rst)
  if (rst) begin
    int_buff <= #1 1'b0;
  end else if (intr) begin
    int_buff <= #1 1'b1;
  end else if (pc_wait)
    int_buff <= #1 1'b0;
 
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    pc_buf <= #1 `OC8051_RST_PC;
  end else begin
    if (pc_wr) begin
//
//case of writing new value to pc (jupms)
      case (pc_wr_sel)
        `OC8051_PIS_ALU: pc_buf        <= #1 alu;
        `OC8051_PIS_AL:  pc_buf[7:0]   <= #1 alu[7:0];
        `OC8051_PIS_AH:  pc_buf[15:8]  <= #1 alu[7:0];
        `OC8051_PIS_I11: pc_buf[10:0]  <= #1 {op1_out[7:5], op2_out};
        `OC8051_PIS_I16: pc_buf        <= #1 {op2_out, op3_out};
      endcase
    end else
//
//or just remember current
      pc_buf <= #1 pc;
  end
end
 
 
always @(posedge clk or posedge rst)
  if (rst)
    ddat_ir <= #1 8'h00;
  else if (dack_i)
    ddat_ir <= #1 ddat_i;
 
////////////////////////
always @(posedge clk or posedge rst)
  if (rst) begin
    rn_r <= #1 5'd0;
    ri_r <= #1 8'h00;
    imm_r <= #1 8'h00;
    imm2_r <= #1 8'h00;
    rd_addr_r <= #1 3'h0;
    op1_r <= #1 8'h0;
    dack_ir <= #1 1'b0;
    sp_r <= #1 1'b0;
  end else begin
    rn_r <= #1 rn;
    ri_r <= #1 ri;
    imm_r <= #1 imm;
    imm2_r <= #1 imm2;
    rd_addr_r <= #1 rd_addr[7:5];
    op1_r <= #1 op1_out;
    dack_ir <= #1 dack_i;
    sp_r <= #1 sp;
  end
 
 
endmodule

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_memory_interface.v] - Blame information for rev 121

Line No.	Rev	Author	Line
1	81	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 memory interface ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// comunication betwen cpu and memory ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	121	simont	`// Revision 1.2 2003/04/09 16:24:03 simont`
48			`// change wr_sft to 2 bit wire.`
49			`//`
50	118	simont	`// Revision 1.1 2003/01/13 14:13:12 simont`
51			`// initial import`
52	81	simont	`//`
53	118	simont	`//`
54	81	simont
55			`// synopsys translate_off`
56			`include "oc8051_timescale.v"
57			`// synopsys translate_on`
58
59			`include "oc8051_defines.v"
60
61
62			`module oc8051_memory_interface (clk, rst,`
63			`//decoder`
64			`wr_i, wr_bit_i, rd_sel, wr_sel,`
65			`pc_wr_sel, pc_wr, pc, rd,`
66			`mem_wait, mem_act, istb,`
67			`//internal ram`
68			`wr_o, wr_bit_o, rd_addr, wr_addr, rd_ind, wr_ind, wr_dat,`
69
70			`bit_in, in_ram, sfr, sfr_bit, bit_out, iram_out,`
71
72			`//program rom`
73			`iadr_o, ea, ea_int,`
74			`op1_out, op2_out, op3_out,`
75			`//internal`
76			`op1_i, op2_i, op3_i,`
77			`//external`
78			`iack_i, istb_o, idat_i,`
79
80			`//external data ram`
81			`dadr_o, dwe_o, dstb_o, dack_i, ddat_i, ddat_o,`
82			`//interrupt interface`
83			`intr, int_v, int_ack,`
84
85			`//alu`
86			`des1, des2,`
87
88			`//sfr's`
89			`dptr, ri, rn_mem, sp, sp_w, rn, acc, reti);`
90
91			`input bit_in, sfr_bit, dack_i;`
92			`input [2:0] mem_act;`
93			`input [7:0] in_ram, sfr, acc, sp_w;`
94			`input [31:0] idat_i;`
95
96			`output bit_out, mem_wait, reti;`
97			`output [7:0] iram_out, wr_dat;`
98
99			`reg bit_out, reti;`
100			`reg [7:0] iram_out, sp_r;`
101			`reg [2:0] rd_addr_r;`
102			`input clk, rst, wr_i, wr_bit_i;`
103			`output wr_o, wr_bit_o;`
104
105			`//????`
106			`reg dack_ir;`
107			`reg [7:0] ddat_ir;`
108			`reg [23:0] idat_ir;`
109
110			`/////////////////////////////`
111			`//`
112			`// rom_addr_sel`
113			`//`
114			`/////////////////////////////`
115			`input iack_i;`
116			`input [7:0] des1, des2;`
117			`output [15:0] iadr_o;`
118
119			`wire ea_rom_sel;`
120
121			`/////////////////////////////`
122			`//`
123			`// ext_addr_sel`
124			`//`
125			`/////////////////////////////`
126			`input [7:0] ri, rn_mem, ddat_i;`
127			`input [15:0] dptr;`
128
129			`output dstb_o, dwe_o;`
130			`output [7:0] ddat_o;`
131			`output [15:0] dadr_o;`
132
133			`/////////////////////////////`
134			`//`
135			`// ram_adr_sel`
136			`//`
137			`/////////////////////////////`
138
139			`input [2:0] rd_sel, wr_sel;`
140			`input [4:0] rn;`
141			`input [7:0] sp;`
142
143			`output rd_ind, wr_ind;`
144			`output [7:0] wr_addr, rd_addr;`
145			`reg rd_ind, wr_ind;`
146			`reg [7:0] wr_addr, rd_addr;`
147
148			`reg [4:0] rn_r;`
149			`reg [7:0] ri_r, imm_r, imm2_r, op1_r;`
150			`wire [7:0] imm, imm2;`
151
152			`/////////////////////////////`
153			`//`
154			`// op_select`
155			`//`
156			`/////////////////////////////`
157
158			`input intr, rd, ea, ea_int, istb;`
159			`input [7:0] op1_i, op2_i, op3_i, int_v;`
160			`output int_ack, istb_o;`
161			`output [7:0] op1_out, op3_out, op2_out;`
162
163			`reg int_ack_t, int_ack, int_ack_buff;`
164			`reg [7:0] int_vec_buff;`
165			`reg [7:0] op1_out, op2_buff, op3_buff;`
166			`reg [7:0] op1_o, op2_o, op3_o;`
167			`reg [7:0] op1_xt, op2_xt, op3_xt;`
168
169			`wire [7:0] op1, op2, op3, op2_direct;`
170			`//wire op_sel;`
171
172			`/////////////////////////////`
173			`//`
174			`// pc`
175			`//`
176			`/////////////////////////////`
177			`input [2:0] pc_wr_sel;`
178
179			`input pc_wr;`
180			`output [15:0] pc;`
181
182
183			`reg [15:0] pc;`
184
185			`//`
186			`//pc program counter register, save current value`
187			`reg [15:0] pc_buf;`
188			`wire [15:0] alu;`
189
190			`//`
191			`// wr_lo write low: used in reti instruction, write only low byte of pc`
192			`// ini_buff interrupt buffer: used to prevent interrupting in the middle of executin instructions`
193			`reg int_buff, int_buff1;`
194
195
196			`//`
197			`//`
198			`////////////////////////////`
199			`reg istb_t, imem_wait, dstb_o, dwe_o;`
200			`//reg [3:0] mem_act_r;`
201			`reg [7:0] ddat_o;`
202			`reg [15:0] iadr_t, dadr_ot;`
203			`reg dmem_wait;`
204			`wire pc_wait;`
205			`wire [1:0] bank;`
206			`//wire pis_l;`
207			`wire [15:0] iadr_ot;`
208			`wire [7:0] isr_call;`
209
210			`assign bank = rn[4:3];`
211			`assign imm = op2_out;`
212			`assign imm2 = op3_out;`
213			`assign alu = {des2,des1};`
214			`assign ea_rom_sel = ea && ea_int;`
215			`assign wr_o = wr_i;`
216			`assign wr_bit_o = wr_bit_i;`
217
218			`assign mem_wait = dmem_wait \|\| imem_wait;`
219			`//assign istb_o = (istb \|\| istb_t \|\| (!iack_i)) && !dstb_o && !ea_rom_sel;`
220			`assign istb_o = (istb \|\| istb_t) && !dstb_o && !ea_rom_sel;`
221
222			`assign pc_wait = rd && (ea_rom_sel \|\| (!istb_t && !(istb_o && !iack_i)));`
223
224			`assign wr_dat = des1;`
225
226
227			`/////////////////////////////`
228			`//`
229			`// ram_select`
230			`//`
231			`/////////////////////////////`
232			`always @(rd_addr_r or in_ram or sfr or bit_in or sfr_bit or rn_mem or rd_ind)`
233			`begin`
234			`if (rd_addr_r[2] && !rd_ind) begin`
235			`iram_out = sfr;`
236			`bit_out = sfr_bit;`
237			`end else if (~\|rd_addr_r[2:0]) begin`
238			`iram_out = rn_mem;`
239			`bit_out = bit_in;`
240			`end else begin`
241			`iram_out = in_ram;`
242			`bit_out = bit_in;`
243			`end`
244			`end`
245
246			`/////////////////////////////`
247			`//`
248			`// ram_adr_sel`
249			`//`
250			`/////////////////////////////`
251
252			`always @(rd_sel or sp or ri or rn or imm or op1_out or dadr_o[15:0] or bank)`
253			`begin`
254			`case (rd_sel)`
255			`OC8051_RRS_RN : rd_addr = {3'h0, rn};
256			`OC8051_RRS_I : rd_addr = ri;
257			`OC8051_RRS_D : rd_addr = imm;
258			`OC8051_RRS_SP : rd_addr = sp;
259
260			`OC8051_RRS_B : rd_addr = `OC8051_SFR_B;
261			`OC8051_RRS_DPTR : rd_addr = `OC8051_SFR_DPTR_LO;
262			`default : rd_addr = 2'bxx;`
263			`endcase`
264
265			`end`
266
267
268			`//`
269			`//`
270			`always @(wr_sel or sp_w or rn_r or imm_r or ri_r or imm2_r or op1_r or dadr_o[15:0])`
271			`begin`
272			`case (wr_sel)`
273			`OC8051_RWS_RN : wr_addr = {3'h0, rn_r};
274	118	simont	`OC8051_RWS_I : wr_addr = ri_r;
275			`OC8051_RWS_D : wr_addr = imm_r;
276	81	simont	`OC8051_RWS_SP : wr_addr = sp_w;
277			`OC8051_RWS_D3 : wr_addr = imm2_r;
278	118	simont	`OC8051_RWS_B : wr_addr = `OC8051_SFR_B;
279	81	simont	`default : wr_addr = 2'bxx;`
280			`endcase`
281			`end`
282
283			`always @(posedge clk or posedge rst)`
284			`if (rst)`
285			`rd_ind <= #1 1'b0;`
286			else if ((rd_sel==`OC8051_RRS_I) \|\| (rd_sel==`OC8051_RRS_SP))
287			`rd_ind <= #1 1'b1;`
288			`else`
289			`rd_ind <= #1 1'b0;`
290
291			`always @(wr_sel)`
292			if ((wr_sel==`OC8051_RWS_I) \|\| (wr_sel==`OC8051_RWS_SP))
293			`wr_ind = 1'b1;`
294			`else`
295			`wr_ind = 1'b0;`
296
297
298			`/////////////////////////////`
299			`//`
300			`// rom_addr_sel`
301			`//`
302			`/////////////////////////////`
303			`//`
304			`// output address is alu destination`
305			`// (instructions MOVC)`
306
307			`assign iadr_ot = istb_t ? iadr_t : pc;`
308			`assign iadr_o = iadr_ot;`
309
310
311			`always @(posedge clk or posedge rst)`
312			`begin`
313			`if (rst) begin`
314			`iadr_t <= #1 23'h0;`
315			`istb_t <= #1 1'b0;`
316			`imem_wait <= #1 1'b0;`
317			`idat_ir <= #1 24'h0;`
318			`end else if (iack_i) begin`
319			`istb_t <= #1 1'b0;`
320			`imem_wait <= #1 1'b0;`
321			`idat_ir <= #1 idat_i [31:8];`
322			`end else if (ea_rom_sel && imem_wait) begin`
323			`imem_wait <= #1 1'b0;`
324			`end else if (ea_rom_sel && !imem_wait && istb_t) begin`
325			`istb_t <= #1 1'b0;`
326			end else if (mem_act==`OC8051_MAS_CODE) begin
327			`iadr_t <= #1 {des2, des1};`
328			`istb_t <= #1 1'b1;`
329			`imem_wait <= #1 1'b1;`
330			`end`
331			`end`
332
333			`/////////////////////////////`
334			`//`
335			`// ext_addr_sel`
336			`//`
337			`/////////////////////////////`
338
339			`assign dadr_o = dadr_ot;`
340
341			`always @(posedge clk or posedge rst)`
342			`begin`
343			`if (rst) begin`
344			`dwe_o <= #1 1'b0;`
345			`dmem_wait <= #1 1'b0;`
346			`dstb_o <= #1 1'b0;`
347			`ddat_o <= #1 8'h00;`
348			`dadr_ot <= #1 23'h0;`
349			`end else if (dack_i) begin`
350			`dwe_o <= #1 1'b0;`
351			`dstb_o <= #1 1'b0;`
352			`dmem_wait <= #1 1'b0;`
353			`end else begin`
354			`case (mem_act)`
355			`OC8051_MAS_DPTR_R: begin // read from external rom: acc=(dptr)
356			`dwe_o <= #1 1'b0;`
357			`dstb_o <= #1 1'b1;`
358			`ddat_o <= #1 8'h00;`
359			`dadr_ot <= #1 {7'h0, dptr};`
360			`dmem_wait <= #1 1'b1;`
361			`end`
362			`OC8051_MAS_DPTR_W: begin // write to external rom: (dptr)=acc
363			`dwe_o <= #1 1'b1;`
364			`dstb_o <= #1 1'b1;`
365			`ddat_o <= #1 acc;`
366			`dadr_ot <= #1 {7'h0, dptr};`
367			`dmem_wait <= #1 1'b1;`
368			`end`
369			`OC8051_MAS_RI_R: begin // read from external rom: acc=(Ri)
370			`dwe_o <= #1 1'b0;`
371			`dstb_o <= #1 1'b1;`
372			`ddat_o <= #1 8'h00;`
373			`dadr_ot <= #1 {15'h0, ri};`
374			`dmem_wait <= #1 1'b1;`
375			`end`
376			`OC8051_MAS_RI_W: begin // write to external rom: (Ri)=acc
377			`dwe_o <= #1 1'b1;`
378			`dstb_o <= #1 1'b1;`
379			`ddat_o <= #1 acc;`
380			`dadr_ot <= #1 {15'h0, ri};`
381			`dmem_wait <= #1 1'b1;`
382			`end`
383			`endcase`
384			`end`
385			`end`
386
387			`/////////////////////////////`
388			`//`
389			`// op_select`
390			`//`
391			`/////////////////////////////`
392
393
394			`assign op1 = ea_rom_sel ? op1_i: op1_xt;`
395			`assign op2 = ea_rom_sel ? op2_i: op2_xt;`
396			`assign op3 = ea_rom_sel ? op3_i: op3_xt;`
397
398
399			`always @(dack_ir or ddat_ir or op1_o or iram_out)`
400			`if (dack_ir)`
401			`op1_out = ddat_ir;`
402			`else`
403			`op1_out = op1_o;`
404
405			`assign op3_out = (rd) ? op3_o : op3_buff;`
406			`assign op2_out = (rd) ? op2_o : op2_buff;`
407
408			`always @(idat_i or iack_i or idat_ir or rd)`
409			`begin`
410			`if (iack_i) begin`
411			`op1_xt = idat_i[31:24];`
412			`op2_xt = idat_i[23:16];`
413			`op3_xt = idat_i[15:8];`
414			`end else if (!rd) begin`
415			`op1_xt = idat_ir[23:16];`
416			`op2_xt = idat_ir[15:8];`
417			`op3_xt = idat_ir[7:0];`
418			`end else begin`
419			`op1_xt = 8'h00;`
420			`op2_xt = 8'h00;`
421			`op3_xt = 8'h00;`
422			`end`
423			`end`
424
425
426			`//`
427			`// in case of interrupts`
428			`always @(op1 or op2 or op3 or int_ack_t or int_vec_buff or iack_i or ea_rom_sel)`
429			`begin`
430			`if (int_ack_t && (iack_i \|\| ea_rom_sel)) begin`
431			op1_o = `OC8051_LCALL;
432			`op2_o = 8'h00;`
433			`op3_o = int_vec_buff;`
434			`end else begin`
435			`op1_o = op1;`
436			`op2_o = op2;`
437			`op3_o = op3;`
438			`end`
439			`end`
440
441			`//`
442			`//in case of reti`
443			`always @(posedge clk or posedge rst)`
444			`if (rst) reti <= #1 1'b0;`
445			else if ((op1_o==`OC8051_RETI) & rd) reti <= #1 1'b1;
446			`else reti <= #1 1'b0;`
447
448			`//`
449			`// remember inputs`
450			`always @(posedge clk or posedge rst)`
451			`begin`
452			`if (rst) begin`
453			`op2_buff <= #1 8'h0;`
454			`op3_buff <= #1 8'h0;`
455			`end else if (rd) begin`
456			`op2_buff <= #1 op2_o;`
457			`op3_buff <= #1 op3_o;`
458			`end`
459			`end`
460
461			`//`
462			`// remember interrupt`
463			`// we don't want to interrupt instruction in the middle of execution`
464			`always @(posedge clk or posedge rst)`
465			`if (rst) begin`
466			`int_ack_t <= #1 1'b0;`
467			`int_vec_buff <= #1 8'h00;`
468			`end else if (intr) begin`
469			`int_ack_t <= #1 1'b1;`
470			`int_vec_buff <= #1 int_v;`
471			`end else if (rd && (ea_rom_sel \|\| iack_i)) int_ack_t <= #1 1'b0;`
472
473			`always @(posedge clk or posedge rst)`
474			`if (rst) int_ack_buff <= #1 1'b0;`
475			`else int_ack_buff <= #1 int_ack_t;`
476
477			`always @(posedge clk or posedge rst)`
478			`if (rst) int_ack <= #1 1'b0;`
479			`else begin`
480			`if ((int_ack_buff) & !(int_ack_t))`
481			`int_ack <= #1 1'b1;`
482			`else int_ack <= #1 1'b0;`
483			`end`
484
485
486			`/////////////////////////////`
487			`//`
488			`// pc`
489			`//`
490			`/////////////////////////////`
491
492			`always @(pc_buf or op1_out or pc_wait or int_buff or int_buff1 or alu[7:0] or ea_rom_sel or iack_i)`
493			`begin`
494			`if (int_buff \|\| int_buff1) begin`
495			`//`
496			`//in case of interrupt hold valut, to be written to stack`
497			`pc= pc_buf;`
498			`// end else if (pis_l) begin`
499			`// pc = {pc_buf[22:8], alu[7:0]};`
500			`end else if (pc_wait) begin`
501			`casex (op1_out)`
502	121	simont	`OC8051_ACALL : pc= pc_buf + 16'h2;
503			`OC8051_AJMP : pc= pc_buf + 16'h2;
504	81	simont
505			`//op_code [7:3]`
506	121	simont	`OC8051_CJNE_R : pc= pc_buf + 16'h3;
507			`OC8051_DJNZ_R : pc= pc_buf + 16'h2;
508			`OC8051_MOV_DR : pc= pc_buf + 16'h2;
509			`OC8051_MOV_CR : pc= pc_buf + 16'h2;
510			`OC8051_MOV_RD : pc= pc_buf + 16'h2;
511	81	simont
512			`//op_code [7:1]`
513	121	simont	`OC8051_CJNE_I : pc= pc_buf + 16'h3;
514			`OC8051_MOV_ID : pc= pc_buf + 16'h2;
515			`OC8051_MOV_DI : pc= pc_buf + 16'h2;
516			`OC8051_MOV_CI : pc= pc_buf + 16'h2;
517	81	simont
518			`//op_code [7:0]`
519	121	simont	`OC8051_ADD_D : pc= pc_buf + 16'h2;
520			`OC8051_ADD_C : pc= pc_buf + 16'h2;
521			`OC8051_ADDC_D : pc= pc_buf + 16'h2;
522			`OC8051_ADDC_C : pc= pc_buf + 16'h2;
523			`OC8051_ANL_D : pc= pc_buf + 16'h2;
524			`OC8051_ANL_C : pc= pc_buf + 16'h2;
525			`OC8051_ANL_DD : pc= pc_buf + 16'h2;
526			`OC8051_ANL_DC : pc= pc_buf + 16'h3;
527			`OC8051_ANL_B : pc= pc_buf + 16'h2;
528			`OC8051_ANL_NB : pc= pc_buf + 16'h2;
529			`OC8051_CJNE_D : pc= pc_buf + 16'h3;
530			`OC8051_CJNE_C : pc= pc_buf + 16'h3;
531			`OC8051_CLR_B : pc= pc_buf + 16'h2;
532			`OC8051_CPL_B : pc= pc_buf + 16'h2;
533			`OC8051_DEC_D : pc= pc_buf + 16'h2;
534			`OC8051_DJNZ_D : pc= pc_buf + 16'h3;
535			`OC8051_INC_D : pc= pc_buf + 16'h2;
536			`OC8051_JB : pc= pc_buf + 16'h3;
537			`OC8051_JBC : pc= pc_buf + 16'h3;
538			`OC8051_JC : pc= pc_buf + 16'h2;
539			`OC8051_JNB : pc= pc_buf + 16'h3;
540			`OC8051_JNC : pc= pc_buf + 16'h2;
541			`OC8051_JNZ : pc= pc_buf + 16'h2;
542			`OC8051_JZ : pc= pc_buf + 16'h2;
543			`OC8051_LCALL : pc= pc_buf + 16'h3;
544			`OC8051_LJMP : pc= pc_buf + 16'h3;
545			`OC8051_MOV_D : pc= pc_buf + 16'h2;
546			`OC8051_MOV_C : pc= pc_buf + 16'h2;
547			`OC8051_MOV_DA : pc= pc_buf + 16'h2;
548			`OC8051_MOV_DD : pc= pc_buf + 16'h3;
549			`OC8051_MOV_CD : pc= pc_buf + 16'h3;
550			`OC8051_MOV_BC : pc= pc_buf + 16'h2;
551			`OC8051_MOV_CB : pc= pc_buf + 16'h2;
552			`OC8051_MOV_DP : pc= pc_buf + 16'h3;
553			`OC8051_ORL_D : pc= pc_buf + 16'h2;
554			`OC8051_ORL_C : pc= pc_buf + 16'h2;
555			`OC8051_ORL_AD : pc= pc_buf + 16'h2;
556			`OC8051_ORL_CD : pc= pc_buf + 16'h3;
557			`OC8051_ORL_B : pc= pc_buf + 16'h2;
558			`OC8051_ORL_NB : pc= pc_buf + 16'h2;
559			`OC8051_POP : pc= pc_buf + 16'h2;
560			`OC8051_PUSH : pc= pc_buf + 16'h2;
561			`OC8051_SETB_B : pc= pc_buf + 16'h2;
562			`OC8051_SJMP : pc= pc_buf + 16'h2;
563			`OC8051_SUBB_D : pc= pc_buf + 16'h2;
564			`OC8051_SUBB_C : pc= pc_buf + 16'h2;
565			`OC8051_XCH_D : pc= pc_buf + 16'h2;
566			`OC8051_XRL_D : pc= pc_buf + 16'h2;
567			`OC8051_XRL_C : pc= pc_buf + 16'h2;
568			`OC8051_XRL_AD : pc= pc_buf + 16'h2;
569			`OC8051_XRL_CD : pc= pc_buf + 16'h3;
570			`default: pc= pc_buf + 16'h1;`
571	81	simont	`endcase`
572			`//`
573			`//in case of instructions that use more than one clock hold current pc`
574			`end else begin`
575			`pc= pc_buf;`
576			`end`
577			`end`
578
579
580			`//`
581			`//interrupt buffer`
582			`always @(posedge clk or posedge rst)`
583			`if (rst) begin`
584			`int_buff1 <= #1 1'b0;`
585			`end else begin`
586			`int_buff1 <= #1 int_buff;`
587			`end`
588
589			`always @(posedge clk or posedge rst)`
590			`if (rst) begin`
591			`int_buff <= #1 1'b0;`
592			`end else if (intr) begin`
593			`int_buff <= #1 1'b1;`
594			`end else if (pc_wait)`
595			`int_buff <= #1 1'b0;`
596
597
598			`always @(posedge clk or posedge rst)`
599			`begin`
600			`if (rst) begin`
601			pc_buf <= #1 `OC8051_RST_PC;
602			`end else begin`
603			`if (pc_wr) begin`
604			`//`
605			`//case of writing new value to pc (jupms)`
606			`case (pc_wr_sel)`
607			`OC8051_PIS_ALU: pc_buf <= #1 alu;
608			`OC8051_PIS_AL: pc_buf[7:0] <= #1 alu[7:0];
609			`OC8051_PIS_AH: pc_buf[15:8] <= #1 alu[7:0];
610			`OC8051_PIS_I11: pc_buf[10:0] <= #1 {op1_out[7:5], op2_out};
611			`OC8051_PIS_I16: pc_buf <= #1 {op2_out, op3_out};
612			`endcase`
613			`end else`
614			`//`
615			`//or just remember current`
616			`pc_buf <= #1 pc;`
617			`end`
618			`end`
619
620
621			`always @(posedge clk or posedge rst)`
622			`if (rst)`
623			`ddat_ir <= #1 8'h00;`
624			`else if (dack_i)`
625			`ddat_ir <= #1 ddat_i;`
626
627			`////////////////////////`
628			`always @(posedge clk or posedge rst)`
629			`if (rst) begin`
630			`rn_r <= #1 5'd0;`
631			`ri_r <= #1 8'h00;`
632			`imm_r <= #1 8'h00;`
633			`imm2_r <= #1 8'h00;`
634			`rd_addr_r <= #1 3'h0;`
635			`op1_r <= #1 8'h0;`
636			`dack_ir <= #1 1'b0;`
637			`sp_r <= #1 1'b0;`
638			`end else begin`
639			`rn_r <= #1 rn;`
640			`ri_r <= #1 ri;`
641			`imm_r <= #1 imm;`
642			`imm2_r <= #1 imm2;`
643			`rd_addr_r <= #1 rd_addr[7:5];`
644			`op1_r <= #1 op1_out;`
645			`dack_ir <= #1 dack_i;`
646			`sp_r <= #1 sp;`
647			`end`
648
649
650			`endmodule`