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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_ram_64x32_dual_bist.v] - Blame information for rev 185

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cache ram                                              ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   64x31 dual port ram                                        ////
////                                                              ////
////  To Do:                                                      ////
////   nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
//
// duble port ram
//
module oc8051_ram_64x32_dual_bist (
                     clk,
                     rst,
 
                     adr0,
                     dat0_o,
                     en0,
 
                     adr1,
                     dat1_i,
                     dat1_o,
                     en1,
                     wr1
`ifdef OC8051_BIST
         ,
         scanb_rst,
         scanb_clk,
         scanb_si,
         scanb_so,
         scanb_en
`endif
                     );
 
parameter ADR_WIDTH = 6;
 
input         clk,
              wr1,
              rst,
              en0,
              en1;
input  [7:0]  dat1_i;
input  [ADR_WIDTH-1:0]  adr0,
                        adr1;
output [7:0]  dat0_o,
              dat1_o;
 
reg    [7:0]  rd_data;
 
 
`ifdef OC8051_BIST
input   scanb_rst;
input   scanb_clk;
input   scanb_si;
output  scanb_so;
input   scanb_en;
`endif
 
 
`ifdef OC8051_RAM_XILINX
  xilinx_ram_dp xilinx_ram(
        // read port
        .CLKA(clk),
        .RSTA(rst),
        .ENA(en0),
        .ADDRA(adr0),
        .DIA(32'h00),
        .WEA(1'b0),
        .DOA(dat0_o),
 
        // write port
        .CLKB(clk),
        .RSTB(rst),
        .ENB(en1),
        .ADDRB(adr1),
        .DIB(dat1_i),
        .WEB(wr1),
        .DOB(dat1_o)
  );
 
  defparam
        xilinx_ram.dwidth = 32,
        xilinx_ram.awidth = ADR_WIDTH;
 
`else
 
  `ifdef OC8051_RAM_VIRTUALSILICON
 
  `else
 
    `ifdef OC8051_RAM_GENERIC
 
      generic_dpram #(ADR_WIDTH, 32) oc8051_ram1(
        .rclk  ( clk            ),
        .rrst  ( rst            ),
        .rce   ( en0            ),
        .oe    ( 1'b1           ),
        .raddr ( adr0           ),
        .do    ( dat0_o         ),
 
        .wclk  ( clk            ),
        .wrst  ( rst            ),
        .wce   ( en1            ),
        .we    ( wr1            ),
        .waddr ( adr1           ),
        .di    ( dat1_i         )
      );
 
    `else
 
      reg [31:0] dat1_o,
                 dat0_o;
      //
      // buffer
      reg    [31:0]  buff [0:(1<<ADR_WIDTH) -1];
 
      always @(posedge clk or posedge rst)
      begin
        if (rst)
          dat1_o     <= #1 32'h0;
        else if (wr1) begin
          buff[adr1] <= #1 dat1_i;
          dat1_o    <= #1 dat1_i;
        end else
          dat1_o <= #1 buff[adr1];
      end
 
      always @(posedge clk or posedge rst)
      begin
        if (rst)
          dat0_o <= #1 32'h0;
        else if ((adr0==adr1) & wr1)
          dat0_o <= #1 dat1_i;
        else
          dat0_o <= #1 buff[adr0];
      end
 
    `endif  //OC8051_RAM_GENERIC
  `endif    //OC8051_RAM_VIRTUALSILICON  
`endif      //OC8051_RAM_XILINX
 
endmodule

Line No.	Rev	Author	Line
1	175	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cache ram ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 64x31 dual port ram ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`//`
48			`//`
49
50			`// synopsys translate_off`
51			`include "oc8051_timescale.v"
52			`// synopsys translate_on`
53
54			`include "oc8051_defines.v"
55
56			`//`
57			`// duble port ram`
58			`//`
59			`module oc8051_ram_64x32_dual_bist (`
60			`clk,`
61			`rst,`
62
63			`adr0,`
64			`dat0_o,`
65			`en0,`
66
67			`adr1,`
68			`dat1_i,`
69			`dat1_o,`
70			`en1,`
71			`wr1`
72			`ifdef OC8051_BIST
73			`,`
74			`scanb_rst,`
75			`scanb_clk,`
76			`scanb_si,`
77			`scanb_so,`
78			`scanb_en`
79			`endif
80			`);`
81
82			`parameter ADR_WIDTH = 6;`
83
84			`input clk,`
85			`wr1,`
86			`rst,`
87			`en0,`
88			`en1;`
89			`input [7:0] dat1_i;`
90			`input [ADR_WIDTH-1:0] adr0,`
91			`adr1;`
92			`output [7:0] dat0_o,`
93			`dat1_o;`
94
95			`reg [7:0] rd_data;`
96
97
98			`ifdef OC8051_BIST
99			`input scanb_rst;`
100			`input scanb_clk;`
101			`input scanb_si;`
102			`output scanb_so;`
103			`input scanb_en;`
104			`endif
105
106
107			`ifdef OC8051_RAM_XILINX
108			`xilinx_ram_dp xilinx_ram(`
109			`// read port`
110			`.CLKA(clk),`
111			`.RSTA(rst),`
112			`.ENA(en0),`
113			`.ADDRA(adr0),`
114			`.DIA(32'h00),`
115			`.WEA(1'b0),`
116			`.DOA(dat0_o),`
117
118			`// write port`
119			`.CLKB(clk),`
120			`.RSTB(rst),`
121			`.ENB(en1),`
122			`.ADDRB(adr1),`
123			`.DIB(dat1_i),`
124			`.WEB(wr1),`
125			`.DOB(dat1_o)`
126			`);`
127
128			`defparam`
129			`xilinx_ram.dwidth = 32,`
130			`xilinx_ram.awidth = ADR_WIDTH;`
131
132			`else
133
134			`ifdef OC8051_RAM_VIRTUALSILICON
135
136			`else
137
138			`ifdef OC8051_RAM_GENERIC
139
140			`generic_dpram #(ADR_WIDTH, 32) oc8051_ram1(`
141			`.rclk ( clk ),`
142			`.rrst ( rst ),`
143			`.rce ( en0 ),`
144			`.oe ( 1'b1 ),`
145			`.raddr ( adr0 ),`
146			`.do ( dat0_o ),`
147
148			`.wclk ( clk ),`
149			`.wrst ( rst ),`
150			`.wce ( en1 ),`
151			`.we ( wr1 ),`
152			`.waddr ( adr1 ),`
153			`.di ( dat1_i )`
154			`);`
155
156			`else
157
158			`reg [31:0] dat1_o,`
159			`dat0_o;`
160			`//`
161			`// buffer`
162			`reg [31:0] buff [0:(1<<ADR_WIDTH) -1];`
163
164			`always @(posedge clk or posedge rst)`
165			`begin`
166			`if (rst)`
167			`dat1_o <= #1 32'h0;`
168			`else if (wr1) begin`
169			`buff[adr1] <= #1 dat1_i;`
170			`dat1_o <= #1 dat1_i;`
171			`end else`
172			`dat1_o <= #1 buff[adr1];`
173			`end`
174
175			`always @(posedge clk or posedge rst)`
176			`begin`
177			`if (rst)`
178			`dat0_o <= #1 32'h0;`
179			`else if ((adr0==adr1) & wr1)`
180			`dat0_o <= #1 dat1_i;`
181			`else`
182			`dat0_o <= #1 buff[adr0];`
183			`end`
184
185			`endif //OC8051_RAM_GENERIC
186			`endif //OC8051_RAM_VIRTUALSILICON
187			`endif //OC8051_RAM_XILINX
188
189			`endmodule`

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_ram_64x32_dual_bist.v] - Blame information for rev 185