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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores sfr top level module                             ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   special function registers for oc8051                      ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7  2003/04/07 14:58:02  simont
// change sfr's interface.
//
// Revision 1.6  2003/04/07 13:29:16  simont
// change uart to meet timing.
//
// Revision 1.5  2003/04/04 10:35:07  simont
// signal prsc_ow added.
//
// Revision 1.4  2003/03/28 17:45:57  simont
// change module name.
//
// Revision 1.3  2003/01/21 13:51:30  simont
// add include oc8051_defines.v
//
// Revision 1.2  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.1  2002/11/05 17:22:27  simont
// initial import
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
module oc8051_sfr (rst, clk,
       adr0, adr1, dat0,
       dat1, dat2,
       we, bit_in, wr_bit,
       bit_out,
       wr_sfr, acc, ram_wr_sel, ram_rd_sel, sp, sp_w, bank_sel, desAc, desOv, psw_set, srcAc, cy, rmw,
       p0_out, p1_out, p2_out, p3_out, p0_in, p1_in, p2_in, p3_in, rxd, txd, int_ack, intr, int0,
       int1, reti, int_src, t0, t1, dptr_hi, dptr_lo, t2, t2ex,
       wait_data);
//
// rst           (in)  reset - pin
// clk           (in)  clock - pin
// adr0, adr1    (in)  address input
// dat0          (out) data output
// dat1          (in)  data input
// dat2
// we            (in)  write enable
// bit_in
// bit_out
// wr_bit
// ram_rd_sel
// ram_wr_sel
// wr_sfr
//////////
//
//  acc:
// acc
//////////
//
//  sp:
// sp
//////////
//
//  psw:
// bank_sel
// desAc
// desOv
// psw_set
// srcAc
// cy
//////////
//
//  ports:
// rmw
// px_out
// px_in
//////////
//
//  serial interface:
// rxd
// txd
//////////
//
//  interrupt interface:
// int_ack
// intr
// int0, int1
// reti
// int_src
//////////
//
//  timers/counters:
// t0
// t1
// t2
// t2ex
//
//////////
//
//  dptr:
// dptr_hi
// dptr_lo
//
//////////
//
 
 
 
 
input rst, clk, we, bit_in, desAc, desOv, rmw, rxd, t2, t2ex;
input int_ack, int0, int1, reti, wr_bit, t0, t1;
input [1:0] psw_set;
input [2:0] ram_rd_sel, ram_wr_sel, wr_sfr;
input [7:0] adr0, adr1, dat1, dat2, p0_in, p1_in, p2_in, p3_in;
 
output bit_out, txd, intr, srcAc, cy, wait_data;
output [1:0] bank_sel;
output [7:0] dat0, p0_out, p1_out, p2_out, p3_out, int_src, dptr_hi, dptr_lo, acc;
output [7:0] sp, sp_w;
 
 
reg bit_out, wait_data;
reg [7:0] dat0, adr0_r;
 
reg wr_bit_r;
reg [2:0] ram_wr_sel_r;
 
//sfr's
wire acc_bit, b_bit, psw_bit, port_bit, uart_bit, int_bit, tc2_bit;
 
wire p, int_uart, tf0, tf1, tr0, tr1;
wire rclk, tclk, brate2, tc2_int;
 
wire [7:0] b_reg, psw,
//ports
          p0_data, p1_data, p2_data, p3_data,
//interrupt control
          ie, tcon, ip,
// t/c 2
          t2con, tl2, th2, rcap2l, rcap2h,
// t/c 0,1
          tmod, tl0, th0, tl1, th1,
// serial interface
          scon, pcon, sbuf,
// stack
          sp_out;
 
wire pres_ow;
 
 
assign cy = psw[7];
assign srcAc = psw [6];
 
 
 
//
// accumulator
// ACC
oc8051_acc oc8051_acc1(.clk(clk), .rst(rst), .bit_in(bit_in), .data_in(dat1),
           .data2_in(dat2), .wr(we), .wr_bit(wr_bit_r), .wr_sfr(wr_sfr),
           .wr_addr(adr1), .data_out(acc), .p(p));
 
 
//
// b register
// B
oc8051_b_register oc8051_b_register (.clk(clk), .rst(rst), .bit_in(bit_in),
           .data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .wr_addr(adr1),
           .data_out(b_reg), .wr_sfr(wr_sfr));
 
//
//stack pointer
// SP
oc8051_sp oc8051_sp1(.clk(clk), .rst(rst), .ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel),
                 .wr_addr(adr1), .wr(we), .wr_bit(wr_bit_r), .data_in(dat1),
                 .data_out(sp_out), .sp_out(sp), .sp_w(sp_w));
 
//
//data pointer
// DPTR, DPH, DPL
oc8051_dptr oc8051_dptr1(.clk(clk), .rst(rst), .addr(adr1), .data_in(dat1),
                .data2_in(dat2), .wr(we), .wr_bit(wr_bit_r),
                .data_hi(dptr_hi), .data_lo(dptr_lo), .wr_sfr(wr_sfr));
 
 
//
//program status word
// PSW
oc8051_psw oc8051_psw1 (.clk(clk), .rst(rst), .wr_addr(adr1), .data_in(dat1),
                .wr(we), .wr_bit(wr_bit_r), .data_out(psw), .p(p), .cy_in(bit_in),
                .ac_in(desAc), .ov_in(desOv), .set(psw_set), .bank_sel(bank_sel));
 
//
// ports
// P0, P1, P2, P3
oc8051_ports oc8051_ports1(.clk(clk), .rst(rst), .bit_in(bit_in), .data_in(dat1), .wr(we),
                 .wr_bit(wr_bit_r), .wr_addr(adr1), .rmw(rmw),
                 .p0_out(p0_out), .p1_out(p1_out), .p2_out(p2_out), .p3_out(p3_out),
                 .p0_in(p0_in), .p1_in(p1_in), .p2_in(p2_in), .p3_in(p3_in),
                 .p0_data(p0_data), .p1_data(p1_data), .p2_data(p2_data), .p3_data(p3_data));
 
//
// serial interface
// SCON, SBUF
oc8051_uart oc8051_uatr1 (.clk(clk), .rst(rst), .bit_in(bit_in),
                .data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .wr_addr(adr1),
                .rxd(rxd), .txd(txd), .intr(uart_int),
                .rclk(rclk), .tclk(tclk), .brate2(brate2),
                .t1_ow(tf1), .pres_ow(pres_ow),
                .scon(scon), .pcon(pcon), .sbuf(sbuf));
 
//
// interrupt control
// IP, IE, TCON
oc8051_int oc8051_int1 (.clk(clk), .rst(rst), .wr_addr(adr1), .bit_in(bit_in),
                .ack(int_ack), .data_in(dat1),
                .wr(we), .wr_bit(wr_bit_r),
                .tf0(tf0), .tf1(tf1), .t2_int(tc2_int), .tr0(tr0), .tr1(tr1),
                .ie0(int0), .ie1(int1),
                .uart_int(uart_int),
                .reti(reti), .intr(intr), .int_vec(int_src),
                .ie(ie), .tcon(tcon), .ip(ip));
 
 
//
// timer/counter control
// TH0, TH1, TL0, TH1, TMOD
oc8051_tc oc8051_tc1(.clk(clk), .rst(rst), .wr_addr(adr1),
                .data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .ie0(int0), .ie1(int1), .tr0(tr0),
                .tr1(tr1), .t0(t0), .t1(t1), .tf0(tf0), .tf1(tf1), .pres_ow(pres_ow),
                .tmod(tmod), .tl0(tl0), .th0(th0), .tl1(tl1), .th1(th1));
 
//
// timer/counter 2
// TH2, TL2, RCAPL2L, RCAPL2H, T2CON
oc8051_tc2 oc8051_tc21(.clk(clk), .rst(rst), .wr_addr(adr1), .data_in(dat1), .wr(we),
           .wr_bit(wr_bit_r), .bit_in(bit_in), .t2(t2), .t2ex(t2ex),
           .rclk(rclk), .tclk(tclk), .brate2(brate2), .tc2_int(tc2_int), .pres_ow(pres_ow),
           .t2con(t2con), .tl2(tl2), .th2(th2), .rcap2l(rcap2l), .rcap2h(rcap2h));
 
 
 
always @(posedge clk or posedge rst)
  if (rst) begin
    adr0_r <= #1 8'h00;
    ram_wr_sel_r <= #1 3'b000;
    wr_bit_r <= #1 1'b0;
//    wait_data <= #1 1'b0;
  end else begin
    adr0_r <= #1 adr0;
    ram_wr_sel_r <= #1 ram_wr_sel;
    wr_bit_r <= #1 wr_bit;
  end
 
/*
//
//set output in case of address (byte)
always @(adr0_r or psw or acc or dptr_hi or dptr_lo or b_reg or
//ports
          p0_data or p1_data or p2_data or p3_data or
//interrupt control
          ie or tcon or ip or
// t/c 2
          t2con or tl2 or th2 or rcap2l or rcap2h or
// t/c 0,1
          tmod or tl0 or th0 or tl1 or th1 or
// serial interface
          scon or pcon or sbuf or
// stack
          sp_out)
begin
    case (adr0_r)
      `OC8051_SFR_ACC:          dat0 = acc;
      `OC8051_SFR_PSW:          dat0 = psw;
      `OC8051_SFR_P0:           dat0 = p0_data;
      `OC8051_SFR_P1:           dat0 = p1_data;
      `OC8051_SFR_P2:           dat0 = p2_data;
      `OC8051_SFR_P3:           dat0 = p3_data;
      `OC8051_SFR_SP:           dat0 = sp_out;
      `OC8051_SFR_B:            dat0 = b_reg;
      `OC8051_SFR_DPTR_HI:      dat0 = dptr_hi;
      `OC8051_SFR_DPTR_LO:      dat0 = dptr_lo;
      `OC8051_SFR_SCON:         dat0 = scon;
      `OC8051_SFR_SBUF:         dat0 = sbuf;
      `OC8051_SFR_PCON:         dat0 = pcon;
      `OC8051_SFR_TH0:          dat0 = th0;
      `OC8051_SFR_TH1:          dat0 = th1;
      `OC8051_SFR_TL0:          dat0 = tl0;
      `OC8051_SFR_TL1:          dat0 = tl1;
      `OC8051_SFR_TMOD:         dat0 = tmod;
      `OC8051_SFR_IP:           dat0 = ip;
      `OC8051_SFR_IE:           dat0 = ie;
      `OC8051_SFR_TCON:         dat0 = tcon;
      `OC8051_SFR_RCAP2H:       dat0 = rcap2h;
      `OC8051_SFR_RCAP2L:       dat0 = rcap2l;
      `OC8051_SFR_TH2:          dat0 = th2;
      `OC8051_SFR_TL2:          dat0 = tl2;
      `OC8051_SFR_T2CON:        dat0 = t2con;
      default:                  dat0 = 8'h00;
    endcase
end
 
 
//
//set output in case of address (bit)
always @(adr0_r or psw or acc or b_reg or
//ports
          p0_data or p1_data or p2_data or p3_data or
//interrupt control
          ie or tcon or ip or
// t/c 2
          t2con or
// serial interface
          scon)
begin
    case (adr0_r[7:3])
      `OC8051_SFR_B_ACC:   bit_out = acc[adr0_r[2:0]];
      `OC8051_SFR_B_PSW:   bit_out = psw[adr0_r[2:0]];
      `OC8051_SFR_B_P0:    bit_out = p0_data[adr0_r[2:0]];
      `OC8051_SFR_B_P1:    bit_out = p1_data[adr0_r[2:0]];
      `OC8051_SFR_B_P2:    bit_out = p2_data[adr0_r[2:0]];
      `OC8051_SFR_B_P3:    bit_out = p3_data[adr0_r[2:0]];
      `OC8051_SFR_B_B:     bit_out = b_reg[adr0_r[2:0]];
      `OC8051_SFR_B_IP:    bit_out = ip[adr0_r[2:0]];
      `OC8051_SFR_B_IE:    bit_out = ie[adr0_r[2:0]];
      `OC8051_SFR_B_TCON:  bit_out = tcon[adr0_r[2:0]];
      `OC8051_SFR_B_SCON:  bit_out = scon[adr0_r[2:0]];
      `OC8051_SFR_B_T2CON: bit_out = t2con[adr0_r[2:0]];
      default:             bit_out = 1'b0;
    endcase
end
*/
 
 
 
//
//set output in case of address (byte)
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    dat0 <= #1 8'h00;
    wait_data <= #1 1'b0;
/*  end else if (((adr0==`OC8051_SFR_PSW) & (((adr1==`OC8051_SFR_ACC) & we & !wr_bit_r)) |
                (({adr1[7:3], 3'b000}==adr0) & we & wr_bit_r)) & !wait_data) begin
//    dat0 <= #1 {dat1[7:1], p};
    wait_data <= #1 1'b1;
  end else if ((adr0==`OC8051_SFR_PSW) & (adr1==adr0) & we & !wr_bit_r & !wait_data) begin
//    dat0 <= #1 {dat1[7:1], p};
    wait_data <= #1 1'b1;*/
  end else if ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) begin                          //write and read same address
    dat0 <= #1 dat1;
    wait_data <= #1 1'b0;
  end else if (
      (((wr_sfr==`OC8051_WRS_ACC1) & (adr0==`OC8051_SFR_ACC)) |                 //write to acc
      ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) |      //write to dpl
      ((wr_sfr==`OC8051_WRS_BA)   & (adr0==`OC8051_SFR_B)) |            //write to b
      (adr1[7] & (adr1==adr0) & we & !wr_bit_r)) & !wait_data) begin                            //write and read same address
//    dat0 <= #1 dat1;
    wait_data <= #1 1'b1;
 
  end else if (
      (((wr_sfr==`OC8051_WRS_ACC2) & (adr0==`OC8051_SFR_ACC)) |         //write to acc
      ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_HI)) |      //write to dph
      ((wr_sfr==`OC8051_WRS_BA)   & (adr0==`OC8051_SFR_ACC))) & !wait_data) begin       //write to b
//    dat0 <= #1 dat2;
    wait_data <= #1 1'b1;
 
//  else if (({adr1[7:3], 3'b000}==adr0_r) & we & wr_bit_r)
//    dat0 <= #1 dat1;
  end else begin
    case (adr0)
      `OC8051_SFR_ACC:          dat0 <= #1 acc;
      `OC8051_SFR_PSW:          dat0 <= #1 psw;
      `OC8051_SFR_P0:           dat0 <= #1 p0_data;
      `OC8051_SFR_P1:           dat0 <= #1 p1_data;
      `OC8051_SFR_P2:           dat0 <= #1 p2_data;
      `OC8051_SFR_P3:           dat0 <= #1 p3_data;
//      `OC8051_SFR_SP:                 dat0 <= #1 sp_out;
      `OC8051_SFR_SP:           dat0 <= #1 sp;
      `OC8051_SFR_B:            dat0 <= #1 b_reg;
      `OC8051_SFR_DPTR_HI:      dat0 <= #1 dptr_hi;
      `OC8051_SFR_DPTR_LO:      dat0 <= #1 dptr_lo;
      `OC8051_SFR_SCON:         dat0 <= #1 scon;
      `OC8051_SFR_SBUF:         dat0 <= #1 sbuf;
      `OC8051_SFR_PCON:         dat0 <= #1 pcon;
      `OC8051_SFR_TH0:          dat0 <= #1 th0;
      `OC8051_SFR_TH1:          dat0 <= #1 th1;
      `OC8051_SFR_TL0:          dat0 <= #1 tl0;
      `OC8051_SFR_TL1:          dat0 <= #1 tl1;
      `OC8051_SFR_TMOD:         dat0 <= #1 tmod;
      `OC8051_SFR_IP:           dat0 <= #1 ip;
      `OC8051_SFR_IE:           dat0 <= #1 ie;
      `OC8051_SFR_TCON:         dat0 <= #1 tcon;
      `OC8051_SFR_RCAP2H:       dat0 <= #1 rcap2h;
      `OC8051_SFR_RCAP2L:       dat0 <= #1 rcap2l;
      `OC8051_SFR_TH2:          dat0 <= #1 th2;
      `OC8051_SFR_TL2:          dat0 <= #1 tl2;
      `OC8051_SFR_T2CON:        dat0 <= #1 t2con;
      default:                  dat0 <= #1 8'h00;
    endcase
    wait_data <= #1 1'b0;
  end
end
 
 
//
//set output in case of address (bit)
always @(posedge clk or posedge rst)
begin
  if (rst)
    bit_out <= #1 1'h0;
  else if (
          ((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) &  we & !wr_bit_r) |
          ((wr_sfr==`OC8051_WRS_ACC1) & (adr0[7:3]==`OC8051_SFR_B_ACC)) |       //write to acc
          ((wr_sfr==`OC8051_WRS_BA)   & (adr0[7:3]==`OC8051_SFR_B_B)))          //write to b
 
    bit_out <= #1 dat1[adr0[2:0]];
  else if ((adr1==adr0) & we & wr_bit_r)
    bit_out <= #1 bit_in;
  else
    case (adr0[7:3])
      `OC8051_SFR_B_ACC:   bit_out <= #1 acc[adr0[2:0]];
      `OC8051_SFR_B_PSW:   bit_out <= #1 psw[adr0[2:0]];
      `OC8051_SFR_B_P0:    bit_out <= #1 p0_data[adr0[2:0]];
      `OC8051_SFR_B_P1:    bit_out <= #1 p1_data[adr0[2:0]];
      `OC8051_SFR_B_P2:    bit_out <= #1 p2_data[adr0[2:0]];
      `OC8051_SFR_B_P3:    bit_out <= #1 p3_data[adr0[2:0]];
      `OC8051_SFR_B_B:     bit_out <= #1 b_reg[adr0[2:0]];
      `OC8051_SFR_B_IP:    bit_out <= #1 ip[adr0[2:0]];
      `OC8051_SFR_B_IE:    bit_out <= #1 ie[adr0[2:0]];
      `OC8051_SFR_B_TCON:  bit_out <= #1 tcon[adr0[2:0]];
      `OC8051_SFR_B_SCON:  bit_out <= #1 scon[adr0[2:0]];
      `OC8051_SFR_B_T2CON: bit_out <= #1 t2con[adr0[2:0]];
      default:             bit_out <= #1 1'b0;
    endcase
end
 
 
endmodule

Line No.	Rev	Author	Line
1	75	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores sfr top level module ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// special function registers for oc8051 ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	117	simont	`// Revision 1.7 2003/04/07 14:58:02 simont`
48			`// change sfr's interface.`
49			`//`
50	116	simont	`// Revision 1.6 2003/04/07 13:29:16 simont`
51			`// change uart to meet timing.`
52			`//`
53	115	simont	`// Revision 1.5 2003/04/04 10:35:07 simont`
54			`// signal prsc_ow added.`
55			`//`
56	113	simont	`// Revision 1.4 2003/03/28 17:45:57 simont`
57			`// change module name.`
58			`//`
59	90	simont	`// Revision 1.3 2003/01/21 13:51:30 simont`
60			`// add include oc8051_defines.v`
61			`//`
62	87	simont	`// Revision 1.2 2003/01/13 14:14:41 simont`
63			`// replace some modules`
64			`//`
65	82	simont	`// Revision 1.1 2002/11/05 17:22:27 simont`
66			`// initial import`
67	75	simont	`//`
68	82	simont	`//`
69	75	simont
70			`// synopsys translate_off`
71			`include "oc8051_timescale.v"
72			`// synopsys translate_on`
73
74	87	simont	`include "oc8051_defines.v"
75	75	simont
76	87	simont
77	117	simont	`module oc8051_sfr (rst, clk,`
78			`adr0, adr1, dat0,`
79			`dat1, dat2,`
80			`we, bit_in, wr_bit,`
81			`bit_out,`
82	82	simont	`wr_sfr, acc, ram_wr_sel, ram_rd_sel, sp, sp_w, bank_sel, desAc, desOv, psw_set, srcAc, cy, rmw,`
83			`p0_out, p1_out, p2_out, p3_out, p0_in, p1_in, p2_in, p3_in, rxd, txd, int_ack, intr, int0,`
84	117	simont	`int1, reti, int_src, t0, t1, dptr_hi, dptr_lo, t2, t2ex,`
85			`wait_data);`
86	75	simont	`//`
87			`// rst (in) reset - pin`
88			`// clk (in) clock - pin`
89			`// adr0, adr1 (in) address input`
90			`// dat0 (out) data output`
91			`// dat1 (in) data input`
92			`// dat2`
93			`// we (in) write enable`
94			`// bit_in`
95			`// bit_out`
96			`// wr_bit`
97			`// ram_rd_sel`
98			`// ram_wr_sel`
99	82	simont	`// wr_sfr`
100	75	simont	`//////////`
101			`//`
102			`// acc:`
103			`// acc`
104			`//////////`
105			`//`
106			`// sp:`
107			`// sp`
108			`//////////`
109			`//`
110			`// psw:`
111			`// bank_sel`
112			`// desAc`
113			`// desOv`
114			`// psw_set`
115			`// srcAc`
116			`// cy`
117			`//////////`
118			`//`
119			`// ports:`
120			`// rmw`
121			`// px_out`
122			`// px_in`
123			`//////////`
124			`//`
125			`// serial interface:`
126			`// rxd`
127			`// txd`
128			`//////////`
129			`//`
130			`// interrupt interface:`
131			`// int_ack`
132			`// intr`
133			`// int0, int1`
134			`// reti`
135			`// int_src`
136			`//////////`
137			`//`
138			`// timers/counters:`
139			`// t0`
140			`// t1`
141	82	simont	`// t2`
142			`// t2ex`
143	75	simont	`//`
144			`//////////`
145			`//`
146			`// dptr:`
147			`// dptr_hi`
148			`// dptr_lo`
149	82	simont	`//`
150			`//////////`
151			`//`
152	75	simont
153
154
155
156	82	simont	`input rst, clk, we, bit_in, desAc, desOv, rmw, rxd, t2, t2ex;`
157			`input int_ack, int0, int1, reti, wr_bit, t0, t1;`
158			`input [1:0] psw_set;`
159			`input [2:0] ram_rd_sel, ram_wr_sel, wr_sfr;`
160			`input [7:0] adr0, adr1, dat1, dat2, p0_in, p1_in, p2_in, p3_in;`
161	75	simont
162	117	simont	`output bit_out, txd, intr, srcAc, cy, wait_data;`
163	82	simont	`output [1:0] bank_sel;`
164			`output [7:0] dat0, p0_out, p1_out, p2_out, p3_out, int_src, dptr_hi, dptr_lo, acc;`
165			`output [7:0] sp, sp_w;`
166	75	simont
167	82	simont
168	117	simont	`reg bit_out, wait_data;`
169	82	simont	`reg [7:0] dat0, adr0_r;`
170	75	simont
171	82	simont	`reg wr_bit_r;`
172	75	simont	`reg [2:0] ram_wr_sel_r;`
173	116	simont
174			`//sfr's`
175			`wire acc_bit, b_bit, psw_bit, port_bit, uart_bit, int_bit, tc2_bit;`
176
177	75	simont	`wire p, int_uart, tf0, tf1, tr0, tr1;`
178	116	simont	`wire rclk, tclk, brate2, tc2_int;`
179	75	simont
180	116	simont	`wire [7:0] b_reg, psw,`
181			`//ports`
182			`p0_data, p1_data, p2_data, p3_data,`
183			`//interrupt control`
184			`ie, tcon, ip,`
185			`// t/c 2`
186			`t2con, tl2, th2, rcap2l, rcap2h,`
187			`// t/c 0,1`
188			`tmod, tl0, th0, tl1, th1,`
189			`// serial interface`
190			`scon, pcon, sbuf,`
191			`// stack`
192			`sp_out;`
193
194	113	simont	`wire pres_ow;`
195	82	simont
196	117	simont
197	75	simont	`assign cy = psw[7];`
198			`assign srcAc = psw [6];`
199
200	82	simont
201
202	75	simont	`//`
203			`// accumulator`
204			`// ACC`
205			`oc8051_acc oc8051_acc1(.clk(clk), .rst(rst), .bit_in(bit_in), .data_in(dat1),`
206	82	simont	`.data2_in(dat2), .wr(we), .wr_bit(wr_bit_r), .wr_sfr(wr_sfr),`
207	116	simont	`.wr_addr(adr1), .data_out(acc), .p(p));`
208	75	simont
209
210			`//`
211			`// b register`
212			`// B`
213	116	simont	`oc8051_b_register oc8051_b_register (.clk(clk), .rst(rst), .bit_in(bit_in),`
214			`.data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .wr_addr(adr1),`
215	82	simont	`.data_out(b_reg), .wr_sfr(wr_sfr));`
216	75	simont
217			`//`
218			`//stack pointer`
219			`// SP`
220			`oc8051_sp oc8051_sp1(.clk(clk), .rst(rst), .ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel),`
221	82	simont	`.wr_addr(adr1), .wr(we), .wr_bit(wr_bit_r), .data_in(dat1),`
222			`.data_out(sp_out), .sp_out(sp), .sp_w(sp_w));`
223	75	simont
224			`//`
225			`//data pointer`
226			`// DPTR, DPH, DPL`
227			`oc8051_dptr oc8051_dptr1(.clk(clk), .rst(rst), .addr(adr1), .data_in(dat1),`
228	82	simont	`.data2_in(dat2), .wr(we), .wr_bit(wr_bit_r),`
229			`.data_hi(dptr_hi), .data_lo(dptr_lo), .wr_sfr(wr_sfr));`
230	75	simont
231	82	simont
232	75	simont	`//`
233			`//program status word`
234			`// PSW`
235	116	simont	`oc8051_psw oc8051_psw1 (.clk(clk), .rst(rst), .wr_addr(adr1), .data_in(dat1),`
236			`.wr(we), .wr_bit(wr_bit_r), .data_out(psw), .p(p), .cy_in(bit_in),`
237	75	simont	`.ac_in(desAc), .ov_in(desOv), .set(psw_set), .bank_sel(bank_sel));`
238
239			`//`
240			`// ports`
241			`// P0, P1, P2, P3`
242			`oc8051_ports oc8051_ports1(.clk(clk), .rst(rst), .bit_in(bit_in), .data_in(dat1), .wr(we),`
243	116	simont	`.wr_bit(wr_bit_r), .wr_addr(adr1), .rmw(rmw),`
244			`.p0_out(p0_out), .p1_out(p1_out), .p2_out(p2_out), .p3_out(p3_out),`
245			`.p0_in(p0_in), .p1_in(p1_in), .p2_in(p2_in), .p3_in(p3_in),`
246			`.p0_data(p0_data), .p1_data(p1_data), .p2_data(p2_data), .p3_data(p3_data));`
247	75	simont
248			`//`
249			`// serial interface`
250			`// SCON, SBUF`
251	116	simont	`oc8051_uart oc8051_uatr1 (.clk(clk), .rst(rst), .bit_in(bit_in),`
252	82	simont	`.data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .wr_addr(adr1),`
253	116	simont	`.rxd(rxd), .txd(txd), .intr(uart_int),`
254			`.rclk(rclk), .tclk(tclk), .brate2(brate2),`
255			`.t1_ow(tf1), .pres_ow(pres_ow),`
256			`.scon(scon), .pcon(pcon), .sbuf(sbuf));`
257	75	simont
258			`//`
259			`// interrupt control`
260			`// IP, IE, TCON`
261	116	simont	`oc8051_int oc8051_int1 (.clk(clk), .rst(rst), .wr_addr(adr1), .bit_in(bit_in),`
262			`.ack(int_ack), .data_in(dat1),`
263	82	simont	`.wr(we), .wr_bit(wr_bit_r),`
264			`.tf0(tf0), .tf1(tf1), .t2_int(tc2_int), .tr0(tr0), .tr1(tr1),`
265			`.ie0(int0), .ie1(int1),`
266			`.uart_int(uart_int),`
267	116	simont	`.reti(reti), .intr(intr), .int_vec(int_src),`
268			`.ie(ie), .tcon(tcon), .ip(ip));`
269	75	simont
270	82	simont
271	75	simont	`//`
272			`// timer/counter control`
273			`// TH0, TH1, TL0, TH1, TMOD`
274	116	simont	`oc8051_tc oc8051_tc1(.clk(clk), .rst(rst), .wr_addr(adr1),`
275	82	simont	`.data_in(dat1), .wr(we), .wr_bit(wr_bit_r), .ie0(int0), .ie1(int1), .tr0(tr0),`
276	116	simont	`.tr1(tr1), .t0(t0), .t1(t1), .tf0(tf0), .tf1(tf1), .pres_ow(pres_ow),`
277			`.tmod(tmod), .tl0(tl0), .th0(th0), .tl1(tl1), .th1(th1));`
278	75	simont
279	82	simont	`//`
280			`// timer/counter 2`
281	116	simont	`// TH2, TL2, RCAPL2L, RCAPL2H, T2CON`
282			`oc8051_tc2 oc8051_tc21(.clk(clk), .rst(rst), .wr_addr(adr1), .data_in(dat1), .wr(we),`
283			`.wr_bit(wr_bit_r), .bit_in(bit_in), .t2(t2), .t2ex(t2ex),`
284			`.rclk(rclk), .tclk(tclk), .brate2(brate2), .tc2_int(tc2_int), .pres_ow(pres_ow),`
285			`.t2con(t2con), .tl2(tl2), .th2(th2), .rcap2l(rcap2l), .rcap2h(rcap2h));`
286	75	simont
287	82	simont
288
289	75	simont	`always @(posedge clk or posedge rst)`
290			`if (rst) begin`
291			`adr0_r <= #1 8'h00;`
292			`ram_wr_sel_r <= #1 3'b000;`
293	82	simont	`wr_bit_r <= #1 1'b0;`
294	117	simont	`// wait_data <= #1 1'b0;`
295	75	simont	`end else begin`
296			`adr0_r <= #1 adr0;`
297			`ram_wr_sel_r <= #1 ram_wr_sel;`
298	82	simont	`wr_bit_r <= #1 wr_bit;`
299	75	simont	`end`
300
301	117	simont	`/*`
302	75	simont	`//`
303			`//set output in case of address (byte)`
304	116	simont	`always @(adr0_r or psw or acc or dptr_hi or dptr_lo or b_reg or`
305			`//ports`
306			`p0_data or p1_data or p2_data or p3_data or`
307			`//interrupt control`
308			`ie or tcon or ip or`
309			`// t/c 2`
310			`t2con or tl2 or th2 or rcap2l or rcap2h or`
311			`// t/c 0,1`
312			`tmod or tl0 or th0 or tl1 or th1 or`
313			`// serial interface`
314			`scon or pcon or sbuf or`
315			`// stack`
316			`sp_out)`
317	75	simont	`begin`
318	82	simont	`case (adr0_r)`
319	116	simont	`OC8051_SFR_ACC: dat0 = acc;
320			`OC8051_SFR_PSW: dat0 = psw;
321			`OC8051_SFR_P0: dat0 = p0_data;
322			`OC8051_SFR_P1: dat0 = p1_data;
323			`OC8051_SFR_P2: dat0 = p2_data;
324			`OC8051_SFR_P3: dat0 = p3_data;
325			`OC8051_SFR_SP: dat0 = sp_out;
326			`OC8051_SFR_B: dat0 = b_reg;
327			`OC8051_SFR_DPTR_HI: dat0 = dptr_hi;
328			`OC8051_SFR_DPTR_LO: dat0 = dptr_lo;
329			`OC8051_SFR_SCON: dat0 = scon;
330			`OC8051_SFR_SBUF: dat0 = sbuf;
331			`OC8051_SFR_PCON: dat0 = pcon;
332			`OC8051_SFR_TH0: dat0 = th0;
333			`OC8051_SFR_TH1: dat0 = th1;
334			`OC8051_SFR_TL0: dat0 = tl0;
335			`OC8051_SFR_TL1: dat0 = tl1;
336			`OC8051_SFR_TMOD: dat0 = tmod;
337			`OC8051_SFR_IP: dat0 = ip;
338			`OC8051_SFR_IE: dat0 = ie;
339			`OC8051_SFR_TCON: dat0 = tcon;
340			`OC8051_SFR_RCAP2H: dat0 = rcap2h;
341			`OC8051_SFR_RCAP2L: dat0 = rcap2l;
342			`OC8051_SFR_TH2: dat0 = th2;
343			`OC8051_SFR_TL2: dat0 = tl2;
344			`OC8051_SFR_T2CON: dat0 = t2con;
345			`default: dat0 = 8'h00;`
346	82	simont	`endcase`
347	75	simont	`end`
348
349
350			`//`
351			`//set output in case of address (bit)`
352	116	simont	`always @(adr0_r or psw or acc or b_reg or`
353			`//ports`
354			`p0_data or p1_data or p2_data or p3_data or`
355			`//interrupt control`
356			`ie or tcon or ip or`
357			`// t/c 2`
358			`t2con or`
359			`// serial interface`
360			`scon)`
361	75	simont	`begin`
362	82	simont	`case (adr0_r[7:3])`
363	116	simont	`OC8051_SFR_B_ACC: bit_out = acc[adr0_r[2:0]];
364			`OC8051_SFR_B_PSW: bit_out = psw[adr0_r[2:0]];
365			`OC8051_SFR_B_P0: bit_out = p0_data[adr0_r[2:0]];
366			`OC8051_SFR_B_P1: bit_out = p1_data[adr0_r[2:0]];
367			`OC8051_SFR_B_P2: bit_out = p2_data[adr0_r[2:0]];
368			`OC8051_SFR_B_P3: bit_out = p3_data[adr0_r[2:0]];
369			`OC8051_SFR_B_B: bit_out = b_reg[adr0_r[2:0]];
370			`OC8051_SFR_B_IP: bit_out = ip[adr0_r[2:0]];
371			`OC8051_SFR_B_IE: bit_out = ie[adr0_r[2:0]];
372			`OC8051_SFR_B_TCON: bit_out = tcon[adr0_r[2:0]];
373			`OC8051_SFR_B_SCON: bit_out = scon[adr0_r[2:0]];
374			`OC8051_SFR_B_T2CON: bit_out = t2con[adr0_r[2:0]];
375			`default: bit_out = 1'b0;`
376	82	simont	`endcase`
377	75	simont	`end`
378	117	simont	`*/`
379	75	simont
380	117	simont
381
382			`//`
383			`//set output in case of address (byte)`
384			`always @(posedge clk or posedge rst)`
385			`begin`
386			`if (rst) begin`
387			`dat0 <= #1 8'h00;`
388			`wait_data <= #1 1'b0;`
389			/* end else if (((adr0==`OC8051_SFR_PSW) & (((adr1==`OC8051_SFR_ACC) & we & !wr_bit_r)) \|
390			`(({adr1[7:3], 3'b000}==adr0) & we & wr_bit_r)) & !wait_data) begin`
391			`// dat0 <= #1 {dat1[7:1], p};`
392			`wait_data <= #1 1'b1;`
393			end else if ((adr0==`OC8051_SFR_PSW) & (adr1==adr0) & we & !wr_bit_r & !wait_data) begin
394			`// dat0 <= #1 {dat1[7:1], p};`
395			`wait_data <= #1 1'b1;*/`
396			end else if ((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) begin //write and read same address
397			`dat0 <= #1 dat1;`
398			`wait_data <= #1 1'b0;`
399			`end else if (`
400			(((wr_sfr==`OC8051_WRS_ACC1) & (adr0==`OC8051_SFR_ACC)) \| //write to acc
401			((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_LO)) \| //write to dpl
402			((wr_sfr==`OC8051_WRS_BA) & (adr0==`OC8051_SFR_B)) \| //write to b
403			`(adr1[7] & (adr1==adr0) & we & !wr_bit_r)) & !wait_data) begin //write and read same address`
404			`// dat0 <= #1 dat1;`
405			`wait_data <= #1 1'b1;`
406
407			`end else if (`
408			(((wr_sfr==`OC8051_WRS_ACC2) & (adr0==`OC8051_SFR_ACC)) \| //write to acc
409			((wr_sfr==`OC8051_WRS_DPTR) & (adr0==`OC8051_SFR_DPTR_HI)) \| //write to dph
410			((wr_sfr==`OC8051_WRS_BA) & (adr0==`OC8051_SFR_ACC))) & !wait_data) begin //write to b
411			`// dat0 <= #1 dat2;`
412			`wait_data <= #1 1'b1;`
413
414			`// else if (({adr1[7:3], 3'b000}==adr0_r) & we & wr_bit_r)`
415			`// dat0 <= #1 dat1;`
416			`end else begin`
417			`case (adr0)`
418			`OC8051_SFR_ACC: dat0 <= #1 acc;
419			`OC8051_SFR_PSW: dat0 <= #1 psw;
420			`OC8051_SFR_P0: dat0 <= #1 p0_data;
421			`OC8051_SFR_P1: dat0 <= #1 p1_data;
422			`OC8051_SFR_P2: dat0 <= #1 p2_data;
423			`OC8051_SFR_P3: dat0 <= #1 p3_data;
424			// `OC8051_SFR_SP: dat0 <= #1 sp_out;
425			`OC8051_SFR_SP: dat0 <= #1 sp;
426			`OC8051_SFR_B: dat0 <= #1 b_reg;
427			`OC8051_SFR_DPTR_HI: dat0 <= #1 dptr_hi;
428			`OC8051_SFR_DPTR_LO: dat0 <= #1 dptr_lo;
429			`OC8051_SFR_SCON: dat0 <= #1 scon;
430			`OC8051_SFR_SBUF: dat0 <= #1 sbuf;
431			`OC8051_SFR_PCON: dat0 <= #1 pcon;
432			`OC8051_SFR_TH0: dat0 <= #1 th0;
433			`OC8051_SFR_TH1: dat0 <= #1 th1;
434			`OC8051_SFR_TL0: dat0 <= #1 tl0;
435			`OC8051_SFR_TL1: dat0 <= #1 tl1;
436			`OC8051_SFR_TMOD: dat0 <= #1 tmod;
437			`OC8051_SFR_IP: dat0 <= #1 ip;
438			`OC8051_SFR_IE: dat0 <= #1 ie;
439			`OC8051_SFR_TCON: dat0 <= #1 tcon;
440			`OC8051_SFR_RCAP2H: dat0 <= #1 rcap2h;
441			`OC8051_SFR_RCAP2L: dat0 <= #1 rcap2l;
442			`OC8051_SFR_TH2: dat0 <= #1 th2;
443			`OC8051_SFR_TL2: dat0 <= #1 tl2;
444			`OC8051_SFR_T2CON: dat0 <= #1 t2con;
445			`default: dat0 <= #1 8'h00;`
446			`endcase`
447			`wait_data <= #1 1'b0;`
448			`end`
449			`end`
450
451
452			`//`
453			`//set output in case of address (bit)`
454			`always @(posedge clk or posedge rst)`
455			`begin`
456			`if (rst)`
457			`bit_out <= #1 1'h0;`
458			`else if (`
459			`((adr1[7:3]==adr0[7:3]) & (~&adr1[2:0]) & we & !wr_bit_r) \|`
460			((wr_sfr==`OC8051_WRS_ACC1) & (adr0[7:3]==`OC8051_SFR_B_ACC)) \| //write to acc
461			((wr_sfr==`OC8051_WRS_BA) & (adr0[7:3]==`OC8051_SFR_B_B))) //write to b
462
463			`bit_out <= #1 dat1[adr0[2:0]];`
464			`else if ((adr1==adr0) & we & wr_bit_r)`
465			`bit_out <= #1 bit_in;`
466			`else`
467			`case (adr0[7:3])`
468			`OC8051_SFR_B_ACC: bit_out <= #1 acc[adr0[2:0]];
469			`OC8051_SFR_B_PSW: bit_out <= #1 psw[adr0[2:0]];
470			`OC8051_SFR_B_P0: bit_out <= #1 p0_data[adr0[2:0]];
471			`OC8051_SFR_B_P1: bit_out <= #1 p1_data[adr0[2:0]];
472			`OC8051_SFR_B_P2: bit_out <= #1 p2_data[adr0[2:0]];
473			`OC8051_SFR_B_P3: bit_out <= #1 p3_data[adr0[2:0]];
474			`OC8051_SFR_B_B: bit_out <= #1 b_reg[adr0[2:0]];
475			`OC8051_SFR_B_IP: bit_out <= #1 ip[adr0[2:0]];
476			`OC8051_SFR_B_IE: bit_out <= #1 ie[adr0[2:0]];
477			`OC8051_SFR_B_TCON: bit_out <= #1 tcon[adr0[2:0]];
478			`OC8051_SFR_B_SCON: bit_out <= #1 scon[adr0[2:0]];
479			`OC8051_SFR_B_T2CON: bit_out <= #1 t2con[adr0[2:0]];
480			`default: bit_out <= #1 1'b0;`
481			`endcase`
482			`end`
483
484
485	75	simont	`endmodule`

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