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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_sfr.v] - Blame information for rev 75

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores sfr top level module                             ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   special function registers for oc8051                      ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
 
module oc8051_sfr (rst, clk, adr0, adr1, dat0, dat1, dat2, we, bit_in, bit_out, wr_bit, wad2, acc,
       rd_x, xdata, ram_wr_sel, ram_rd_sel, sp, bank_sel, desAc, desOv, psw_set, srcAc, cy, rmw,
       p0_out, p1_out, p2_out, p3_out, p0_in, p1_in, p2_in, p3_in, rxd, txd, int_ack, intr, int0,
       int1, reti, int_src, t0, t1, dptr_hi, dptr_lo);
//
// rst           (in)  reset - pin
// clk           (in)  clock - pin
// adr0, adr1    (in)  address input
// dat0          (out) data output
// dat1          (in)  data input
// dat2
// we            (in)  write enable
// bit_in
// bit_out
// wr_bit
// ram_rd_sel
// ram_wr_sel
//////////
//
//  acc:
// wad2
// acc
// rd_x
// xdata
//////////
//
//  sp:
// sp
//////////
//
//  psw:
// bank_sel
// desAc
// desOv
// psw_set
// srcAc
// cy
//////////
//
//  ports:
// rmw
// px_out
// px_in
//////////
//
//  serial interface:
// rxd
// txd
//////////
//
//  interrupt interface:
// int_ack
// intr
// int0, int1
// reti
// int_src
//////////
//
//  timers/counters:
// t0
// t1
//
//////////
//
//  dptr:
// dptr_hi
// dptr_lo
 
 
 
 
 
input rst, clk, we, bit_in, wad2, desAc, desOv, rmw, rxd, int_ack, int0, int1, reti, wr_bit, rd_x;
input [1:0] ram_rd_sel, psw_set;
input [2:0] ram_wr_sel;
input [7:0] adr0, adr1, dat1, dat2, p0_in, p1_in, p2_in, p3_in, xdata;
 
output bit_out, txd, intr, t0, t1, srcAc, cy;
output [1:0] bank_sel;
output [7:0] dat0, p0_out, p1_out, p2_out, p3_out, int_src, dptr_hi, dptr_lo, acc, sp;
reg bit_out;
reg [7:0] dat0, sp_r, adr0_r;
 
reg [2:0] ram_wr_sel_r;
wire acc_bit, b_bit, psw_bit, port_bit, uart_bit, int_bit;
wire p, int_uart, tf0, tf1, tr0, tr1;
wire [7:0] b_reg, psw, ports, uart, int_out, tc_out;
 
assign cy = psw[7];
assign srcAc = psw [6];
 
//
// accumulator
// ACC
oc8051_acc oc8051_acc1(.clk(clk), .rst(rst), .bit_in(bit_in), .data_in(dat1),
           .data2_in(dat2), .wr(we), .wr_bit(wr_bit), .wad2(wad2),
           .wr_addr(adr1), .rd_addr(adr0[2:0]), .data_out(acc), .bit_out(acc_bit), .p(p),
           .rd_x(rd_x), .xdata(xdata));
 
 
//
// b register
// B
oc8051_b_register oc8051_b_register (.clk(clk), .rst(rst), .bit_in(bit_in), .bit_out(b_bit),
           .data_in(dat1), .wr(we), .wr_bit(wr_bit), .wr_addr(adr1), .rd_addr(adr0[2:0]),
           .data_out(b_reg));
 
//
//stack pointer
// SP
oc8051_sp oc8051_sp1(.clk(clk), .rst(rst), .ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel),
                 .wr_addr(adr1), .wr(we), .wr_bit(wr_bit), .data_in(dat1),
                 .data_out(sp));
 
//
//data pointer
// DPTR, DPH, DPL
oc8051_dptr oc8051_dptr1(.clk(clk), .rst(rst), .addr(adr1), .data_in(dat1),
                .data2_in(dat2), .wr(we), .wr_bit(wr_bit), .wd2(ram_wr_sel_r),
                .data_hi(dptr_hi), .data_lo(dptr_lo));
 
//
//program status word
// PSW
oc8051_psw oc8051_psw1 (.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0[2:0]), .data_in(dat1),
                .wr(we), .wr_bit(wr_bit), .data_out(psw), .bit_out(psw_bit), .p(p), .cy_in(bit_in),
                .ac_in(desAc), .ov_in(desOv), .set(psw_set), .bank_sel(bank_sel));
 
//
// ports
// P0, P1, P2, P3
oc8051_ports oc8051_ports1(.clk(clk), .rst(rst), .bit_in(bit_in), .data_in(dat1), .wr(we),
                 .wr_bit(wr_bit), .wr_addr(adr1), .rd_addr(adr0), .rmw(rmw),
                 .data_out(ports), .bit_out(port_bit), .p0_out(p0_out), .p1_out(p1_out),
                 .p2_out(p2_out), .p3_out(p3_out), .p0_in(p0_in), .p1_in(p1_in), .p2_in(p2_in),
                 .p3_in(p3_in));
 
//
// serial interface
// SCON, SBUF
oc8051_uart oc8051_uatr1 (.clk(clk), .rst(rst), .bit_in(bit_in), .rd_addr(adr0),
                .data_in(dat1), .wr(we), .wr_bit(wr_bit), .wr_addr(adr1),
                .data_out(uart), .bit_out(uart_bit), .rxd(rxd), .txd(txd), .intr(int_uart),
                .t1_ow(tf1));
 
//
// interrupt control
// IP, IE, TCON
oc0851_int oc8051_int1 (.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0), .bit_in(bit_in),
                .ack(int_ack), .intr(intr), .data_in(dat1), .data_out(int_out), .bit_out(int_bit),
                .wr(we), .wr_bit(wr_bit), .tf0(tf0), .tf1(tf1), .ie0(int0), .ie1(int1),
                .reti(reti), .int_vec(int_src), .tr0(tr0), .tr1(tr1), .uart(int_uart));
 
//
// timer/counter control
// TH0, TH1, TL0, TH1, TMOD
oc8051_tc oc8051_tc1(.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0),
                .data_in(dat1), .wr(we), .wr_bit(wr_bit), .ie0(int0), .ie1(int1), .tr0(tr0),
                .tr1(tr1), .t0(t0), .t1(t1), .data_out(tc_out), .tf0(tf0), .tf1(tf1));
 
 
always @(posedge clk or posedge rst)
  if (rst) begin
    sp_r <= #1 8'h00;
    adr0_r <= #1 8'h00;
    ram_wr_sel_r <= #1 3'b000;
  end else begin
    sp_r <= #1 sp;
    adr0_r <= #1 adr0;
    ram_wr_sel_r <= #1 ram_wr_sel;
  end
 
//
//set output in case of address (byte)
always @(adr0_r or psw or acc or dptr_hi or ports or sp_r or b_reg or uart or tc_out or int_out or dptr_lo)
begin
  case (adr0_r)
    `OC8051_SFR_ACC: dat0 = acc;
    `OC8051_SFR_PSW: dat0 = psw;
    `OC8051_SFR_P0: dat0 = ports;
    `OC8051_SFR_P1: dat0 = ports;
    `OC8051_SFR_P2: dat0 = ports;
    `OC8051_SFR_P3: dat0 = ports;
    `OC8051_SFR_SP: dat0 = sp_r;
    `OC8051_SFR_B: dat0 = b_reg;
    `OC8051_SFR_DPTR_HI: dat0 = dptr_hi;
    `OC8051_SFR_DPTR_LO: dat0 = dptr_lo;
    `OC8051_SFR_SCON: dat0 = uart;
    `OC8051_SFR_SBUF: dat0 = uart;
    `OC8051_SFR_PCON: dat0 = uart;
    `OC8051_SFR_TH0: dat0 = tc_out;
    `OC8051_SFR_TH1: dat0 = tc_out;
    `OC8051_SFR_TL0: dat0 = tc_out;
    `OC8051_SFR_TL1: dat0 = tc_out;
    `OC8051_SFR_TMOD: dat0 = tc_out;
    `OC8051_SFR_IP: dat0 = int_out;
    `OC8051_SFR_IE: dat0 = int_out;
    `OC8051_SFR_TCON: dat0 = int_out;
    default: dat0 = 8'h00;
  endcase
end
 
 
//
//set output in case of address (bit)
always @(adr0_r or b_bit or acc_bit or psw_bit or int_bit or port_bit or uart_bit)
begin
  case (adr0_r[7:3])
    `OC8051_SFR_B_ACC: bit_out = acc_bit;
    `OC8051_SFR_B_PSW: bit_out = psw_bit;
    `OC8051_SFR_B_P0: bit_out = port_bit;
    `OC8051_SFR_B_P1: bit_out = port_bit;
    `OC8051_SFR_B_P2: bit_out = port_bit;
    `OC8051_SFR_B_P3: bit_out = port_bit;
    `OC8051_SFR_B_B: bit_out = b_bit;
    `OC8051_SFR_B_IP: bit_out = int_bit;
    `OC8051_SFR_B_IE: bit_out = int_bit;
    `OC8051_SFR_B_TCON: bit_out = int_bit;
    `OC8051_SFR_B_SCON: bit_out = uart_bit;
    default: bit_out = 1'b0;
  endcase
end
 
endmodule

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_sfr.v] - Blame information for rev 75

Line No.	Rev	Author	Line
1	75	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores sfr top level module ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// special function registers for oc8051 ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`//`
48
49			`// synopsys translate_off`
50			`include "oc8051_timescale.v"
51			`// synopsys translate_on`
52
53
54			`module oc8051_sfr (rst, clk, adr0, adr1, dat0, dat1, dat2, we, bit_in, bit_out, wr_bit, wad2, acc,`
55			`rd_x, xdata, ram_wr_sel, ram_rd_sel, sp, bank_sel, desAc, desOv, psw_set, srcAc, cy, rmw,`
56			`p0_out, p1_out, p2_out, p3_out, p0_in, p1_in, p2_in, p3_in, rxd, txd, int_ack, intr, int0,`
57			`int1, reti, int_src, t0, t1, dptr_hi, dptr_lo);`
58			`//`
59			`// rst (in) reset - pin`
60			`// clk (in) clock - pin`
61			`// adr0, adr1 (in) address input`
62			`// dat0 (out) data output`
63			`// dat1 (in) data input`
64			`// dat2`
65			`// we (in) write enable`
66			`// bit_in`
67			`// bit_out`
68			`// wr_bit`
69			`// ram_rd_sel`
70			`// ram_wr_sel`
71			`//////////`
72			`//`
73			`// acc:`
74			`// wad2`
75			`// acc`
76			`// rd_x`
77			`// xdata`
78			`//////////`
79			`//`
80			`// sp:`
81			`// sp`
82			`//////////`
83			`//`
84			`// psw:`
85			`// bank_sel`
86			`// desAc`
87			`// desOv`
88			`// psw_set`
89			`// srcAc`
90			`// cy`
91			`//////////`
92			`//`
93			`// ports:`
94			`// rmw`
95			`// px_out`
96			`// px_in`
97			`//////////`
98			`//`
99			`// serial interface:`
100			`// rxd`
101			`// txd`
102			`//////////`
103			`//`
104			`// interrupt interface:`
105			`// int_ack`
106			`// intr`
107			`// int0, int1`
108			`// reti`
109			`// int_src`
110			`//////////`
111			`//`
112			`// timers/counters:`
113			`// t0`
114			`// t1`
115			`//`
116			`//////////`
117			`//`
118			`// dptr:`
119			`// dptr_hi`
120			`// dptr_lo`
121
122
123
124
125
126			`input rst, clk, we, bit_in, wad2, desAc, desOv, rmw, rxd, int_ack, int0, int1, reti, wr_bit, rd_x;`
127			`input [1:0] ram_rd_sel, psw_set;`
128			`input [2:0] ram_wr_sel;`
129			`input [7:0] adr0, adr1, dat1, dat2, p0_in, p1_in, p2_in, p3_in, xdata;`
130
131			`output bit_out, txd, intr, t0, t1, srcAc, cy;`
132			`output [1:0] bank_sel;`
133			`output [7:0] dat0, p0_out, p1_out, p2_out, p3_out, int_src, dptr_hi, dptr_lo, acc, sp;`
134			`reg bit_out;`
135			`reg [7:0] dat0, sp_r, adr0_r;`
136
137			`reg [2:0] ram_wr_sel_r;`
138			`wire acc_bit, b_bit, psw_bit, port_bit, uart_bit, int_bit;`
139			`wire p, int_uart, tf0, tf1, tr0, tr1;`
140			`wire [7:0] b_reg, psw, ports, uart, int_out, tc_out;`
141
142			`assign cy = psw[7];`
143			`assign srcAc = psw [6];`
144
145			`//`
146			`// accumulator`
147			`// ACC`
148			`oc8051_acc oc8051_acc1(.clk(clk), .rst(rst), .bit_in(bit_in), .data_in(dat1),`
149			`.data2_in(dat2), .wr(we), .wr_bit(wr_bit), .wad2(wad2),`
150			`.wr_addr(adr1), .rd_addr(adr0[2:0]), .data_out(acc), .bit_out(acc_bit), .p(p),`
151			`.rd_x(rd_x), .xdata(xdata));`
152
153
154			`//`
155			`// b register`
156			`// B`
157			`oc8051_b_register oc8051_b_register (.clk(clk), .rst(rst), .bit_in(bit_in), .bit_out(b_bit),`
158			`.data_in(dat1), .wr(we), .wr_bit(wr_bit), .wr_addr(adr1), .rd_addr(adr0[2:0]),`
159			`.data_out(b_reg));`
160
161			`//`
162			`//stack pointer`
163			`// SP`
164			`oc8051_sp oc8051_sp1(.clk(clk), .rst(rst), .ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel),`
165			`.wr_addr(adr1), .wr(we), .wr_bit(wr_bit), .data_in(dat1),`
166			`.data_out(sp));`
167
168			`//`
169			`//data pointer`
170			`// DPTR, DPH, DPL`
171			`oc8051_dptr oc8051_dptr1(.clk(clk), .rst(rst), .addr(adr1), .data_in(dat1),`
172			`.data2_in(dat2), .wr(we), .wr_bit(wr_bit), .wd2(ram_wr_sel_r),`
173			`.data_hi(dptr_hi), .data_lo(dptr_lo));`
174
175			`//`
176			`//program status word`
177			`// PSW`
178			`oc8051_psw oc8051_psw1 (.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0[2:0]), .data_in(dat1),`
179			`.wr(we), .wr_bit(wr_bit), .data_out(psw), .bit_out(psw_bit), .p(p), .cy_in(bit_in),`
180			`.ac_in(desAc), .ov_in(desOv), .set(psw_set), .bank_sel(bank_sel));`
181
182			`//`
183			`// ports`
184			`// P0, P1, P2, P3`
185			`oc8051_ports oc8051_ports1(.clk(clk), .rst(rst), .bit_in(bit_in), .data_in(dat1), .wr(we),`
186			`.wr_bit(wr_bit), .wr_addr(adr1), .rd_addr(adr0), .rmw(rmw),`
187			`.data_out(ports), .bit_out(port_bit), .p0_out(p0_out), .p1_out(p1_out),`
188			`.p2_out(p2_out), .p3_out(p3_out), .p0_in(p0_in), .p1_in(p1_in), .p2_in(p2_in),`
189			`.p3_in(p3_in));`
190
191			`//`
192			`// serial interface`
193			`// SCON, SBUF`
194			`oc8051_uart oc8051_uatr1 (.clk(clk), .rst(rst), .bit_in(bit_in), .rd_addr(adr0),`
195			`.data_in(dat1), .wr(we), .wr_bit(wr_bit), .wr_addr(adr1),`
196			`.data_out(uart), .bit_out(uart_bit), .rxd(rxd), .txd(txd), .intr(int_uart),`
197			`.t1_ow(tf1));`
198
199			`//`
200			`// interrupt control`
201			`// IP, IE, TCON`
202			`oc0851_int oc8051_int1 (.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0), .bit_in(bit_in),`
203			`.ack(int_ack), .intr(intr), .data_in(dat1), .data_out(int_out), .bit_out(int_bit),`
204			`.wr(we), .wr_bit(wr_bit), .tf0(tf0), .tf1(tf1), .ie0(int0), .ie1(int1),`
205			`.reti(reti), .int_vec(int_src), .tr0(tr0), .tr1(tr1), .uart(int_uart));`
206
207			`//`
208			`// timer/counter control`
209			`// TH0, TH1, TL0, TH1, TMOD`
210			`oc8051_tc oc8051_tc1(.clk(clk), .rst(rst), .wr_addr(adr1), .rd_addr(adr0),`
211			`.data_in(dat1), .wr(we), .wr_bit(wr_bit), .ie0(int0), .ie1(int1), .tr0(tr0),`
212			`.tr1(tr1), .t0(t0), .t1(t1), .data_out(tc_out), .tf0(tf0), .tf1(tf1));`
213
214
215			`always @(posedge clk or posedge rst)`
216			`if (rst) begin`
217			`sp_r <= #1 8'h00;`
218			`adr0_r <= #1 8'h00;`
219			`ram_wr_sel_r <= #1 3'b000;`
220			`end else begin`
221			`sp_r <= #1 sp;`
222			`adr0_r <= #1 adr0;`
223			`ram_wr_sel_r <= #1 ram_wr_sel;`
224			`end`
225
226			`//`
227			`//set output in case of address (byte)`
228			`always @(adr0_r or psw or acc or dptr_hi or ports or sp_r or b_reg or uart or tc_out or int_out or dptr_lo)`
229			`begin`
230			`case (adr0_r)`
231			`OC8051_SFR_ACC: dat0 = acc;
232			`OC8051_SFR_PSW: dat0 = psw;
233			`OC8051_SFR_P0: dat0 = ports;
234			`OC8051_SFR_P1: dat0 = ports;
235			`OC8051_SFR_P2: dat0 = ports;
236			`OC8051_SFR_P3: dat0 = ports;
237			`OC8051_SFR_SP: dat0 = sp_r;
238			`OC8051_SFR_B: dat0 = b_reg;
239			`OC8051_SFR_DPTR_HI: dat0 = dptr_hi;
240			`OC8051_SFR_DPTR_LO: dat0 = dptr_lo;
241			`OC8051_SFR_SCON: dat0 = uart;
242			`OC8051_SFR_SBUF: dat0 = uart;
243			`OC8051_SFR_PCON: dat0 = uart;
244			`OC8051_SFR_TH0: dat0 = tc_out;
245			`OC8051_SFR_TH1: dat0 = tc_out;
246			`OC8051_SFR_TL0: dat0 = tc_out;
247			`OC8051_SFR_TL1: dat0 = tc_out;
248			`OC8051_SFR_TMOD: dat0 = tc_out;
249			`OC8051_SFR_IP: dat0 = int_out;
250			`OC8051_SFR_IE: dat0 = int_out;
251			`OC8051_SFR_TCON: dat0 = int_out;
252			`default: dat0 = 8'h00;`
253			`endcase`
254			`end`
255
256
257			`//`
258			`//set output in case of address (bit)`
259			`always @(adr0_r or b_bit or acc_bit or psw_bit or int_bit or port_bit or uart_bit)`
260			`begin`
261			`case (adr0_r[7:3])`
262			`OC8051_SFR_B_ACC: bit_out = acc_bit;
263			`OC8051_SFR_B_PSW: bit_out = psw_bit;
264			`OC8051_SFR_B_P0: bit_out = port_bit;
265			`OC8051_SFR_B_P1: bit_out = port_bit;
266			`OC8051_SFR_B_P2: bit_out = port_bit;
267			`OC8051_SFR_B_P3: bit_out = port_bit;
268			`OC8051_SFR_B_B: bit_out = b_bit;
269			`OC8051_SFR_B_IP: bit_out = int_bit;
270			`OC8051_SFR_B_IE: bit_out = int_bit;
271			`OC8051_SFR_B_TCON: bit_out = int_bit;
272			`OC8051_SFR_B_SCON: bit_out = uart_bit;
273			`default: bit_out = 1'b0;`
274			`endcase`
275			`end`
276
277			`endmodule`