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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_tc.v] - Blame information for rev 17

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//
// version 0.9
//
 
 
//clk  clock (pin)
//rst  reset (pin)
//sfr_sel   address for selecting different registers (TMOD, TL0, TH0, TL1, TH1) (input)
//data_in   data input (input)
//wr   read/write signal (input)
//ie0  condition signal (one of), must be low for T/C 0 to start counting (input)
//ie1  condition signal (one of), must be low for T/C 1 to start counting (input)
//tr0  signal which activates Timer/Counter 0 (input)
//tr1  signal which activates Timer/Counter 1 (input)
//t0  external signal that increases Counter 0 (input)
//t1  external signal that increases Counter 1 (input)
//data_out  data output from the chosen register (TMOD, TL0, TH0, TL1, TH1) (output)
//tf0  overflow flag for T/C 0 (output)
//tf1  overflow flag for T/C 1 (output)
//tmod  register that describes T/C modes (internal)
//tl0   T/C 0 register, lower eight bits (internal)
//th0   T/C 0 register, higher eight bits (internal)
//tl1   T/C 1 register, lower eight bits (internal)
//th1   T/C 1 register, higher eight bits (internal)
 
 
 
 
 
 
`include "oc8051_defines.v"
 
//synopsys translate_off
`include "oc8051_timescale.v"
//synopsys translate_on
 
 
 
module oc8051_tc (clk, rst, wr_addr, rd_addr, data_in, wr, wr_bit, ie0, ie1, tr0, tr1, t0, t1, data_out,
            tf0, tf1);
input [7:0] wr_addr, data_in, rd_addr;
input clk, rst, wr, wr_bit, ie0, ie1, tr0, tr1, t0, t1;
output [7:0] data_out;
output tf0, tf1;
reg [7:0] tmod, tl0, th0, tl1, th1, data_out;
reg tf0, tf1_0, tf1_1, t0_buff, t1_buff;
 
wire tc0_add, tc1_add;
 
assign tc0_add = (tr0 & (!tmod[3] | !ie0) & (!(tmod[2]) | (tmod[2] & !t0 & t0_buff)));
assign tc1_add = (tr1 & (!tmod[7] | !ie1) & (!(tmod[6]) | (tmod[6] & !t1 & t1_buff)));
assign tf1= tf1_0 | tf1_1;
 
//
// read or write from one of the addresses in tmod
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tmod <=#1 `OC8051_RST_TMOD;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TMOD))
    tmod <= #1 data_in;
end
 
//
// TIMER COUNTER 0
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tl0 <=#1 `OC8051_RST_TL0;
   th0 <=#1 `OC8051_RST_TH0;
   tf0 <= #1 1'b0;
   tf1_0 <= #1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL0)) begin
   tl0 <= #1 data_in;
   tf0 <= #1 1'b0;
   tf1_0 <= #1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH0)) begin
   th0 <= #1 data_in;
   tf0 <= #1 1'b0;
   tf1_0 <= #1 1'b0;
 end else begin
     case (tmod[1:0])
      `OC8051_MODE0: begin                       // mode 0
        tf1_0 <= #1 1'b0;
        if (tc0_add)
          {tf0, th0,tl0[4:0]} <= #1 {1'b0, th0, tl0[4:0]}+ 1'b1;
      end
      `OC8051_MODE1: begin                       // mode 1
        tf1_0 <= #1 1'b0;
        if (tc0_add)
          {tf0, th0,tl0} <= #1 {1'b0, th0, tl0}+ 1'b1;
      end
 
      `OC8051_MODE2: begin                       // mode 2
        tf1_0 <= #1 1'b0;
        if (tc0_add) begin
          if (tl0 == 8'b1111_1111) begin
            tf0 <=#1 1'b1;
            tl0 <=#1 th0;
           end
          else begin
            tl0 <=#1 tl0 + 8'h1;
            tf0 <= #1 1'b0;
          end
        end
      end
      `OC8051_MODE3: begin                       // mode 3
 
         if (tc0_add)
           {tf0, tl0} <= #1 {1'b0, tl0} +1'b1;
 
         if (tr1)
           {tf1_0, th0} <= #1 {1'b0, th0} +1'b1;
 
      end
      default:begin
        tf0 <= #1 1'b0;
        tf1_0 <= #1 1'b0;
      end
    endcase
 end
end
 
//
// TIMER COUNTER 1
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tl1 <=#1 `OC8051_RST_TL1;
   th1 <=#1 `OC8051_RST_TH1;
   tf1_1 <= #1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL1)) begin
   tl1 <= #1 data_in;
   tf1_1 <= #1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH1)) begin
   th1 <= #1 data_in;
   tf1_1 <= #1 1'b0;
 end else begin
     case (tmod[5:4])
      `OC8051_MODE0: begin                       // mode 0
        if (tc1_add)
          {tf1_1, th1,tl1[4:0]} <= #1 {1'b0, th1, tl1[4:0]}+ 1'b1;
      end
      `OC8051_MODE1: begin                       // mode 1
        if (tc1_add)
          {tf1_1, th1,tl1} <= #1 {1'b0, th1, tl1}+ 1'b1;
      end
 
      `OC8051_MODE2: begin                       // mode 2
        if (tc1_add) begin
          if (tl1 == 8'b1111_1111) begin
            tf1_1 <=#1 1'b1;
            tl1 <=#1 th1;
           end
          else begin
            tl1 <=#1 tl1 + 8'h1;
            tf1_1 <= #1 1'b0;
          end
        end
      end
      default:begin
        tf1_1 <= #1 1'b0;
      end
    endcase
 end
end
 
always @(posedge clk or posedge rst)
begin
  if (rst) data_out <= #1 8'h0;
  else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_TH0) |
     (wr_addr==`OC8051_SFR_TH1)|(wr_addr==`OC8051_SFR_TL0)|(wr_addr==`OC8051_SFR_TL1)|
     (wr_addr==`OC8051_SFR_TMOD))) begin
    data_out <= #1 data_in;
  end else begin
    case (rd_addr)
      `OC8051_SFR_TH0: data_out <= #1 th0;
      `OC8051_SFR_TH1: data_out <= #1 th1;
      `OC8051_SFR_TL0: data_out <= #1 tl0;
      `OC8051_SFR_TL1: data_out <= #1 tl1;
      default: data_out <= #1 tmod;
    endcase
  end
end
 
 
always @(posedge clk or posedge rst)
  if (rst) begin
    t0_buff <= #1 1'b0;
    t1_buff <= #1 1'b0;
  end else begin
    t0_buff <= #1 t0;
    t1_buff <= #1 t1;
  end
endmodule

Line No.	Rev	Author	Line
1	2	simont	`//`
2			`// version 0.9`
3			`//`
4
5
6			`//clk clock (pin)`
7			`//rst reset (pin)`
8			`//sfr_sel address for selecting different registers (TMOD, TL0, TH0, TL1, TH1) (input)`
9			`//data_in data input (input)`
10			`//wr read/write signal (input)`
11			`//ie0 condition signal (one of), must be low for T/C 0 to start counting (input)`
12			`//ie1 condition signal (one of), must be low for T/C 1 to start counting (input)`
13			`//tr0 signal which activates Timer/Counter 0 (input)`
14			`//tr1 signal which activates Timer/Counter 1 (input)`
15			`//t0 external signal that increases Counter 0 (input)`
16			`//t1 external signal that increases Counter 1 (input)`
17			`//data_out data output from the chosen register (TMOD, TL0, TH0, TL1, TH1) (output)`
18			`//tf0 overflow flag for T/C 0 (output)`
19			`//tf1 overflow flag for T/C 1 (output)`
20			`//tmod register that describes T/C modes (internal)`
21			`//tl0 T/C 0 register, lower eight bits (internal)`
22			`//th0 T/C 0 register, higher eight bits (internal)`
23			`//tl1 T/C 1 register, lower eight bits (internal)`
24			`//th1 T/C 1 register, higher eight bits (internal)`
25
26
27
28
29
30
31			`include "oc8051_defines.v"
32
33			`//synopsys translate_off`
34			`include "oc8051_timescale.v"
35			`//synopsys translate_on`
36
37
38
39			`module oc8051_tc (clk, rst, wr_addr, rd_addr, data_in, wr, wr_bit, ie0, ie1, tr0, tr1, t0, t1, data_out,`
40			`tf0, tf1);`
41			`input [7:0] wr_addr, data_in, rd_addr;`
42			`input clk, rst, wr, wr_bit, ie0, ie1, tr0, tr1, t0, t1;`
43			`output [7:0] data_out;`
44			`output tf0, tf1;`
45			`reg [7:0] tmod, tl0, th0, tl1, th1, data_out;`
46			`reg tf0, tf1_0, tf1_1, t0_buff, t1_buff;`
47
48			`wire tc0_add, tc1_add;`
49
50			`assign tc0_add = (tr0 & (!tmod[3] \| !ie0) & (!(tmod[2]) \| (tmod[2] & !t0 & t0_buff)));`
51	17	simont	`assign tc1_add = (tr1 & (!tmod[7] \| !ie1) & (!(tmod[6]) \| (tmod[6] & !t1 & t1_buff)));`
52	2	simont	`assign tf1= tf1_0 \| tf1_1;`
53
54			`//`
55			`// read or write from one of the addresses in tmod`
56			`//`
57			`always @(posedge clk or posedge rst)`
58			`begin`
59			`if (rst) begin`
60			tmod <=#1 `OC8051_RST_TMOD;
61			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TMOD))
62			`tmod <= #1 data_in;`
63			`end`
64
65			`//`
66			`// TIMER COUNTER 0`
67			`//`
68			`always @(posedge clk or posedge rst)`
69			`begin`
70			`if (rst) begin`
71			tl0 <=#1 `OC8051_RST_TL0;
72			th0 <=#1 `OC8051_RST_TH0;
73			`tf0 <= #1 1'b0;`
74			`tf1_0 <= #1 1'b0;`
75			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL0)) begin
76			`tl0 <= #1 data_in;`
77			`tf0 <= #1 1'b0;`
78			`tf1_0 <= #1 1'b0;`
79			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH0)) begin
80			`th0 <= #1 data_in;`
81			`tf0 <= #1 1'b0;`
82			`tf1_0 <= #1 1'b0;`
83			`end else begin`
84			`case (tmod[1:0])`
85			`OC8051_MODE0: begin // mode 0
86			`tf1_0 <= #1 1'b0;`
87			`if (tc0_add)`
88			`{tf0, th0,tl0[4:0]} <= #1 {1'b0, th0, tl0[4:0]}+ 1'b1;`
89			`end`
90			`OC8051_MODE1: begin // mode 1
91			`tf1_0 <= #1 1'b0;`
92			`if (tc0_add)`
93			`{tf0, th0,tl0} <= #1 {1'b0, th0, tl0}+ 1'b1;`
94			`end`
95
96			`OC8051_MODE2: begin // mode 2
97			`tf1_0 <= #1 1'b0;`
98			`if (tc0_add) begin`
99			`if (tl0 == 8'b1111_1111) begin`
100			`tf0 <=#1 1'b1;`
101			`tl0 <=#1 th0;`
102			`end`
103			`else begin`
104	4	markom	`tl0 <=#1 tl0 + 8'h1;`
105	2	simont	`tf0 <= #1 1'b0;`
106			`end`
107			`end`
108			`end`
109			`OC8051_MODE3: begin // mode 3
110
111			`if (tc0_add)`
112			`{tf0, tl0} <= #1 {1'b0, tl0} +1'b1;`
113
114			`if (tr1)`
115			`{tf1_0, th0} <= #1 {1'b0, th0} +1'b1;`
116
117			`end`
118			`default:begin`
119			`tf0 <= #1 1'b0;`
120			`tf1_0 <= #1 1'b0;`
121			`end`
122			`endcase`
123			`end`
124			`end`
125
126			`//`
127			`// TIMER COUNTER 1`
128			`//`
129			`always @(posedge clk or posedge rst)`
130			`begin`
131			`if (rst) begin`
132			tl1 <=#1 `OC8051_RST_TL1;
133			th1 <=#1 `OC8051_RST_TH1;
134			`tf1_1 <= #1 1'b0;`
135			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL1)) begin
136			`tl1 <= #1 data_in;`
137			`tf1_1 <= #1 1'b0;`
138			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH1)) begin
139			`th1 <= #1 data_in;`
140			`tf1_1 <= #1 1'b0;`
141			`end else begin`
142			`case (tmod[5:4])`
143			`OC8051_MODE0: begin // mode 0
144			`if (tc1_add)`
145			`{tf1_1, th1,tl1[4:0]} <= #1 {1'b0, th1, tl1[4:0]}+ 1'b1;`
146			`end`
147			`OC8051_MODE1: begin // mode 1
148			`if (tc1_add)`
149			`{tf1_1, th1,tl1} <= #1 {1'b0, th1, tl1}+ 1'b1;`
150			`end`
151
152			`OC8051_MODE2: begin // mode 2
153			`if (tc1_add) begin`
154			`if (tl1 == 8'b1111_1111) begin`
155			`tf1_1 <=#1 1'b1;`
156			`tl1 <=#1 th1;`
157			`end`
158			`else begin`
159	4	markom	`tl1 <=#1 tl1 + 8'h1;`
160	2	simont	`tf1_1 <= #1 1'b0;`
161			`end`
162			`end`
163			`end`
164			`default:begin`
165			`tf1_1 <= #1 1'b0;`
166			`end`
167			`endcase`
168			`end`
169			`end`
170
171	4	markom	`always @(posedge clk or posedge rst)`
172	2	simont	`begin`
173	4	markom	`if (rst) data_out <= #1 8'h0;`
174			else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_TH0) \|
175	2	simont	(wr_addr==`OC8051_SFR_TH1)\|(wr_addr==`OC8051_SFR_TL0)\|(wr_addr==`OC8051_SFR_TL1)\|
176			(wr_addr==`OC8051_SFR_TMOD))) begin
177			`data_out <= #1 data_in;`
178			`end else begin`
179			`case (rd_addr)`
180			`OC8051_SFR_TH0: data_out <= #1 th0;
181			`OC8051_SFR_TH1: data_out <= #1 th1;
182			`OC8051_SFR_TL0: data_out <= #1 tl0;
183			`OC8051_SFR_TL1: data_out <= #1 tl1;
184			`default: data_out <= #1 tmod;`
185			`endcase`
186			`end`
187			`end`
188
189
190	4	markom	`always @(posedge clk or posedge rst)`
191			`if (rst) begin`
192			`t0_buff <= #1 1'b0;`
193			`t1_buff <= #1 1'b0;`
194			`end else begin`
195			`t0_buff <= #1 t0;`
196			`t1_buff <= #1 t1;`
197			`end`
198	2	simont	`endmodule`

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_tc.v] - Blame information for rev 17