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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_tc.v] - Blame information for rev 2

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//
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// version 0.9
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//
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//clk  clock (pin)
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//rst  reset (pin)
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//sfr_sel   address for selecting different registers (TMOD, TL0, TH0, TL1, TH1) (input)
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//data_in   data input (input)
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//wr   read/write signal (input)
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//ie0  condition signal (one of), must be low for T/C 0 to start counting (input)
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//ie1  condition signal (one of), must be low for T/C 1 to start counting (input)
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//tr0  signal which activates Timer/Counter 0 (input)
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//tr1  signal which activates Timer/Counter 1 (input)
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//t0  external signal that increases Counter 0 (input)
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//t1  external signal that increases Counter 1 (input)
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//data_out  data output from the chosen register (TMOD, TL0, TH0, TL1, TH1) (output)
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//tf0  overflow flag for T/C 0 (output)
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//tf1  overflow flag for T/C 1 (output)
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//tmod  register that describes T/C modes (internal)
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//tl0   T/C 0 register, lower eight bits (internal)
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//th0   T/C 0 register, higher eight bits (internal)
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//tl1   T/C 1 register, lower eight bits (internal)
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//th1   T/C 1 register, higher eight bits (internal)
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`include "oc8051_defines.v"
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//synopsys translate_off
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`include "oc8051_timescale.v"
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//synopsys translate_on
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module oc8051_tc (clk, rst, wr_addr, rd_addr, data_in, wr, wr_bit, ie0, ie1, tr0, tr1, t0, t1, data_out,
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            tf0, tf1);
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input [7:0] wr_addr, data_in, rd_addr;
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input clk, rst, wr, wr_bit, ie0, ie1, tr0, tr1, t0, t1;
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output [7:0] data_out;
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output tf0, tf1;
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reg [7:0] tmod, tl0, th0, tl1, th1, data_out;
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reg [1:0] tmp0, tmp1;
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reg tf0, tf1_0, tf1_1, t0_buff, t1_buff;
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wire tc0_add, tc1_add;
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assign tc0_add = (tr0 & (!tmod[3] | !ie0) & (!(tmod[2]) | (tmod[2] & !t0 & t0_buff)));
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assign tc1_add = (tr1 & (!tmod[7] | !ie0) & (!(tmod[6]) | (tmod[6] & !t1 & t1_buff)));
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assign tf1= tf1_0 | tf1_1;
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//
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// read or write from one of the addresses in tmod
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//
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always @(posedge clk or posedge rst)
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begin
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 if (rst) begin
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   tmod <=#1 `OC8051_RST_TMOD;
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 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TMOD))
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    tmod <= #1 data_in;
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end
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//
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// TIMER COUNTER 0
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//
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always @(posedge clk or posedge rst)
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begin
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 if (rst) begin
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   tl0 <=#1 `OC8051_RST_TL0;
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   th0 <=#1 `OC8051_RST_TH0;
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   tf0 <= #1 1'b0;
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   tf1_0 <= #1 1'b0;
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 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL0)) begin
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   tl0 <= #1 data_in;
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   tf0 <= #1 1'b0;
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   tf1_0 <= #1 1'b0;
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 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH0)) begin
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   th0 <= #1 data_in;
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   tf0 <= #1 1'b0;
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   tf1_0 <= #1 1'b0;
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 end else begin
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     case (tmod[1:0])
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      `OC8051_MODE0: begin                       // mode 0
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        tf1_0 <= #1 1'b0;
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        if (tc0_add)
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          {tf0, th0,tl0[4:0]} <= #1 {1'b0, th0, tl0[4:0]}+ 1'b1;
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      end
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      `OC8051_MODE1: begin                       // mode 1
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        tf1_0 <= #1 1'b0;
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        if (tc0_add)
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          {tf0, th0,tl0} <= #1 {1'b0, th0, tl0}+ 1'b1;
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      end
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      `OC8051_MODE2: begin                       // mode 2
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        tf1_0 <= #1 1'b0;
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        if (tc0_add) begin
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          if (tl0 == 8'b1111_1111) begin
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            tf0 <=#1 1'b1;
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            tl0 <=#1 th0;
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           end
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          else begin
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            tl0 <=#1 tl0 + 1;
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            tf0 <= #1 1'b0;
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          end
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        end
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      end
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      `OC8051_MODE3: begin                       // mode 3
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         if (tc0_add)
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           {tf0, tl0} <= #1 {1'b0, tl0} +1'b1;
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         if (tr1)
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           {tf1_0, th0} <= #1 {1'b0, th0} +1'b1;
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      end
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      default:begin
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        tf0 <= #1 1'b0;
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        tf1_0 <= #1 1'b0;
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      end
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    endcase
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 end
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end
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//
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// TIMER COUNTER 1
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//
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always @(posedge clk or posedge rst)
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begin
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 if (rst) begin
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   tl1 <=#1 `OC8051_RST_TL1;
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   th1 <=#1 `OC8051_RST_TH1;
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   tf1_1 <= #1 1'b0;
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 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL1)) begin
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   tl1 <= #1 data_in;
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   tf1_1 <= #1 1'b0;
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 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH1)) begin
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   th1 <= #1 data_in;
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   tf1_1 <= #1 1'b0;
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 end else begin
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     case (tmod[5:4])
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      `OC8051_MODE0: begin                       // mode 0
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        if (tc1_add)
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          {tf1_1, th1,tl1[4:0]} <= #1 {1'b0, th1, tl1[4:0]}+ 1'b1;
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      end
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      `OC8051_MODE1: begin                       // mode 1
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        if (tc1_add)
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          {tf1_1, th1,tl1} <= #1 {1'b0, th1, tl1}+ 1'b1;
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      end
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      `OC8051_MODE2: begin                       // mode 2
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        if (tc1_add) begin
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          if (tl1 == 8'b1111_1111) begin
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            tf1_1 <=#1 1'b1;
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            tl1 <=#1 th1;
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           end
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          else begin
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            tl1 <=#1 tl1 + 1;
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            tf1_1 <= #1 1'b0;
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          end
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        end
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      end
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      default:begin
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        tf1_1 <= #1 1'b0;
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      end
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    endcase
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 end
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end
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always @(posedge clk)
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begin
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  if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_TH0) |
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     (wr_addr==`OC8051_SFR_TH1)|(wr_addr==`OC8051_SFR_TL0)|(wr_addr==`OC8051_SFR_TL1)|
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     (wr_addr==`OC8051_SFR_TMOD))) begin
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    data_out <= #1 data_in;
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  end else begin
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    case (rd_addr)
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      `OC8051_SFR_TH0: data_out <= #1 th0;
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      `OC8051_SFR_TH1: data_out <= #1 th1;
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      `OC8051_SFR_TL0: data_out <= #1 tl0;
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      `OC8051_SFR_TL1: data_out <= #1 tl1;
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      default: data_out <= #1 tmod;
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    endcase
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  end
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end
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always @(posedge clk)
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  t0_buff <= #1 t0;
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always @(posedge clk)
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  t1_buff <= #1 t1;
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endmodule

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