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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_tc.v] - Blame information for rev 4

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//
// version 0.9
//
 
 
//clk  clock (pin)
//rst  reset (pin)
//sfr_sel   address for selecting different registers (TMOD, TL0, TH0, TL1, TH1) (input)
//data_in   data input (input)
//wr   read/write signal (input)
//ie0  condition signal (one of), must be low for T/C 0 to start counting (input)
//ie1  condition signal (one of), must be low for T/C 1 to start counting (input)
//tr0  signal which activates Timer/Counter 0 (input)
//tr1  signal which activates Timer/Counter 1 (input)
//t0  external signal that increases Counter 0 (input)
//t1  external signal that increases Counter 1 (input)
//data_out  data output from the chosen register (TMOD, TL0, TH0, TL1, TH1) (output)
//tf0  overflow flag for T/C 0 (output)
//tf1  overflow flag for T/C 1 (output)
//tmod  register that describes T/C modes (internal)
//tl0   T/C 0 register, lower eight bits (internal)
//th0   T/C 0 register, higher eight bits (internal)
//tl1   T/C 1 register, lower eight bits (internal)
//th1   T/C 1 register, higher eight bits (internal)
 
 
 
 
 
 
`include "oc8051_defines.v"
 
//synopsys translate_off
`include "oc8051_timescale.v"
//synopsys translate_on
 
 
 
module oc8051_tc (clk, rst, wr_addr, rd_addr, data_in, wr, wr_bit, ie0, ie1, tr0, tr1, t0, t1, data_out,
            tf0, tf1);
input [7:0] wr_addr, data_in, rd_addr;
input clk, rst, wr, wr_bit, ie0, ie1, tr0, tr1, t0, t1;
output [7:0] data_out;
output tf0, tf1;
reg [7:0] tmod, tl0, th0, tl1, th1, data_out;
reg [1:0] tmp0, tmp1;
reg tf0, tf1_0, tf1_1, t0_buff, t1_buff;
 
wire tc0_add, tc1_add;
 
assign tc0_add = (tr0 & (!tmod[3] | !ie0) & (!(tmod[2]) | (tmod[2] & !t0 & t0_buff)));
assign tc1_add = (tr1 & (!tmod[7] | !ie0) & (!(tmod[6]) | (tmod[6] & !t1 & t1_buff)));
assign tf1= tf1_0 | tf1_1;
 
//
// read or write from one of the addresses in tmod
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tmod <=#1 `OC8051_RST_TMOD;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TMOD))
    tmod <= #1 data_in;
end
 
//
// TIMER COUNTER 0
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tl0 <=#1 `OC8051_RST_TL0;
   th0 <=#1 `OC8051_RST_TH0;
   tf0 <= #1 1'b0;
   tf1_0 <= #1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL0)) begin
   tl0 <= #1 data_in;
   tf0 <= #1 1'b0;
   tf1_0 <= #1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH0)) begin
   th0 <= #1 data_in;
   tf0 <= #1 1'b0;
   tf1_0 <= #1 1'b0;
 end else begin
     case (tmod[1:0])
      `OC8051_MODE0: begin                       // mode 0
        tf1_0 <= #1 1'b0;
        if (tc0_add)
          {tf0, th0,tl0[4:0]} <= #1 {1'b0, th0, tl0[4:0]}+ 1'b1;
      end
      `OC8051_MODE1: begin                       // mode 1
        tf1_0 <= #1 1'b0;
        if (tc0_add)
          {tf0, th0,tl0} <= #1 {1'b0, th0, tl0}+ 1'b1;
      end
 
      `OC8051_MODE2: begin                       // mode 2
        tf1_0 <= #1 1'b0;
        if (tc0_add) begin
          if (tl0 == 8'b1111_1111) begin
            tf0 <=#1 1'b1;
            tl0 <=#1 th0;
           end
          else begin
            tl0 <=#1 tl0 + 8'h1;
            tf0 <= #1 1'b0;
          end
        end
      end
      `OC8051_MODE3: begin                       // mode 3
 
         if (tc0_add)
           {tf0, tl0} <= #1 {1'b0, tl0} +1'b1;
 
         if (tr1)
           {tf1_0, th0} <= #1 {1'b0, th0} +1'b1;
 
      end
      default:begin
        tf0 <= #1 1'b0;
        tf1_0 <= #1 1'b0;
      end
    endcase
 end
end
 
//
// TIMER COUNTER 1
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tl1 <=#1 `OC8051_RST_TL1;
   th1 <=#1 `OC8051_RST_TH1;
   tf1_1 <= #1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL1)) begin
   tl1 <= #1 data_in;
   tf1_1 <= #1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH1)) begin
   th1 <= #1 data_in;
   tf1_1 <= #1 1'b0;
 end else begin
     case (tmod[5:4])
      `OC8051_MODE0: begin                       // mode 0
        if (tc1_add)
          {tf1_1, th1,tl1[4:0]} <= #1 {1'b0, th1, tl1[4:0]}+ 1'b1;
      end
      `OC8051_MODE1: begin                       // mode 1
        if (tc1_add)
          {tf1_1, th1,tl1} <= #1 {1'b0, th1, tl1}+ 1'b1;
      end
 
      `OC8051_MODE2: begin                       // mode 2
        if (tc1_add) begin
          if (tl1 == 8'b1111_1111) begin
            tf1_1 <=#1 1'b1;
            tl1 <=#1 th1;
           end
          else begin
            tl1 <=#1 tl1 + 8'h1;
            tf1_1 <= #1 1'b0;
          end
        end
      end
      default:begin
        tf1_1 <= #1 1'b0;
      end
    endcase
 end
end
 
always @(posedge clk or posedge rst)
begin
  if (rst) data_out <= #1 8'h0;
  else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_TH0) |
     (wr_addr==`OC8051_SFR_TH1)|(wr_addr==`OC8051_SFR_TL0)|(wr_addr==`OC8051_SFR_TL1)|
     (wr_addr==`OC8051_SFR_TMOD))) begin
    data_out <= #1 data_in;
  end else begin
    case (rd_addr)
      `OC8051_SFR_TH0: data_out <= #1 th0;
      `OC8051_SFR_TH1: data_out <= #1 th1;
      `OC8051_SFR_TL0: data_out <= #1 tl0;
      `OC8051_SFR_TL1: data_out <= #1 tl1;
      default: data_out <= #1 tmod;
    endcase
  end
end
 
 
always @(posedge clk or posedge rst)
  if (rst) begin
    t0_buff <= #1 1'b0;
    t1_buff <= #1 1'b0;
  end else begin
    t0_buff <= #1 t0;
    t1_buff <= #1 t1;
  end
endmodule

Line No.	Rev	Author	Line
1	2	simont	`//`
2			`// version 0.9`
3			`//`
4
5
6			`//clk clock (pin)`
7			`//rst reset (pin)`
8			`//sfr_sel address for selecting different registers (TMOD, TL0, TH0, TL1, TH1) (input)`
9			`//data_in data input (input)`
10			`//wr read/write signal (input)`
11			`//ie0 condition signal (one of), must be low for T/C 0 to start counting (input)`
12			`//ie1 condition signal (one of), must be low for T/C 1 to start counting (input)`
13			`//tr0 signal which activates Timer/Counter 0 (input)`
14			`//tr1 signal which activates Timer/Counter 1 (input)`
15			`//t0 external signal that increases Counter 0 (input)`
16			`//t1 external signal that increases Counter 1 (input)`
17			`//data_out data output from the chosen register (TMOD, TL0, TH0, TL1, TH1) (output)`
18			`//tf0 overflow flag for T/C 0 (output)`
19			`//tf1 overflow flag for T/C 1 (output)`
20			`//tmod register that describes T/C modes (internal)`
21			`//tl0 T/C 0 register, lower eight bits (internal)`
22			`//th0 T/C 0 register, higher eight bits (internal)`
23			`//tl1 T/C 1 register, lower eight bits (internal)`
24			`//th1 T/C 1 register, higher eight bits (internal)`
25
26
27
28
29
30
31			`include "oc8051_defines.v"
32
33			`//synopsys translate_off`
34			`include "oc8051_timescale.v"
35			`//synopsys translate_on`
36
37
38
39			`module oc8051_tc (clk, rst, wr_addr, rd_addr, data_in, wr, wr_bit, ie0, ie1, tr0, tr1, t0, t1, data_out,`
40			`tf0, tf1);`
41			`input [7:0] wr_addr, data_in, rd_addr;`
42			`input clk, rst, wr, wr_bit, ie0, ie1, tr0, tr1, t0, t1;`
43			`output [7:0] data_out;`
44			`output tf0, tf1;`
45			`reg [7:0] tmod, tl0, th0, tl1, th1, data_out;`
46			`reg [1:0] tmp0, tmp1;`
47			`reg tf0, tf1_0, tf1_1, t0_buff, t1_buff;`
48
49			`wire tc0_add, tc1_add;`
50
51			`assign tc0_add = (tr0 & (!tmod[3] \| !ie0) & (!(tmod[2]) \| (tmod[2] & !t0 & t0_buff)));`
52			`assign tc1_add = (tr1 & (!tmod[7] \| !ie0) & (!(tmod[6]) \| (tmod[6] & !t1 & t1_buff)));`
53			`assign tf1= tf1_0 \| tf1_1;`
54
55			`//`
56			`// read or write from one of the addresses in tmod`
57			`//`
58			`always @(posedge clk or posedge rst)`
59			`begin`
60			`if (rst) begin`
61			tmod <=#1 `OC8051_RST_TMOD;
62			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TMOD))
63			`tmod <= #1 data_in;`
64			`end`
65
66			`//`
67			`// TIMER COUNTER 0`
68			`//`
69			`always @(posedge clk or posedge rst)`
70			`begin`
71			`if (rst) begin`
72			tl0 <=#1 `OC8051_RST_TL0;
73			th0 <=#1 `OC8051_RST_TH0;
74			`tf0 <= #1 1'b0;`
75			`tf1_0 <= #1 1'b0;`
76			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL0)) begin
77			`tl0 <= #1 data_in;`
78			`tf0 <= #1 1'b0;`
79			`tf1_0 <= #1 1'b0;`
80			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH0)) begin
81			`th0 <= #1 data_in;`
82			`tf0 <= #1 1'b0;`
83			`tf1_0 <= #1 1'b0;`
84			`end else begin`
85			`case (tmod[1:0])`
86			`OC8051_MODE0: begin // mode 0
87			`tf1_0 <= #1 1'b0;`
88			`if (tc0_add)`
89			`{tf0, th0,tl0[4:0]} <= #1 {1'b0, th0, tl0[4:0]}+ 1'b1;`
90			`end`
91			`OC8051_MODE1: begin // mode 1
92			`tf1_0 <= #1 1'b0;`
93			`if (tc0_add)`
94			`{tf0, th0,tl0} <= #1 {1'b0, th0, tl0}+ 1'b1;`
95			`end`
96
97			`OC8051_MODE2: begin // mode 2
98			`tf1_0 <= #1 1'b0;`
99			`if (tc0_add) begin`
100			`if (tl0 == 8'b1111_1111) begin`
101			`tf0 <=#1 1'b1;`
102			`tl0 <=#1 th0;`
103			`end`
104			`else begin`
105	4	markom	`tl0 <=#1 tl0 + 8'h1;`
106	2	simont	`tf0 <= #1 1'b0;`
107			`end`
108			`end`
109			`end`
110			`OC8051_MODE3: begin // mode 3
111
112			`if (tc0_add)`
113			`{tf0, tl0} <= #1 {1'b0, tl0} +1'b1;`
114
115			`if (tr1)`
116			`{tf1_0, th0} <= #1 {1'b0, th0} +1'b1;`
117
118			`end`
119			`default:begin`
120			`tf0 <= #1 1'b0;`
121			`tf1_0 <= #1 1'b0;`
122			`end`
123			`endcase`
124			`end`
125			`end`
126
127			`//`
128			`// TIMER COUNTER 1`
129			`//`
130			`always @(posedge clk or posedge rst)`
131			`begin`
132			`if (rst) begin`
133			tl1 <=#1 `OC8051_RST_TL1;
134			th1 <=#1 `OC8051_RST_TH1;
135			`tf1_1 <= #1 1'b0;`
136			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL1)) begin
137			`tl1 <= #1 data_in;`
138			`tf1_1 <= #1 1'b0;`
139			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH1)) begin
140			`th1 <= #1 data_in;`
141			`tf1_1 <= #1 1'b0;`
142			`end else begin`
143			`case (tmod[5:4])`
144			`OC8051_MODE0: begin // mode 0
145			`if (tc1_add)`
146			`{tf1_1, th1,tl1[4:0]} <= #1 {1'b0, th1, tl1[4:0]}+ 1'b1;`
147			`end`
148			`OC8051_MODE1: begin // mode 1
149			`if (tc1_add)`
150			`{tf1_1, th1,tl1} <= #1 {1'b0, th1, tl1}+ 1'b1;`
151			`end`
152
153			`OC8051_MODE2: begin // mode 2
154			`if (tc1_add) begin`
155			`if (tl1 == 8'b1111_1111) begin`
156			`tf1_1 <=#1 1'b1;`
157			`tl1 <=#1 th1;`
158			`end`
159			`else begin`
160	4	markom	`tl1 <=#1 tl1 + 8'h1;`
161	2	simont	`tf1_1 <= #1 1'b0;`
162			`end`
163			`end`
164			`end`
165			`default:begin`
166			`tf1_1 <= #1 1'b0;`
167			`end`
168			`endcase`
169			`end`
170			`end`
171
172	4	markom	`always @(posedge clk or posedge rst)`
173	2	simont	`begin`
174	4	markom	`if (rst) data_out <= #1 8'h0;`
175			else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_TH0) \|
176	2	simont	(wr_addr==`OC8051_SFR_TH1)\|(wr_addr==`OC8051_SFR_TL0)\|(wr_addr==`OC8051_SFR_TL1)\|
177			(wr_addr==`OC8051_SFR_TMOD))) begin
178			`data_out <= #1 data_in;`
179			`end else begin`
180			`case (rd_addr)`
181			`OC8051_SFR_TH0: data_out <= #1 th0;
182			`OC8051_SFR_TH1: data_out <= #1 th1;
183			`OC8051_SFR_TL0: data_out <= #1 tl0;
184			`OC8051_SFR_TL1: data_out <= #1 tl1;
185			`default: data_out <= #1 tmod;`
186			`endcase`
187			`end`
188			`end`
189
190
191	4	markom	`always @(posedge clk or posedge rst)`
192			`if (rst) begin`
193			`t0_buff <= #1 1'b0;`
194			`t1_buff <= #1 1'b0;`
195			`end else begin`
196			`t0_buff <= #1 t0;`
197			`t1_buff <= #1 t1;`
198			`end`
199	2	simont	`endmodule`

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_tc.v] - Blame information for rev 4