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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_tc.v] - Blame information for rev 82

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores timer/counter control                            ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   timers and counters handling for 8051 core                 ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2002/09/30 17:33:59  simont
// prepared header
//
//
 
`include "oc8051_defines.v"
 
//synopsys translate_off
`include "oc8051_timescale.v"
//synopsys translate_on
 
 
 
module oc8051_tc (clk, rst, wr_addr, rd_addr, data_in, wr, wr_bit, ie0, ie1, tr0, tr1, t0, t1, data_out,
            tf0, tf1);
 
input [7:0] wr_addr, data_in, rd_addr;
input clk, rst, wr, wr_bit, ie0, ie1, tr0, tr1, t0, t1;
output [7:0] data_out;
output tf0, tf1;
 
reg [7:0] tmod, tl0, th0, tl1, th1, data_out;
reg tf0, tf1_0, tf1_1, t0_buff, t1_buff;
 
wire tc0_add, tc1_add;
 
assign tc0_add = (tr0 & (!tmod[3] | !ie0) & (!(tmod[2]) | (tmod[2] & !t0 & t0_buff)));
assign tc1_add = (tr1 & (!tmod[7] | !ie1) & (!(tmod[6]) | (tmod[6] & !t1 & t1_buff)));
assign tf1= tf1_0 | tf1_1;
 
//
// read or write from one of the addresses in tmod
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tmod <=#1 `OC8051_RST_TMOD;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TMOD))
    tmod <= #1 data_in;
end
 
//
// TIMER COUNTER 0
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tl0 <=#1 `OC8051_RST_TL0;
   th0 <=#1 `OC8051_RST_TH0;
   tf0 <= #1 1'b0;
   tf1_0 <= #1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL0)) begin
   tl0 <= #1 data_in;
   tf0 <= #1 1'b0;
   tf1_0 <= #1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH0)) begin
   th0 <= #1 data_in;
   tf0 <= #1 1'b0;
   tf1_0 <= #1 1'b0;
 end else begin
     case (tmod[1:0])
      `OC8051_MODE0: begin                       // mode 0
        tf1_0 <= #1 1'b0;
        if (tc0_add)
          {tf0, th0,tl0[4:0]} <= #1 {1'b0, th0, tl0[4:0]}+ 1'b1;
      end
      `OC8051_MODE1: begin                       // mode 1
        tf1_0 <= #1 1'b0;
        if (tc0_add)
          {tf0, th0,tl0} <= #1 {1'b0, th0, tl0}+ 1'b1;
      end
 
      `OC8051_MODE2: begin                       // mode 2
        tf1_0 <= #1 1'b0;
        if (tc0_add) begin
          if (tl0 == 8'b1111_1111) begin
            tf0 <=#1 1'b1;
            tl0 <=#1 th0;
           end
          else begin
            tl0 <=#1 tl0 + 8'h1;
            tf0 <= #1 1'b0;
          end
        end
      end
      `OC8051_MODE3: begin                       // mode 3
 
         if (tc0_add)
           {tf0, tl0} <= #1 {1'b0, tl0} +1'b1;
 
         if (tr1)
           {tf1_0, th0} <= #1 {1'b0, th0} +1'b1;
 
      end
      default:begin
        tf0 <= #1 1'b0;
        tf1_0 <= #1 1'b0;
      end
    endcase
 end
end
 
//
// TIMER COUNTER 1
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tl1 <=#1 `OC8051_RST_TL1;
   th1 <=#1 `OC8051_RST_TH1;
   tf1_1 <= #1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL1)) begin
   tl1 <= #1 data_in;
   tf1_1 <= #1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH1)) begin
   th1 <= #1 data_in;
   tf1_1 <= #1 1'b0;
 end else begin
     case (tmod[5:4])
      `OC8051_MODE0: begin                       // mode 0
        if (tc1_add)
          {tf1_1, th1,tl1[4:0]} <= #1 {1'b0, th1, tl1[4:0]}+ 1'b1;
      end
      `OC8051_MODE1: begin                       // mode 1
        if (tc1_add)
          {tf1_1, th1,tl1} <= #1 {1'b0, th1, tl1}+ 1'b1;
      end
 
      `OC8051_MODE2: begin                       // mode 2
        if (tc1_add) begin
          if (tl1 == 8'b1111_1111) begin
            tf1_1 <=#1 1'b1;
            tl1 <=#1 th1;
           end
          else begin
            tl1 <=#1 tl1 + 8'h1;
            tf1_1 <= #1 1'b0;
          end
        end
      end
      default:begin
        tf1_1 <= #1 1'b0;
      end
    endcase
 end
end
 
always @(posedge clk or posedge rst)
begin
  if (rst) data_out <= #1 8'h0;
  else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_TH0) |
     (wr_addr==`OC8051_SFR_TH1)|(wr_addr==`OC8051_SFR_TL0)|(wr_addr==`OC8051_SFR_TL1)|
     (wr_addr==`OC8051_SFR_TMOD))) begin
    data_out <= #1 data_in;
  end else begin
    case (rd_addr)
      `OC8051_SFR_TH0: data_out <= #1 th0;
      `OC8051_SFR_TH1: data_out <= #1 th1;
      `OC8051_SFR_TL0: data_out <= #1 tl0;
      `OC8051_SFR_TL1: data_out <= #1 tl1;
      default: data_out <= #1 tmod;
    endcase
  end
end
 
 
always @(posedge clk or posedge rst)
  if (rst) begin
    t0_buff <= #1 1'b0;
    t1_buff <= #1 1'b0;
  end else begin
    t0_buff <= #1 t0;
    t1_buff <= #1 t1;
  end
endmodule

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_tc.v] - Blame information for rev 82

Line No.	Rev	Author	Line
1	82	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores timer/counter control ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// timers and counters handling for 8051 core ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// Nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.4 2002/09/30 17:33:59 simont`
48			`// prepared header`
49			`//`
50			`//`
51
52			`include "oc8051_defines.v"
53
54			`//synopsys translate_off`
55			`include "oc8051_timescale.v"
56			`//synopsys translate_on`
57
58
59
60			`module oc8051_tc (clk, rst, wr_addr, rd_addr, data_in, wr, wr_bit, ie0, ie1, tr0, tr1, t0, t1, data_out,`
61			`tf0, tf1);`
62
63			`input [7:0] wr_addr, data_in, rd_addr;`
64			`input clk, rst, wr, wr_bit, ie0, ie1, tr0, tr1, t0, t1;`
65			`output [7:0] data_out;`
66			`output tf0, tf1;`
67
68			`reg [7:0] tmod, tl0, th0, tl1, th1, data_out;`
69			`reg tf0, tf1_0, tf1_1, t0_buff, t1_buff;`
70
71			`wire tc0_add, tc1_add;`
72
73			`assign tc0_add = (tr0 & (!tmod[3] \| !ie0) & (!(tmod[2]) \| (tmod[2] & !t0 & t0_buff)));`
74			`assign tc1_add = (tr1 & (!tmod[7] \| !ie1) & (!(tmod[6]) \| (tmod[6] & !t1 & t1_buff)));`
75			`assign tf1= tf1_0 \| tf1_1;`
76
77			`//`
78			`// read or write from one of the addresses in tmod`
79			`//`
80			`always @(posedge clk or posedge rst)`
81			`begin`
82			`if (rst) begin`
83			tmod <=#1 `OC8051_RST_TMOD;
84			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TMOD))
85			`tmod <= #1 data_in;`
86			`end`
87
88			`//`
89			`// TIMER COUNTER 0`
90			`//`
91			`always @(posedge clk or posedge rst)`
92			`begin`
93			`if (rst) begin`
94			tl0 <=#1 `OC8051_RST_TL0;
95			th0 <=#1 `OC8051_RST_TH0;
96			`tf0 <= #1 1'b0;`
97			`tf1_0 <= #1 1'b0;`
98			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL0)) begin
99			`tl0 <= #1 data_in;`
100			`tf0 <= #1 1'b0;`
101			`tf1_0 <= #1 1'b0;`
102			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH0)) begin
103			`th0 <= #1 data_in;`
104			`tf0 <= #1 1'b0;`
105			`tf1_0 <= #1 1'b0;`
106			`end else begin`
107			`case (tmod[1:0])`
108			`OC8051_MODE0: begin // mode 0
109			`tf1_0 <= #1 1'b0;`
110			`if (tc0_add)`
111			`{tf0, th0,tl0[4:0]} <= #1 {1'b0, th0, tl0[4:0]}+ 1'b1;`
112			`end`
113			`OC8051_MODE1: begin // mode 1
114			`tf1_0 <= #1 1'b0;`
115			`if (tc0_add)`
116			`{tf0, th0,tl0} <= #1 {1'b0, th0, tl0}+ 1'b1;`
117			`end`
118
119			`OC8051_MODE2: begin // mode 2
120			`tf1_0 <= #1 1'b0;`
121			`if (tc0_add) begin`
122			`if (tl0 == 8'b1111_1111) begin`
123			`tf0 <=#1 1'b1;`
124			`tl0 <=#1 th0;`
125			`end`
126			`else begin`
127			`tl0 <=#1 tl0 + 8'h1;`
128			`tf0 <= #1 1'b0;`
129			`end`
130			`end`
131			`end`
132			`OC8051_MODE3: begin // mode 3
133
134			`if (tc0_add)`
135			`{tf0, tl0} <= #1 {1'b0, tl0} +1'b1;`
136
137			`if (tr1)`
138			`{tf1_0, th0} <= #1 {1'b0, th0} +1'b1;`
139
140			`end`
141			`default:begin`
142			`tf0 <= #1 1'b0;`
143			`tf1_0 <= #1 1'b0;`
144			`end`
145			`endcase`
146			`end`
147			`end`
148
149			`//`
150			`// TIMER COUNTER 1`
151			`//`
152			`always @(posedge clk or posedge rst)`
153			`begin`
154			`if (rst) begin`
155			tl1 <=#1 `OC8051_RST_TL1;
156			th1 <=#1 `OC8051_RST_TH1;
157			`tf1_1 <= #1 1'b0;`
158			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL1)) begin
159			`tl1 <= #1 data_in;`
160			`tf1_1 <= #1 1'b0;`
161			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH1)) begin
162			`th1 <= #1 data_in;`
163			`tf1_1 <= #1 1'b0;`
164			`end else begin`
165			`case (tmod[5:4])`
166			`OC8051_MODE0: begin // mode 0
167			`if (tc1_add)`
168			`{tf1_1, th1,tl1[4:0]} <= #1 {1'b0, th1, tl1[4:0]}+ 1'b1;`
169			`end`
170			`OC8051_MODE1: begin // mode 1
171			`if (tc1_add)`
172			`{tf1_1, th1,tl1} <= #1 {1'b0, th1, tl1}+ 1'b1;`
173			`end`
174
175			`OC8051_MODE2: begin // mode 2
176			`if (tc1_add) begin`
177			`if (tl1 == 8'b1111_1111) begin`
178			`tf1_1 <=#1 1'b1;`
179			`tl1 <=#1 th1;`
180			`end`
181			`else begin`
182			`tl1 <=#1 tl1 + 8'h1;`
183			`tf1_1 <= #1 1'b0;`
184			`end`
185			`end`
186			`end`
187			`default:begin`
188			`tf1_1 <= #1 1'b0;`
189			`end`
190			`endcase`
191			`end`
192			`end`
193
194			`always @(posedge clk or posedge rst)`
195			`begin`
196			`if (rst) data_out <= #1 8'h0;`
197			else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_TH0) \|
198			(wr_addr==`OC8051_SFR_TH1)\|(wr_addr==`OC8051_SFR_TL0)\|(wr_addr==`OC8051_SFR_TL1)\|
199			(wr_addr==`OC8051_SFR_TMOD))) begin
200			`data_out <= #1 data_in;`
201			`end else begin`
202			`case (rd_addr)`
203			`OC8051_SFR_TH0: data_out <= #1 th0;
204			`OC8051_SFR_TH1: data_out <= #1 th1;
205			`OC8051_SFR_TL0: data_out <= #1 tl0;
206			`OC8051_SFR_TL1: data_out <= #1 tl1;
207			`default: data_out <= #1 tmod;`
208			`endcase`
209			`end`
210			`end`
211
212
213			`always @(posedge clk or posedge rst)`
214			`if (rst) begin`
215			`t0_buff <= #1 1'b0;`
216			`t1_buff <= #1 1'b0;`
217			`end else begin`
218			`t0_buff <= #1 t0;`
219			`t1_buff <= #1 t1;`
220			`end`
221			`endmodule`