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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores serial interface                                 ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   uart for 8051 core                                         ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.14  2003/04/29 11:25:42  simont
// prepared start of receiving if ren is not active.
//
// Revision 1.13  2003/04/10 08:57:16  simont
// remove signal sbuf_txd [12:11]
//
// Revision 1.12  2003/04/07 14:58:02  simont
// change sfr's interface.
//
// Revision 1.11  2003/04/07 13:29:16  simont
// change uart to meet timing.
//
// Revision 1.10  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.9  2002/09/30 17:33:59  simont
// prepared header
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
module oc8051_uart (rst, clk,
             bit_in, data_in,
             wr_addr,
             wr, wr_bit,
             rxd, txd,
             intr,
             brate2, t1_ow, pres_ow,
             rclk, tclk,
//registers
             scon, pcon, sbuf);
 
input        rst,
             clk,
             bit_in,
             wr,
             rxd,
             wr_bit,
             t1_ow,
             brate2,
             pres_ow,
             rclk,
             tclk;
input [7:0]  data_in,
             wr_addr;
 
output       txd,
             intr;
output [7:0] scon,
             pcon,
             sbuf;
 
 
reg t1_ow_buf;
//
reg [7:0] scon, pcon;
 
 
reg        txd,
           trans,
           receive,
           tx_done,
           rx_done,
           rxd_r,
           shift_tr,
           shift_re;
reg [1:0]  rx_sam;
reg [3:0]  tr_count,
           re_count;
reg [7:0]  sbuf_rxd;
reg [11:0] sbuf_rxd_tmp;
reg [10:0] sbuf_txd;
 
assign sbuf = sbuf_rxd;
assign intr = scon[1] | scon [0];
 
//
//serial port control register
//
wire ren, tb8, rb8, ri;
assign ren = scon[4];
assign tb8 = scon[3];
assign rb8 = scon[2];
assign ri  = scon[0];
 
always @(posedge clk or posedge rst)
begin
  if (rst)
    scon <= #1 `OC8051_RST_SCON;
  else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
    scon <= #1 data_in;
  else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
    scon[wr_addr[2:0]] <= #1 bit_in;
  else if (tx_done)
    scon[1] <= #1 1'b1;
  else if (!rx_done) begin
    if (scon[7:6]==2'b00) begin
      scon[0] <= #1 1'b1;
    end else if ((sbuf_rxd_tmp[11]) | !(scon[5])) begin
      scon[0] <= #1 1'b1;
      scon[2] <= #1 sbuf_rxd_tmp[11];
    end else
      scon[2] <= #1 sbuf_rxd_tmp[11];
  end
end
 
//
//power control register
//
wire smod;
assign smod = pcon[7];
always @(posedge clk or posedge rst)
begin
  if (rst)
  begin
    pcon <= #1 `OC8051_RST_PCON;
  end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
    pcon <= #1 data_in;
end
 
 
//
//serial port buffer (transmit)
//
 
wire wr_sbuf;
assign wr_sbuf = (wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit);
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    txd      <= #1 1'b1;
    tr_count <= #1 4'd0;
    trans    <= #1 1'b0;
    sbuf_txd <= #1 11'h00;
    tx_done  <= #1 1'b0;
//
// start transmiting
//
  end else if (wr_sbuf) begin
    case (scon[7:6]) /* synopsys parallel_case */
      2'b00: begin  // mode 0
        sbuf_txd <= #1 {3'b001, data_in};
      end
      2'b01: begin // mode 1
        sbuf_txd <= #1 {2'b01, data_in, 1'b0};
      end
      default: begin  // mode 2 and mode 3
        sbuf_txd <= #1 {1'b1, tb8, data_in, 1'b0};
      end
    endcase
    trans    <= #1 1'b1;
    tr_count <= #1 4'd0;
    tx_done  <= #1 1'b0;
//
// transmiting
//
  end else if (trans & (scon[7:6] == 2'b00) & pres_ow) // mode 0
  begin
    if (~|sbuf_txd[10:1]) begin
      trans   <= #1 1'b0;
      tx_done <= #1 1'b1;
    end else begin
      {sbuf_txd, txd} <= #1 {1'b0, sbuf_txd};
      tx_done         <= #1 1'b0;
    end
  end else if (trans & (scon[7:6] != 2'b00) & shift_tr) begin // mode 1, 2, 3
    tr_count <= #1 tr_count + 4'd1;
    if (~|tr_count) begin
      if (~|sbuf_txd[10:0]) begin
        trans   <= #1 1'b0;
        tx_done <= #1 1'b1;
        txd <= #1 1'b1;
      end else begin
        {sbuf_txd, txd} <= #1 {1'b0, sbuf_txd};
        tx_done         <= #1 1'b0;
      end
    end
  end else if (!trans) begin
    txd     <= #1 1'b1;
    tx_done <= #1 1'b0;
  end
end
 
//
//
reg sc_clk_tr, smod_clk_tr;
always @(brate2 or t1_ow or t1_ow_buf or scon[7:6] or tclk)
begin
  if (scon[7:6]==8'b10) begin //mode 2
    sc_clk_tr = 1'b1;
  end else if (tclk) begin //
    sc_clk_tr = brate2;
  end else begin //
    sc_clk_tr = !t1_ow_buf & t1_ow;
  end
end
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    smod_clk_tr <= #1 1'b0;
    shift_tr    <= #1 1'b0;
  end else if (sc_clk_tr) begin
    if (smod) begin
      shift_tr <= #1 1'b1;
    end else begin
      shift_tr    <= #1  smod_clk_tr;
      smod_clk_tr <= #1 !smod_clk_tr;
    end
  end else begin
    shift_tr <= #1 1'b0;
  end
end
 
 
//
//serial port buffer (receive)
//
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    re_count     <= #1 4'd0;
    receive      <= #1 1'b0;
    sbuf_rxd     <= #1 8'h00;
    sbuf_rxd_tmp <= #1 12'd0;
    rx_done      <= #1 1'b1;
    rxd_r        <= #1 1'b1;
    rx_sam       <= #1 2'b00;
  end else if (!rx_done) begin
    receive <= #1 1'b0;
    rx_done <= #1 1'b1;
    sbuf_rxd <= #1 sbuf_rxd_tmp[10:3];
  end else if (receive & (scon[7:6]==2'b00) & pres_ow) begin //mode 0
    {sbuf_rxd_tmp, rx_done} <= #1 {rxd, sbuf_rxd_tmp};
  end else if (receive & (scon[7:6]!=2'b00) & shift_re) begin //mode 1, 2, 3
    re_count <= #1 re_count + 4'd1;
    case (re_count) /* synopsys full_case parallel_case */
      4'h7: rx_sam[0] <= #1 rxd;
      4'h8: rx_sam[1] <= #1 rxd;
      4'h9: begin
        {sbuf_rxd_tmp, rx_done} <= #1 {(rxd==rx_sam[0] ? rxd : rx_sam[1]), sbuf_rxd_tmp};
      end
    endcase
//
//start receiving
//
  end else if (scon[7:6]==2'b00) begin //start mode 0
    rx_done <= #1 1'b1;
    if (ren && !ri && !receive) begin
      receive      <= #1 1'b1;
      sbuf_rxd_tmp <= #1 10'h0ff;
    end
  end else if (ren & shift_re) begin
    rxd_r <= #1 rxd;
    rx_done <= #1 1'b1;
    re_count <= #1 4'h0;
    receive <= #1 (rxd_r & !rxd);
    sbuf_rxd_tmp <= #1 10'h1ff;
  end else if (!ren) begin
    rxd_r <= #1 rxd;
  end else
    rx_done <= #1 1'b1;
end
 
//
//
reg sc_clk_re, smod_clk_re;
always @(brate2 or t1_ow or t1_ow_buf or scon[7:6] or rclk)
begin
  if (scon[7:6]==8'b10) begin //mode 2
    sc_clk_re = 1'b1;
  end else if (rclk) begin //
    sc_clk_re = brate2;
  end else begin //
    sc_clk_re = !t1_ow_buf & t1_ow;
  end
end
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    smod_clk_re <= #1 1'b0;
    shift_re    <= #1 1'b0;
  end else if (sc_clk_re) begin
    if (smod) begin
      shift_re <= #1 1'b1;
    end else begin
      shift_re    <= #1  smod_clk_re;
      smod_clk_re <= #1 !smod_clk_re;
    end
  end else begin
    shift_re <= #1 1'b0;
  end
end
 
 
 
//
//
//
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    t1_ow_buf <= #1 1'b0;
  end else begin
    t1_ow_buf <= #1 t1_ow;
  end
end
 
 
 
endmodule
 

Line No.	Rev	Author	Line
1	82	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores serial interface ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// uart for 8051 core ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// Nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	179	simont	`// Revision 1.14 2003/04/29 11:25:42 simont`
48			`// prepared start of receiving if ren is not active.`
49			`//`
50	135	simont	`// Revision 1.13 2003/04/10 08:57:16 simont`
51			`// remove signal sbuf_txd [12:11]`
52			`//`
53	119	simont	`// Revision 1.12 2003/04/07 14:58:02 simont`
54			`// change sfr's interface.`
55			`//`
56	116	simont	`// Revision 1.11 2003/04/07 13:29:16 simont`
57			`// change uart to meet timing.`
58			`//`
59	115	simont	`// Revision 1.10 2003/01/13 14:14:41 simont`
60			`// replace some modules`
61			`//`
62	82	simont	`// Revision 1.9 2002/09/30 17:33:59 simont`
63			`// prepared header`
64			`//`
65			`//`
66
67			`// synopsys translate_off`
68			`include "oc8051_timescale.v"
69			`// synopsys translate_on`
70
71			`include "oc8051_defines.v"
72
73	115	simont	`module oc8051_uart (rst, clk,`
74			`bit_in, data_in,`
75	116	simont	`wr_addr,`
76	115	simont	`wr, wr_bit,`
77	116	simont	`rxd, txd,`
78	115	simont	`intr,`
79			`brate2, t1_ow, pres_ow,`
80	116	simont	`rclk, tclk,`
81			`//registers`
82			`scon, pcon, sbuf);`
83	82	simont
84	115	simont	`input rst,`
85			`clk,`
86			`bit_in,`
87			`wr,`
88			`rxd,`
89			`wr_bit,`
90			`t1_ow,`
91			`brate2,`
92			`pres_ow,`
93			`rclk,`
94			`tclk;`
95	116	simont	`input [7:0] data_in,`
96	115	simont	`wr_addr;`
97	82	simont
98	115	simont	`output txd,`
99	116	simont	`intr;`
100			`output [7:0] scon,`
101			`pcon,`
102			`sbuf;`
103	82	simont
104
105	115	simont	`reg t1_ow_buf;`
106	82	simont	`//`
107	116	simont	`reg [7:0] scon, pcon;`
108	82	simont
109
110	115	simont	`reg txd,`
111			`trans,`
112			`receive,`
113			`tx_done,`
114			`rx_done,`
115			`rxd_r,`
116			`shift_tr,`
117			`shift_re;`
118			`reg [1:0] rx_sam;`
119			`reg [3:0] tr_count,`
120			`re_count;`
121			`reg [7:0] sbuf_rxd;`
122			`reg [11:0] sbuf_rxd_tmp;`
123	119	simont	`reg [10:0] sbuf_txd;`
124	115	simont
125	116	simont	`assign sbuf = sbuf_rxd;`
126	82	simont	`assign intr = scon[1] \| scon [0];`
127
128			`//`
129			`//serial port control register`
130			`//`
131	115	simont	`wire ren, tb8, rb8, ri;`
132			`assign ren = scon[4];`
133			`assign tb8 = scon[3];`
134			`assign rb8 = scon[2];`
135			`assign ri = scon[0];`
136
137	82	simont	`always @(posedge clk or posedge rst)`
138			`begin`
139			`if (rst)`
140			scon <= #1 `OC8051_RST_SCON;
141			else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
142			`scon <= #1 data_in;`
143			else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
144			`scon[wr_addr[2:0]] <= #1 bit_in;`
145	115	simont	`else if (tx_done)`
146	82	simont	`scon[1] <= #1 1'b1;`
147	115	simont	`else if (!rx_done) begin`
148			`if (scon[7:6]==2'b00) begin`
149			`scon[0] <= #1 1'b1;`
150			`end else if ((sbuf_rxd_tmp[11]) \| !(scon[5])) begin`
151			`scon[0] <= #1 1'b1;`
152			`scon[2] <= #1 sbuf_rxd_tmp[11];`
153			`end else`
154			`scon[2] <= #1 sbuf_rxd_tmp[11];`
155			`end`
156			`end`
157
158			`//`
159			`//power control register`
160			`//`
161			`wire smod;`
162			`assign smod = pcon[7];`
163			`always @(posedge clk or posedge rst)`
164			`begin`
165			`if (rst)`
166			`begin`
167			pcon <= #1 `OC8051_RST_PCON;
168			end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
169			`pcon <= #1 data_in;`
170			`end`
171
172
173			`//`
174			`//serial port buffer (transmit)`
175			`//`
176
177			`wire wr_sbuf;`
178			assign wr_sbuf = (wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit);
179
180			`always @(posedge clk or posedge rst)`
181			`begin`
182			`if (rst) begin`
183			`txd <= #1 1'b1;`
184			`tr_count <= #1 4'd0;`
185			`trans <= #1 1'b0;`
186			`sbuf_txd <= #1 11'h00;`
187			`tx_done <= #1 1'b0;`
188			`//`
189			`// start transmiting`
190			`//`
191			`end else if (wr_sbuf) begin`
192	179	simont	`case (scon[7:6]) /* synopsys parallel_case */`
193	115	simont	`2'b00: begin // mode 0`
194			`sbuf_txd <= #1 {3'b001, data_in};`
195	82	simont	`end`
196	115	simont	`2'b01: begin // mode 1`
197			`sbuf_txd <= #1 {2'b01, data_in, 1'b0};`
198			`end`
199			`default: begin // mode 2 and mode 3`
200			`sbuf_txd <= #1 {1'b1, tb8, data_in, 1'b0};`
201			`end`
202	82	simont	`endcase`
203	115	simont	`trans <= #1 1'b1;`
204			`tr_count <= #1 4'd0;`
205			`tx_done <= #1 1'b0;`
206			`//`
207			`// transmiting`
208			`//`
209			`end else if (trans & (scon[7:6] == 2'b00) & pres_ow) // mode 0`
210			`begin`
211			`if (~\|sbuf_txd[10:1]) begin`
212			`trans <= #1 1'b0;`
213			`tx_done <= #1 1'b1;`
214			`end else begin`
215			`{sbuf_txd, txd} <= #1 {1'b0, sbuf_txd};`
216			`tx_done <= #1 1'b0;`
217			`end`
218			`end else if (trans & (scon[7:6] != 2'b00) & shift_tr) begin // mode 1, 2, 3`
219			`tr_count <= #1 tr_count + 4'd1;`
220			`if (~\|tr_count) begin`
221			`if (~\|sbuf_txd[10:0]) begin`
222			`trans <= #1 1'b0;`
223			`tx_done <= #1 1'b1;`
224			`txd <= #1 1'b1;`
225			`end else begin`
226			`{sbuf_txd, txd} <= #1 {1'b0, sbuf_txd};`
227			`tx_done <= #1 1'b0;`
228			`end`
229			`end`
230			`end else if (!trans) begin`
231			`txd <= #1 1'b1;`
232			`tx_done <= #1 1'b0;`
233	82	simont	`end`
234			`end`
235
236			`//`
237			`//`
238	115	simont	`reg sc_clk_tr, smod_clk_tr;`
239			`always @(brate2 or t1_ow or t1_ow_buf or scon[7:6] or tclk)`
240			`begin`
241			`if (scon[7:6]==8'b10) begin //mode 2`
242			`sc_clk_tr = 1'b1;`
243			`end else if (tclk) begin //`
244			`sc_clk_tr = brate2;`
245			`end else begin //`
246			`sc_clk_tr = !t1_ow_buf & t1_ow;`
247			`end`
248			`end`
249
250	82	simont	`always @(posedge clk or posedge rst)`
251			`begin`
252			`if (rst) begin`
253	115	simont	`smod_clk_tr <= #1 1'b0;`
254			`shift_tr <= #1 1'b0;`
255			`end else if (sc_clk_tr) begin`
256			`if (smod) begin`
257			`shift_tr <= #1 1'b1;`
258			`end else begin`
259			`shift_tr <= #1 smod_clk_tr;`
260			`smod_clk_tr <= #1 !smod_clk_tr;`
261			`end`
262			`end else begin`
263			`shift_tr <= #1 1'b0;`
264			`end`
265	82	simont	`end`
266
267
268			`//`
269	115	simont	`//serial port buffer (receive)`
270	82	simont	`//`
271			`always @(posedge clk or posedge rst)`
272			`begin`
273	115	simont	`if (rst) begin`
274			`re_count <= #1 4'd0;`
275			`receive <= #1 1'b0;`
276			`sbuf_rxd <= #1 8'h00;`
277			`sbuf_rxd_tmp <= #1 12'd0;`
278			`rx_done <= #1 1'b1;`
279			`rxd_r <= #1 1'b1;`
280			`rx_sam <= #1 2'b00;`
281			`end else if (!rx_done) begin`
282			`receive <= #1 1'b0;`
283			`rx_done <= #1 1'b1;`
284	116	simont	`sbuf_rxd <= #1 sbuf_rxd_tmp[10:3];`
285	115	simont	`end else if (receive & (scon[7:6]==2'b00) & pres_ow) begin //mode 0`
286			`{sbuf_rxd_tmp, rx_done} <= #1 {rxd, sbuf_rxd_tmp};`
287			`end else if (receive & (scon[7:6]!=2'b00) & shift_re) begin //mode 1, 2, 3`
288			`re_count <= #1 re_count + 4'd1;`
289	179	simont	`case (re_count) /* synopsys full_case parallel_case */`
290	115	simont	`4'h7: rx_sam[0] <= #1 rxd;`
291			`4'h8: rx_sam[1] <= #1 rxd;`
292			`4'h9: begin`
293			`{sbuf_rxd_tmp, rx_done} <= #1 {(rxd==rx_sam[0] ? rxd : rx_sam[1]), sbuf_rxd_tmp};`
294			`end`
295			`endcase`
296			`//`
297			`//start receiving`
298			`//`
299			`end else if (scon[7:6]==2'b00) begin //start mode 0`
300			`rx_done <= #1 1'b1;`
301			`if (ren && !ri && !receive) begin`
302			`receive <= #1 1'b1;`
303			`sbuf_rxd_tmp <= #1 10'h0ff;`
304			`end`
305			`end else if (ren & shift_re) begin`
306			`rxd_r <= #1 rxd;`
307			`rx_done <= #1 1'b1;`
308			`re_count <= #1 4'h0;`
309			`receive <= #1 (rxd_r & !rxd);`
310			`sbuf_rxd_tmp <= #1 10'h1ff;`
311	135	simont	`end else if (!ren) begin`
312			`rxd_r <= #1 rxd;`
313	115	simont	`end else`
314			`rx_done <= #1 1'b1;`
315	82	simont	`end`
316
317			`//`
318			`//`
319	115	simont	`reg sc_clk_re, smod_clk_re;`
320			`always @(brate2 or t1_ow or t1_ow_buf or scon[7:6] or rclk)`
321			`begin`
322			`if (scon[7:6]==8'b10) begin //mode 2`
323			`sc_clk_re = 1'b1;`
324			`end else if (rclk) begin //`
325			`sc_clk_re = brate2;`
326			`end else begin //`
327			`sc_clk_re = !t1_ow_buf & t1_ow;`
328			`end`
329			`end`
330
331	82	simont	`always @(posedge clk or posedge rst)`
332			`begin`
333			`if (rst) begin`
334	115	simont	`smod_clk_re <= #1 1'b0;`
335			`shift_re <= #1 1'b0;`
336			`end else if (sc_clk_re) begin`
337			`if (smod) begin`
338			`shift_re <= #1 1'b1;`
339			`end else begin`
340			`shift_re <= #1 smod_clk_re;`
341			`smod_clk_re <= #1 !smod_clk_re;`
342			`end`
343			`end else begin`
344			`shift_re <= #1 1'b0;`
345			`end`
346			`end`
347
348
349	82	simont
350			`//`
351			`//`
352			`//`
353
354			`always @(posedge clk or posedge rst)`
355			`begin`
356			`if (rst) begin`
357			`t1_ow_buf <= #1 1'b0;`
358			`end else begin`
359			`t1_ow_buf <= #1 t1_ow;`
360			`end`
361			`end`
362
363	115	simont
364	82	simont
365			`endmodule`
366

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