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1 41 sybreon
// $Id: aeMB_ibuf.v,v 1.1 2007-11-02 03:25:40 sybreon Exp $
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//
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// AEMB INSTRUCTION BUFFER
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// 
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// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
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//  
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public License
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// as published by the Free Software Foundation; either version 2.1 of
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// the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful, but
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// WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//  
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
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// USA
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//
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// $Log: not supported by cvs2svn $
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module aeMB_ibuf (/*AUTOARG*/
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   // Outputs
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   rIMM, rRA, rRD, rRB, rALT, rOPC, rSIMM, iwb_stb_o,
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   // Inputs
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   rBRA, rXCE, iwb_dat_i, iwb_ack_i, gclk, grst, gena
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   );
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   // INTERNAL
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   output [15:0] rIMM;
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   output [4:0]  rRA, rRD, rRB;
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   output [10:0] rALT;
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   output [5:0]  rOPC;
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   output [31:0] rSIMM;
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   input         rBRA;
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   input [1:0]    rXCE;
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   // INST WISHBONE
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   output        iwb_stb_o;
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   input [31:0]  iwb_dat_i;
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   input         iwb_ack_i;
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   // SYSTEM
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   input         gclk, grst, gena;
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   reg [15:0]     rIMM;
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   reg [4:0]      rRA, rRD;
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   reg [5:0]      rOPC;
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   // FIXME: Endian
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   wire [31:0]    wIDAT = iwb_dat_i;
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   assign        {rRB, rALT} = rIMM;
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   // TODO: Assign to FIFO not full.
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   assign       iwb_stb_o = 1'b1;
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   reg [31:0]    rSIMM, xSIMM;
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   wire [31:0]   wSIMM = (fIMM) ? {rIMM, wIDAT[15:0]} : { {(16){wIDAT[15]}}, wIDAT[15:0]}; // TODO: Factor
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   wire         fIMM = (rOPC == 6'o54);
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   reg [31:0]    xIREG;
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   // DELAY SLOT
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   always @(/*AUTOSENSE*/rBRA or wIDAT)
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     if (rBRA) begin
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        xIREG <= 32'h88000000;
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        /*AUTORESET*/
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     end else begin
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        xIREG <= wIDAT; // FIXME: Simplify
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        //xSIMM <= wSIMM;
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     end
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   always @(/*AUTOSENSE*/fIMM or rBRA or rIMM or xIREG)
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     if (rBRA) begin
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        /*AUTORESET*/
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        // Beginning of autoreset for uninitialized flops
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        xSIMM <= 32'h0;
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        // End of automatics
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     end else begin
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        //xIREG <= wIDAT; // FIXME: Simplify
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        xSIMM <= (fIMM) ? {rIMM, xIREG[15:0]} : { {(16){xIREG[15]}}, xIREG[15:0]}; // TODO: Factor
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     end
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   // Synchronous
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   always @(posedge gclk)
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     if (grst) begin
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        /*AUTORESET*/
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        // Beginning of autoreset for uninitialized flops
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        rIMM <= 16'h0;
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        rOPC <= 6'h0;
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        rRA <= 5'h0;
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        rRD <= 5'h0;
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        rSIMM <= 32'h0;
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        // End of automatics
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     end else if (gena) begin
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        {rOPC, rRD, rRA, rIMM} <= #1 xIREG;
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        rSIMM <= #1 xSIMM;
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     end
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endmodule // aeMB_ibuf

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