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[/] [embedded_risc/] [trunk/] [Verilog/] [MEM.V] - Blame information for rev 27

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1 26 hosseinami
/****************************************************************************************
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 MODULE:                Sub Level Memory Block
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 FILE NAME:     mem.v
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 VERSION:       1.0
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 DATE:          September 28th, 2001
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 AUTHOR:                Hossein Amidi
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 COMPANY:       California Unique Electrical Co.
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 CODE TYPE:     Behavioral Level
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 Instantiations:
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 DESCRIPTION:
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 Sub Level Behavioral Memory Block, It uses 12 Address and 16 Data Line
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 the memory size would be 2 ^ 12 = 4096 * 16-bit wide = 65536 bits.
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 65536 bits / 8 = 8192 Byte ->  8K Byte of memory.
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 This memory is organized as 4096 locations of 16-bit (2 Byte) wide.
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 Hossein Amidi
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 (C) September 2001
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 California Unique Electric
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***************************************************************************************/
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`timescale 1ns / 1ps
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module MEM (// Input
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                                DataIn,
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                                Address,
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                                MemReq,
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                                RdWrBar,
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                                clock,
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                                // Output
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                                DataOut
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                                );
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// Parameter
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parameter words = 4096;
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parameter AccessTime = 0;
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parameter DataWidth = 32;
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parameter AddrWidth = 24;
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// Input
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input [DataWidth - 1 : 0] DataIn;
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input [AddrWidth - 1 : 0] Address;
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input MemReq;
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input RdWrBar;
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input clock;
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// Output
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output [DataWidth - 1 : 0] DataOut;
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// Internal Memory Declerations
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// 4096 x 16 bit wide
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reg [DataWidth - 1 : 0] MEM_Data [0:words-1];
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// Signal Declerations
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wire [DataWidth - 1 : 0] Data;
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// Assignments
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// Read Cycle
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assign Data = (MemReq && RdWrBar)? MEM_Data [Address]:32'hz;
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assign #AccessTime DataOut = Data; // Delay in a continuous assign
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// Write Cycle
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always @(posedge clock)
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begin
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        if(MemReq && ~RdWrBar)
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                MEM_Data [Address] <= DataIn;
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end
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endmodule

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