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[/] [embedded_risc/] [trunk/] [Verilog/] [PC.V] - Blame information for rev 27

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/****************************************************************************************
 MODULE:                Sub Level Program Counter Block
 
 FILE NAME:     pc.v
 VERSION:       1.0
 DATE:          September 28th, 2001
 AUTHOR:                Hossein Amidi
 COMPANY:       California Unique Electrical Co.
 CODE TYPE:     Register Transfer Level
 
 Instantiations:
 
 DESCRIPTION:
 Sub Level RTL Program Counter block
 
 Hossein Amidi
 (C) September 2001
 California Unique Electric
 
***************************************************************************************/
 
`timescale 1ns / 1ps
 
module PC (     // Input
                                clock,
                                reset,
                                PCInEn,
                                PCDataIn,
                                // Output
                                PCDataOut
                                );
 
// Parameter
parameter AddrWidth = 24;
 
// Inputs
input clock;
input reset;
input PCInEn;
input [AddrWidth - 1 : 0] PCDataIn;
 
// Outputs
output [AddrWidth - 1 : 0] PCDataOut;
 
// Signal Declerations
reg [AddrWidth - 1 : 0] PCDataOut;
 
 
// Main Block
always @ (posedge reset or negedge clock)
begin
        if(reset == 1'b1)
                PCDataOut <= 24'h000;
        else
        if (PCInEn == 1'b1)
        PCDataOut <= PCDataIn;
        else
        PCDataOut <= PCDataOut;
end
endmodule

Line No.	Rev	Author	Line
1	26	hosseinami	`/****************************************************************************************`
2			`MODULE: Sub Level Program Counter Block`
3
4			`FILE NAME: pc.v`
5			`VERSION: 1.0`
6			`DATE: September 28th, 2001`
7			`AUTHOR: Hossein Amidi`
8			`COMPANY: California Unique Electrical Co.`
9			`CODE TYPE: Register Transfer Level`
10
11			`Instantiations:`
12
13			`DESCRIPTION:`
14			`Sub Level RTL Program Counter block`
15
16			`Hossein Amidi`
17			`(C) September 2001`
18			`California Unique Electric`
19
20			`***************************************************************************************/`
21
22			`timescale 1ns / 1ps
23
24			`module PC ( // Input`
25			`clock,`
26			`reset,`
27			`PCInEn,`
28			`PCDataIn,`
29			`// Output`
30			`PCDataOut`
31			`);`
32
33			`// Parameter`
34			`parameter AddrWidth = 24;`
35
36			`// Inputs`
37			`input clock;`
38			`input reset;`
39			`input PCInEn;`
40			`input [AddrWidth - 1 : 0] PCDataIn;`
41
42			`// Outputs`
43			`output [AddrWidth - 1 : 0] PCDataOut;`
44
45			`// Signal Declerations`
46			`reg [AddrWidth - 1 : 0] PCDataOut;`
47
48
49			`// Main Block`
50			`always @ (posedge reset or negedge clock)`
51			`begin`
52			`if(reset == 1'b1)`
53			`PCDataOut <= 24'h000;`
54			`else`
55			`if (PCInEn == 1'b1)`
56			`PCDataOut <= PCDataIn;`
57			`else`
58			`PCDataOut <= PCDataOut;`
59			`end`
60			`endmodule`

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[/] [embedded_risc/] [trunk/] [Verilog/] [PC.V] - Blame information for rev 27