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[/] [embedded_risc/] [trunk/] [Verilog/] [dma_cntrl.v] - Blame information for rev 27

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/*********************************************************
 MODULE:                Sub Level Direct Memory Access Controller
 
 FILE NAME:     dma_cntrl.v
 VERSION:       1.0
 DATE:          May 7th, 2002
 AUTHOR:                Hossein Amidi
 COMPANY:
 CODE TYPE:     Register Transfer Level
 
 DESCRIPTION:   This module is the top level RTL code of DMA Controller verilog code.
 
 It will instantiate the following blocks in the ASIC:
 
 1)     DMA FIFO
 2)     DMA Internal Registers
 
 Hossein Amidi
 (C) April 2002
 
*********************************************************/
 
// DEFINES
`timescale 1ns / 10ps
 
// TOP MODULE
module dma_cntrl(       // Inputs
                                                reset,
                                                clk0,
                                                dma_host_addr,
                                                dma_host_cmd,
                                                dma_host_datain,
                                                dma_bus_grant,
                                                dma_rd_datain,
                                                dma_wr_datain,
                                                // Output
                                                dma_host_dataout,
                                                dma_irq,
                                                dma_bus_req,
                                                dma_rd_addr,
                                                dma_wr_addr,
                                                dma_wr_dataout,
                                                dma_rd_cmd,
                                                dma_busy,
                                                uart_cs,
                                                uart_rd,
                                                uart_wr,
                                                dma_rd_dataout
                                                );
 
// Parameter
`include "parameter.v"
 
// Inputs
input reset;
input clk0;
input [padd_size - 1 : 0]dma_host_addr;
input [cmd_size  - 1 : 0]dma_host_cmd;
input [data_size - 1 : 0]dma_host_datain;
input dma_bus_grant;
input [fifo_size - 1 : 0]dma_rd_datain;
input [fifo_size - 1 : 0]dma_wr_datain;
 
// Outputs
output [data_size - 1 : 0]dma_host_dataout;
output dma_irq;
output dma_bus_req;
output [padd_size - 1 : 0]dma_rd_addr;
output [padd_size - 1 : 0]dma_wr_addr;
output [fifo_size - 1 : 0]dma_wr_dataout;
output [cmd_size  - 1 : 0]dma_rd_cmd;
output dma_busy;
output uart_cs;
output uart_rd;
output uart_wr;
output [fifo_size - 1 : 0]dma_rd_dataout;
 
// Signal Declarations
wire reset;
wire clk0;
wire [padd_size - 1 : 0]dma_host_addr;
wire [cmd_size  - 1 : 0]dma_host_cmd;
wire [data_size - 1 : 0]dma_host_datain;
wire dma_bus_grant;
wire [fifo_size - 1 : 0]dma_rd_datain;
wire [fifo_size - 1 : 0]dma_wr_datain;
 
wire [data_size - 1 : 0]dma_host_dataout;
wire dma_irq;
wire dma_bus_req;
reg [padd_size - 1 : 0]dma_rd_addr;
reg [padd_size - 1 : 0]dma_wr_addr;
reg [fifo_size - 1 : 0]dma_wr_dataout;
reg [cmd_size  - 1 : 0]dma_rd_cmd;
reg [fifo_size - 1 : 0]dma_rd_dataout;
wire [fifo_size - 1 : 0]wdma_rd_dataout;
wire dma_busy;
 
reg uart_cs;
reg uart_rd;
reg uart_wr;
 
// Internal wire and reg Signals
wire done;
wire busy;
wire reop;
wire weop;
wire len;
 
wire byte;
wire hw;
wire word;
wire go;
wire i_en;
wire reen;
wire ween;
wire leen;
wire rcon;
wire wcon;
 
reg fifo_rd;
reg fifo_wr;
 
reg [dma_fifo_depth - 1 : 0]dma_wr_addr_cnt;
reg [dma_fifo_depth - 1 : 0]dma_rd_addr_cnt;
 
wire [dma_fifo_depth - 1 : 0]wdma_wr_addr_cnt;
wire [dma_fifo_depth - 1 : 0]wdma_rd_addr_cnt;
 
 
wire wr_inc1;
wire wr_inc2;
wire wr_inc4;
 
wire rd_inc1;
wire rd_inc2;
wire rd_inc4;
 
wire fifo_wr_enb;
wire fifo_rd_enb;
 
wire [fifo_size - 1 : 0]fifo_in_data;
wire [fifo_size - 1 : 0]fifo_out_data;
 
reg fifo_sel_in;
reg fifo_sel_out;
 
 
// Assignment statments
assign dma_irq = done;
assign dma_bus_req = go;
assign dma_busy = busy;
assign wdma_wr_addr_cnt = dma_wr_addr_cnt;
assign wdma_rd_addr_cnt = dma_rd_addr_cnt;
 
// Muxing the fifo for bidirection functionality
assign fifo_in_data = fifo_sel_in ? dma_wr_datain : dma_rd_datain;
 
/********************************** FIFO Instantiation ******************************/
 
dma_fifo dma_fifo0 (// Input
                                                        .clk(clk0),
                                                        .sinit(reset),
                                                        .din(fifo_in_data),
                                                        .wr_en(fifo_wr),
                                                        .rd_en(fifo_rd),
                                                        // Output
                                                        .dout(fifo_out_data),
                                                        .full(),
                                                        .empty()
                                                        );
 
 
dma_internal_reg dma_internal_reg0(// Input
                                                                                        .reset(reset),
                                                                                        .clk0(clk0),
                                                                                        .dma_host_cmd(dma_host_cmd),
                                                                                        .dma_host_addr(dma_host_addr),
                                                                                        .dma_host_datain(dma_host_datain),
                                                                                        .dma_rd_addr_cnt(wdma_rd_addr_cnt),
                                                                                        .dma_wr_addr_cnt(wdma_wr_addr_cnt),
                                                                                        .fifo_rd(fifo_rd),
                                                                                        .fifo_wr(fifo_wr),
                                                                                        // Output
                                                                                        .dma_host_dataout(dma_host_dataout),
                                                                                        .done(done),
                                                                                        .go(go),
                                                                                        .busy(busy),
                                                                                        .fifo_wr_enb(fifo_wr_enb),
                                                                                        .fifo_rd_enb(fifo_rd_enb),
                                                                                        .wr_inc1(wr_inc1),
                                                                                        .wr_inc2(wr_inc2),
                                                                                        .wr_inc4(wr_in4),
                                                                                        .rd_inc1(rd_inc1),
                                                                                        .rd_inc2(rd_inc2),
                                                                                        .rd_inc4(rd_inc4)
                                                                                        );
 
 
// Set the Demultiplexer for the FIFO output port
always @(reset or fifo_sel_out or dma_bus_grant or fifo_out_data)
begin
        if(reset == 1'b1)
        begin
                dma_rd_dataout <= 8'h0;
                dma_wr_dataout <= 8'h0;
        end
        else
        if((dma_bus_grant == 1'b1) && (fifo_sel_out == 1'b1))
                dma_wr_dataout <= fifo_out_data;
        else
        if((dma_bus_grant == 1'b0) && (fifo_sel_out == 1'b0))
                        dma_rd_dataout <= fifo_out_data;
end
 
 
// Increment the DMA Write Slave Address
always @(posedge reset or posedge clk0)
begin
        if(reset == 1'b1)
                dma_wr_addr_cnt <= 32'h0;
        else
        if (wr_inc1 == 1'b1)
                dma_wr_addr_cnt <= dma_wr_addr_cnt + 1;
        else
        if (wr_inc2 == 1'b1)
                dma_wr_addr_cnt <= dma_wr_addr_cnt + 2;
        else
        if (wr_inc4 == 1'b1)
                dma_wr_addr_cnt <= dma_wr_addr_cnt + 4;
        else
                dma_wr_addr_cnt <= dma_wr_addr_cnt;
end
 
 
// Increment the DMA Read Slave Address
always @(posedge reset or posedge clk0)
begin
        if(reset == 1'b1)
                dma_rd_addr_cnt <= 32'h0;
        else
        if (rd_inc1 == 1'b1)
                dma_rd_addr_cnt <= dma_rd_addr_cnt + 1;
        else
        if (rd_inc2 == 1'b1)
                dma_rd_addr_cnt <= dma_rd_addr_cnt + 2;
        else
        if (rd_inc4 == 1'b1)
                dma_rd_addr_cnt <= dma_rd_addr_cnt + 4;
        else
                dma_rd_addr_cnt <= dma_rd_addr_cnt;
end
 
 
// Generating FIFO read and write enable signals
always @(posedge reset or posedge clk0)
begin
        if(reset == 1'b1)
        begin
                fifo_wr <= 1'b0;
                fifo_rd <= 1'b0;
                fifo_sel_in  <= 1'b0;
                fifo_sel_out <= 1'b0;
        end
        else
        begin
                if((fifo_wr_enb == 1'b1) && (dma_bus_req == 1'b1))
                begin
                        fifo_sel_in <= 1'b1;
                        fifo_wr <= 1'b1;
                end
                else
                if((fifo_wr_enb == 1'b1) && (dma_bus_req == 1'b0))
                begin
                        fifo_sel_in <= 1'b0;
                        fifo_wr <= 1'b1;
                end
                else
                begin
                        fifo_sel_in <= 1'b0;
                        fifo_wr <= 1'b0;
                end
 
                if((fifo_rd_enb == 1'b1) && (dma_bus_req == 1'b1))
                begin
                        fifo_sel_out <= 1'b0;
                        fifo_rd <= 1'b1;
                end
                else
                if((fifo_rd_enb == 1'b1) && (dma_bus_req == 1'b0))
                begin
                        fifo_sel_out <= 1'b1;
                        fifo_rd <= 1'b1;
                end
                else
                begin
                        fifo_sel_out <= 1'b0;
                        fifo_rd <= 1'b0;
                end
        end
end
 
 
always @(posedge reset or posedge clk0)
begin
        if(reset == 1'b1)
        begin
                dma_wr_addr <= 24'h0;
                dma_rd_addr <= 24'h0;
                dma_rd_cmd <= 3'h0;
                uart_cs <= 1'b0;
                uart_rd <= 1'b0;
                uart_wr <= 1'b0;
        end
        else
        begin
                dma_wr_addr <= dma_wr_addr_cnt;
                if(ween == 1'b1)
                begin
                        uart_cs <= 1'b1;
                        uart_wr <= 1'b1;
                        dma_rd_cmd <= 3'b010;
                        dma_wr_addr <= dma_wr_addr_cnt;
                end
                else
                if(reen == 1'b1)
                begin
                        uart_cs <= 1'b1;
                        uart_rd <= 1'b1;
                        dma_rd_cmd <= 3'b001;
                        dma_rd_addr <= dma_rd_addr_cnt;
                end
        end
end
 
endmodule

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[/] [embedded_risc/] [trunk/] [Verilog/] [dma_cntrl.v] - Blame information for rev 27

Line No.	Rev	Author	Line
1	26	hosseinami	`/*********************************************************`
2			`MODULE: Sub Level Direct Memory Access Controller`
3
4			`FILE NAME: dma_cntrl.v`
5			`VERSION: 1.0`
6			`DATE: May 7th, 2002`
7			`AUTHOR: Hossein Amidi`
8			`COMPANY:`
9			`CODE TYPE: Register Transfer Level`
10
11			`DESCRIPTION: This module is the top level RTL code of DMA Controller verilog code.`
12
13			`It will instantiate the following blocks in the ASIC:`
14
15			`1) DMA FIFO`
16			`2) DMA Internal Registers`
17
18			`Hossein Amidi`
19			`(C) April 2002`
20
21			`*********************************************************/`
22
23			`// DEFINES`
24			`timescale 1ns / 10ps
25
26			`// TOP MODULE`
27			`module dma_cntrl( // Inputs`
28			`reset,`
29			`clk0,`
30			`dma_host_addr,`
31			`dma_host_cmd,`
32			`dma_host_datain,`
33			`dma_bus_grant,`
34			`dma_rd_datain,`
35			`dma_wr_datain,`
36			`// Output`
37			`dma_host_dataout,`
38			`dma_irq,`
39			`dma_bus_req,`
40			`dma_rd_addr,`
41			`dma_wr_addr,`
42			`dma_wr_dataout,`
43			`dma_rd_cmd,`
44			`dma_busy,`
45			`uart_cs,`
46			`uart_rd,`
47			`uart_wr,`
48			`dma_rd_dataout`
49			`);`
50
51			`// Parameter`
52			`include "parameter.v"
53
54			`// Inputs`
55			`input reset;`
56			`input clk0;`
57			`input [padd_size - 1 : 0]dma_host_addr;`
58			`input [cmd_size - 1 : 0]dma_host_cmd;`
59			`input [data_size - 1 : 0]dma_host_datain;`
60			`input dma_bus_grant;`
61			`input [fifo_size - 1 : 0]dma_rd_datain;`
62			`input [fifo_size - 1 : 0]dma_wr_datain;`
63
64			`// Outputs`
65			`output [data_size - 1 : 0]dma_host_dataout;`
66			`output dma_irq;`
67			`output dma_bus_req;`
68			`output [padd_size - 1 : 0]dma_rd_addr;`
69			`output [padd_size - 1 : 0]dma_wr_addr;`
70			`output [fifo_size - 1 : 0]dma_wr_dataout;`
71			`output [cmd_size - 1 : 0]dma_rd_cmd;`
72			`output dma_busy;`
73			`output uart_cs;`
74			`output uart_rd;`
75			`output uart_wr;`
76			`output [fifo_size - 1 : 0]dma_rd_dataout;`
77
78			`// Signal Declarations`
79			`wire reset;`
80			`wire clk0;`
81			`wire [padd_size - 1 : 0]dma_host_addr;`
82			`wire [cmd_size - 1 : 0]dma_host_cmd;`
83			`wire [data_size - 1 : 0]dma_host_datain;`
84			`wire dma_bus_grant;`
85			`wire [fifo_size - 1 : 0]dma_rd_datain;`
86			`wire [fifo_size - 1 : 0]dma_wr_datain;`
87
88			`wire [data_size - 1 : 0]dma_host_dataout;`
89			`wire dma_irq;`
90			`wire dma_bus_req;`
91			`reg [padd_size - 1 : 0]dma_rd_addr;`
92			`reg [padd_size - 1 : 0]dma_wr_addr;`
93			`reg [fifo_size - 1 : 0]dma_wr_dataout;`
94			`reg [cmd_size - 1 : 0]dma_rd_cmd;`
95			`reg [fifo_size - 1 : 0]dma_rd_dataout;`
96			`wire [fifo_size - 1 : 0]wdma_rd_dataout;`
97			`wire dma_busy;`
98
99			`reg uart_cs;`
100			`reg uart_rd;`
101			`reg uart_wr;`
102
103			`// Internal wire and reg Signals`
104			`wire done;`
105			`wire busy;`
106			`wire reop;`
107			`wire weop;`
108			`wire len;`
109
110			`wire byte;`
111			`wire hw;`
112			`wire word;`
113			`wire go;`
114			`wire i_en;`
115			`wire reen;`
116			`wire ween;`
117			`wire leen;`
118			`wire rcon;`
119			`wire wcon;`
120
121			`reg fifo_rd;`
122			`reg fifo_wr;`
123
124			`reg [dma_fifo_depth - 1 : 0]dma_wr_addr_cnt;`
125			`reg [dma_fifo_depth - 1 : 0]dma_rd_addr_cnt;`
126
127			`wire [dma_fifo_depth - 1 : 0]wdma_wr_addr_cnt;`
128			`wire [dma_fifo_depth - 1 : 0]wdma_rd_addr_cnt;`
129
130
131			`wire wr_inc1;`
132			`wire wr_inc2;`
133			`wire wr_inc4;`
134
135			`wire rd_inc1;`
136			`wire rd_inc2;`
137			`wire rd_inc4;`
138
139			`wire fifo_wr_enb;`
140			`wire fifo_rd_enb;`
141
142			`wire [fifo_size - 1 : 0]fifo_in_data;`
143			`wire [fifo_size - 1 : 0]fifo_out_data;`
144
145			`reg fifo_sel_in;`
146			`reg fifo_sel_out;`
147
148
149			`// Assignment statments`
150			`assign dma_irq = done;`
151			`assign dma_bus_req = go;`
152			`assign dma_busy = busy;`
153			`assign wdma_wr_addr_cnt = dma_wr_addr_cnt;`
154			`assign wdma_rd_addr_cnt = dma_rd_addr_cnt;`
155
156			`// Muxing the fifo for bidirection functionality`
157			`assign fifo_in_data = fifo_sel_in ? dma_wr_datain : dma_rd_datain;`
158
159			`/******************************** FIFO Instantiation ****************************/`
160
161			`dma_fifo dma_fifo0 (// Input`
162			`.clk(clk0),`
163			`.sinit(reset),`
164			`.din(fifo_in_data),`
165			`.wr_en(fifo_wr),`
166			`.rd_en(fifo_rd),`
167			`// Output`
168			`.dout(fifo_out_data),`
169			`.full(),`
170			`.empty()`
171			`);`
172
173
174			`dma_internal_reg dma_internal_reg0(// Input`
175			`.reset(reset),`
176			`.clk0(clk0),`
177			`.dma_host_cmd(dma_host_cmd),`
178			`.dma_host_addr(dma_host_addr),`
179			`.dma_host_datain(dma_host_datain),`
180			`.dma_rd_addr_cnt(wdma_rd_addr_cnt),`
181			`.dma_wr_addr_cnt(wdma_wr_addr_cnt),`
182			`.fifo_rd(fifo_rd),`
183			`.fifo_wr(fifo_wr),`
184			`// Output`
185			`.dma_host_dataout(dma_host_dataout),`
186			`.done(done),`
187			`.go(go),`
188			`.busy(busy),`
189			`.fifo_wr_enb(fifo_wr_enb),`
190			`.fifo_rd_enb(fifo_rd_enb),`
191			`.wr_inc1(wr_inc1),`
192			`.wr_inc2(wr_inc2),`
193			`.wr_inc4(wr_in4),`
194			`.rd_inc1(rd_inc1),`
195			`.rd_inc2(rd_inc2),`
196			`.rd_inc4(rd_inc4)`
197			`);`
198
199
200			`// Set the Demultiplexer for the FIFO output port`
201			`always @(reset or fifo_sel_out or dma_bus_grant or fifo_out_data)`
202			`begin`
203			`if(reset == 1'b1)`
204			`begin`
205			`dma_rd_dataout <= 8'h0;`
206			`dma_wr_dataout <= 8'h0;`
207			`end`
208			`else`
209			`if((dma_bus_grant == 1'b1) && (fifo_sel_out == 1'b1))`
210			`dma_wr_dataout <= fifo_out_data;`
211			`else`
212			`if((dma_bus_grant == 1'b0) && (fifo_sel_out == 1'b0))`
213			`dma_rd_dataout <= fifo_out_data;`
214			`end`
215
216
217			`// Increment the DMA Write Slave Address`
218			`always @(posedge reset or posedge clk0)`
219			`begin`
220			`if(reset == 1'b1)`
221			`dma_wr_addr_cnt <= 32'h0;`
222			`else`
223			`if (wr_inc1 == 1'b1)`
224			`dma_wr_addr_cnt <= dma_wr_addr_cnt + 1;`
225			`else`
226			`if (wr_inc2 == 1'b1)`
227			`dma_wr_addr_cnt <= dma_wr_addr_cnt + 2;`
228			`else`
229			`if (wr_inc4 == 1'b1)`
230			`dma_wr_addr_cnt <= dma_wr_addr_cnt + 4;`
231			`else`
232			`dma_wr_addr_cnt <= dma_wr_addr_cnt;`
233			`end`
234
235
236			`// Increment the DMA Read Slave Address`
237			`always @(posedge reset or posedge clk0)`
238			`begin`
239			`if(reset == 1'b1)`
240			`dma_rd_addr_cnt <= 32'h0;`
241			`else`
242			`if (rd_inc1 == 1'b1)`
243			`dma_rd_addr_cnt <= dma_rd_addr_cnt + 1;`
244			`else`
245			`if (rd_inc2 == 1'b1)`
246			`dma_rd_addr_cnt <= dma_rd_addr_cnt + 2;`
247			`else`
248			`if (rd_inc4 == 1'b1)`
249			`dma_rd_addr_cnt <= dma_rd_addr_cnt + 4;`
250			`else`
251			`dma_rd_addr_cnt <= dma_rd_addr_cnt;`
252			`end`
253
254
255			`// Generating FIFO read and write enable signals`
256			`always @(posedge reset or posedge clk0)`
257			`begin`
258			`if(reset == 1'b1)`
259			`begin`
260			`fifo_wr <= 1'b0;`
261			`fifo_rd <= 1'b0;`
262			`fifo_sel_in <= 1'b0;`
263			`fifo_sel_out <= 1'b0;`
264			`end`
265			`else`
266			`begin`
267			`if((fifo_wr_enb == 1'b1) && (dma_bus_req == 1'b1))`
268			`begin`
269			`fifo_sel_in <= 1'b1;`
270			`fifo_wr <= 1'b1;`
271			`end`
272			`else`
273			`if((fifo_wr_enb == 1'b1) && (dma_bus_req == 1'b0))`
274			`begin`
275			`fifo_sel_in <= 1'b0;`
276			`fifo_wr <= 1'b1;`
277			`end`
278			`else`
279			`begin`
280			`fifo_sel_in <= 1'b0;`
281			`fifo_wr <= 1'b0;`
282			`end`
283
284			`if((fifo_rd_enb == 1'b1) && (dma_bus_req == 1'b1))`
285			`begin`
286			`fifo_sel_out <= 1'b0;`
287			`fifo_rd <= 1'b1;`
288			`end`
289			`else`
290			`if((fifo_rd_enb == 1'b1) && (dma_bus_req == 1'b0))`
291			`begin`
292			`fifo_sel_out <= 1'b1;`
293			`fifo_rd <= 1'b1;`
294			`end`
295			`else`
296			`begin`
297			`fifo_sel_out <= 1'b0;`
298			`fifo_rd <= 1'b0;`
299			`end`
300			`end`
301			`end`
302
303
304			`always @(posedge reset or posedge clk0)`
305			`begin`
306			`if(reset == 1'b1)`
307			`begin`
308			`dma_wr_addr <= 24'h0;`
309			`dma_rd_addr <= 24'h0;`
310			`dma_rd_cmd <= 3'h0;`
311			`uart_cs <= 1'b0;`
312			`uart_rd <= 1'b0;`
313			`uart_wr <= 1'b0;`
314			`end`
315			`else`
316			`begin`
317			`dma_wr_addr <= dma_wr_addr_cnt;`
318			`if(ween == 1'b1)`
319			`begin`
320			`uart_cs <= 1'b1;`
321			`uart_wr <= 1'b1;`
322			`dma_rd_cmd <= 3'b010;`
323			`dma_wr_addr <= dma_wr_addr_cnt;`
324			`end`
325			`else`
326			`if(reen == 1'b1)`
327			`begin`
328			`uart_cs <= 1'b1;`
329			`uart_rd <= 1'b1;`
330			`dma_rd_cmd <= 3'b001;`
331			`dma_rd_addr <= dma_rd_addr_cnt;`
332			`end`
333			`end`
334			`end`
335
336			`endmodule`