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/*********************************************************
 MODULE:                Sub Level RISC uProcessor Block
 
 FILE NAME:     risc.v
 VERSION:       1.0
 DATE:          May 7th, 2002
 AUTHOR:                Hossein Amidi
 COMPANY:
 CODE TYPE:     Register Transfer Level
 
 DESCRIPTION:   This module is the top level RTL code of RISC uProcessor verilog code.
 
 It will instantiate the following blocks in the ASIC:
 
 1) Program Counter
 2) Instruction Register
 3) Accumulator
 4) Arithmatic Logic Unit
 5) Multiplexer
 6) Multiplexer
 7) Control Unit
 
 Hossein Amidi
 (C) April 2002
 
*********************************************************/
 
// DEFINES
`timescale 1ns / 10ps
 
// TOP MODULE
module risc(// Inputs
                                reset,
                                clk0,
                                pll_lock,
                                interrupt,
                                cmdack,
                                dcache_datain,
                                dcache_hit,
                                dcache_miss,
                                icache_datain,
                                icache_hit,
                                icache_miss,
                                dma_datain,
                                dma_busy,
                                timer_host_datain,
                                flash_host_datain,
                                uart_host_datain,
                                mem_datain,
                                // Outputs
                                paddr,
                                cmd,
                                dm,
                                dcache_request,
                                icache_request,
                                dma_dataout,
                                dcache_dataout,
                                icache_dataout,
                                timer_host_dataout,
                                flash_host_dataout,
                                uart_host_dataout,
                                mem_dataout,
                                mem_req,
                                mem_rdwr,
                                halted
                                );
 
 
// Parameter
`include        "parameter.v"
 
 
// Inputs
input reset;
input clk0;
input pll_lock;
input [irq_size - 1 : 0]interrupt;
input cmdack;
input [data_size - 1 : 0]dcache_datain;
input dcache_hit;
input dcache_miss;
input [data_size - 1 : 0]icache_datain;
input icache_hit;
input icache_miss;
input [data_size - 1 : 0]dma_datain;
input dma_busy;
input [data_size - 1 : 0]timer_host_datain;
input [data_size - 1 : 0]flash_host_datain;
input [data_size - 1 : 0]uart_host_datain;
input [data_size - 1 : 0]mem_datain;
 
// Outputs
output [padd_size - 1 : 0]paddr;
output [cmd_size  - 1 : 0]cmd;
output [dqm_size  - 1 : 0]dm;
output dcache_request;
output icache_request;
output [data_size - 1 : 0]dma_dataout;
output [data_size - 1 : 0]dcache_dataout;
output [data_size - 1 : 0]icache_dataout;
output [data_size - 1 : 0]timer_host_dataout;
output halted;
output [data_size - 1 : 0]flash_host_dataout;
output [data_size - 1 : 0]uart_host_dataout;
output [data_size - 1 : 0]mem_dataout;
output mem_req;
output mem_rdwr;
 
// Signal Declarations
wire reset;
wire clk0;
wire pll_lock;
wire [irq_size - 1 : 0]interrupt;
wire cmdack;
wire [data_size - 1 : 0]dcache_datain;
wire dcache_hit;
wire dcache_miss;
wire [data_size - 1 : 0]icache_datain;
wire icache_hit;
wire icache_miss;
wire [data_size - 1 : 0]dma_datain;
wire dma_busy;
wire [data_size - 1 : 0]timer_host_datain;
wire [data_size - 1 : 0]flash_host_datain;
wire [data_size - 1 : 0]uart_host_datain;
wire [data_size - 1 : 0]mem_datain;
wire ready;
 
 
wire [padd_size - 1 : 0]paddr;
reg [cmd_size  - 1 : 0]cmd;
reg [dqm_size  - 1 : 0]dm;
wire dcache_request;
wire icache_request;
wire [data_size - 1 : 0]dma_dataout;
wire [data_size - 1 : 0]dcache_dataout;
wire [data_size - 1 : 0]icache_dataout;
wire [data_size - 1 : 0]timer_host_dataout;
wire halted;
wire [data_size - 1 : 0]flash_host_dataout;
wire [data_size - 1 : 0]uart_host_dataout;
wire [data_size - 1 : 0]mem_dataout;
wire mem_req;
wire mem_rdwr;
 
reg [data_size - 1 : 0]rdma_datain;
reg rdcache_miss;
reg rdcache_hit;
reg [data_size - 1 : 0]rdcache_datain;
reg ricache_miss;
reg ricache_hit;
reg [data_size - 1 : 0]ricache_datain;
reg [irq_size - 1 : 0]rinterrupt;
 
 
// Assignment statments
 
 
// Signal Declerations
wire [AddrWidth - 1 : 0] instraddress;
wire [DataWidth - 1 : 0] aludataout;
wire pcinen;
wire [AddrWidth - 1 : 0] operandaddress;
wire [OpcodeWidth - 1 : 0] opcode;
wire [DataWidth - 1 : 0] datain;
wire irinen;
wire [DataWidth - 1 : 0] accdataout;
wire accneg;
wire acczero;
wire accinen;
wire [StateSize - 1 : 0] currentstate;
wire [DataWidth - 1 : 0] mux16out;
wire [AddrWidth - 1 : 0] address;
wire addresssel;
wire alusrcbsel;
wire walusrcbsel;
wire accouten;
 
wire memreq;
wire rdwrbar;
 
reg Rd_req;
reg Wr_req;
wire [DataWidth - 1 : 0] dataout;
wire Halted;
//wire [DataWidth - 1 : 0] datain;
 
 
// Assignments
assign halted = Halted;
assign ready = cmdack;
assign paddr = address;
assign datain = dcache_hit ? datain : 32'bz;
assign mem_dataout = accouten? accdataout: 32'bz;
assign Halted = (opcode == 7) ? 1'b1 : 1'b0;
 
assign walusrcbsel = alusrcbsel;
 
assign dcache_request = Rd_req | Wr_req;
assign icache_request = Rd_req | Wr_req;
 
 
assign mem_req = memreq;
assign mem_rdwr = rdwrbar;
 
assign dma_dataout = mem_dataout;
assign flash_host_dataout = mem_dataout;
assign dcache_dataout = mem_dataout;
assign icache_dataout = mem_dataout;
assign timer_host_dataout = mem_dataout;
assign uart_host_dataout = mem_dataout;
 
always @(rdwrbar or memreq)
begin
        if((memreq == 1'b1) && (rdwrbar == 1'b1))
        begin
                Rd_req = 1'b1;
                Wr_req = 1'b0;
        end
        else
        if((memreq == 1'b1) && (rdwrbar == 1'b0))
        begin
                Rd_req = 1'b0;
                Wr_req = 1'b1;
        end
        else
        begin
                Rd_req = 1'b0;
                Wr_req = 1'b0;
        end
end
 
 
always @(memreq or Wr_req or Rd_req)
begin
        case({memreq, Wr_req, Rd_req})
 
                3'b100: cmd <= 3'b000;  // NOP
                3'b101: cmd <= 3'b001;  // ReadA
                3'b110: cmd <= 3'b010;  // WriteA
                3'b111: cmd <= 3'b011;  // Refresh
                3'b000: cmd <= 3'b100;  // Preacharge
                3'b001: cmd <= 3'b101;  // Load Mode Register
                3'b010: cmd <= 3'b110;  // Load Timing Register
                3'b011: cmd <= 3'b111;  // Load Refresh Counter
        endcase
 
end
 
always @(posedge reset or posedge clk0)
begin
        if (reset == 1'b1)
        begin
                dm <= 4'h0;
        end
        else
        begin
                dm <= {1'b1,rinterrupt};
        end
end
 
 
always @(posedge reset or posedge clk0)
begin
        if(reset == 1'b1)
        begin
                rdma_datain <= 32'h0;
                rdcache_miss <= 1'b0;
                rdcache_hit <= 1'b0;
                rdcache_datain <= 32'h0;
                ricache_miss <= 1'b0;
                ricache_hit <= 1'b0;
                ricache_datain <= 32'h0;
                rinterrupt <= 3'b0;
        end
        else
        begin
                rdma_datain <= dma_datain;
                rdcache_miss <= dcache_miss;
                rdcache_hit <= dcache_hit & rdcache_hit;
                rdcache_datain <= dcache_datain;
                ricache_miss <= icache_miss;
                ricache_hit <= icache_hit & ricache_hit;
                ricache_datain <= icache_datain;
                rinterrupt <= interrupt;
        end
end
 
 
 
 
 
/***************************** Instantiation **************************/
 
// RISC CPU's Program Counter Instantiation
PC ProgramCounter (     // INPUT
                                                        .clock(clk0),
                                                        .reset(reset),
                                                        .PCInEn(pcinen),
                                                        .PCDataIn(aludataout[23:0]),
                                                        // OUTPUT
                                                        .PCDataOut(instraddress)
                                                        );
 
 
// RISC CPU's Instruction Register Instantiation
IR InstructionRegister (        // Input
                                                                        .clock(clk0),
                                                                        .reset(reset),
                                                                        .IRInEn(irinen),
                                                                        .IRDataIn(mem_datain),
                                                                        // Output
                                                                        .OperandOut(operandaddress),
                                                                        .OpCodeOut(opcode)
                                                                        );
 
 
// RISC CPU's Accumulator Instantiation
ACC Accumulator (       // Input
                                                .clock(clk0),
                                                .reset(reset),
                                                .ACCInEn(accinen),
                                                .ACCDataIn(aludataout),
                                                // Output
                                                .ACCNeg(accneg),
                                                .ACCZero(acczero),
                                                .ACCDataOut(accdataout)
                                        );
 
 
 
// RISC CPU's Arithmatic Logic Unit Instantiation
ALU ALU                         (       // Input
                                                .ALUSrcA(accdataout),
                                                .ALUSrcB(mux16out),
                                                .OpCode(opcode),
                                                .CurrentState(currentstate),
                                                // Output
                                                .ALUDataOut(aludataout)
                                        );
 
 
MUX12 Mux12             (       // Input
                                                        .A_in(operandaddress),
                                                        .B_in(instraddress),
                                                        .A_Select(addresssel),
                                                        // Output
                                                        .Out(address)
                                                );
 
 
MUX16 Mux16             (       // Input
                                                        .A_in(address),
                                                        .B_in(mem_datain),
                                                        .A_Select(walusrcbsel),
                                                        // Output
                                                        .Out(mux16out)
                                                );
 
 
 
// RISC CPU's Control Unit Instantiation
CNTRL ControlUnit (     // Input
                                                        .clock(clk0),
                                                        .reset(reset),
                                                        .OpCode(opcode),
                                                        .ACCNeg(accneg),
                                                        .ACCZero(acczero),
                                                        .Grant(pll_lock),
                                                        // Output
                                                        .NextState(currentstate),
                                                        .PCInEn(pcinen),
                                                        .IRInEn(irinen),
                                                        .ACCInEn(accinen),
                                                        .ACCOutEn(accouten),
                                                        .MemReq(memreq),
                                                        .RdWrBar(rdwrbar),
                                                        .AddressSel(addresssel),
                                                        .ALUSrcBSel(alusrcbsel)
                                                        );
 
endmodule

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[/] [embedded_risc/] [trunk/] [Verilog/] [risc.v] - Blame information for rev 27

Line No.	Rev	Author	Line
1	26	hosseinami	`/*********************************************************`
2			`MODULE: Sub Level RISC uProcessor Block`
3
4			`FILE NAME: risc.v`
5			`VERSION: 1.0`
6			`DATE: May 7th, 2002`
7			`AUTHOR: Hossein Amidi`
8			`COMPANY:`
9			`CODE TYPE: Register Transfer Level`
10
11			`DESCRIPTION: This module is the top level RTL code of RISC uProcessor verilog code.`
12
13			`It will instantiate the following blocks in the ASIC:`
14
15			`1) Program Counter`
16			`2) Instruction Register`
17			`3) Accumulator`
18			`4) Arithmatic Logic Unit`
19			`5) Multiplexer`
20			`6) Multiplexer`
21			`7) Control Unit`
22
23			`Hossein Amidi`
24			`(C) April 2002`
25
26			`*********************************************************/`
27
28			`// DEFINES`
29			`timescale 1ns / 10ps
30
31			`// TOP MODULE`
32			`module risc(// Inputs`
33			`reset,`
34			`clk0,`
35			`pll_lock,`
36			`interrupt,`
37			`cmdack,`
38			`dcache_datain,`
39			`dcache_hit,`
40			`dcache_miss,`
41			`icache_datain,`
42			`icache_hit,`
43			`icache_miss,`
44			`dma_datain,`
45			`dma_busy,`
46			`timer_host_datain,`
47			`flash_host_datain,`
48			`uart_host_datain,`
49			`mem_datain,`
50			`// Outputs`
51			`paddr,`
52			`cmd,`
53			`dm,`
54			`dcache_request,`
55			`icache_request,`
56			`dma_dataout,`
57			`dcache_dataout,`
58			`icache_dataout,`
59			`timer_host_dataout,`
60			`flash_host_dataout,`
61			`uart_host_dataout,`
62			`mem_dataout,`
63			`mem_req,`
64			`mem_rdwr,`
65			`halted`
66			`);`
67
68
69			`// Parameter`
70			`include "parameter.v"
71
72
73			`// Inputs`
74			`input reset;`
75			`input clk0;`
76			`input pll_lock;`
77			`input [irq_size - 1 : 0]interrupt;`
78			`input cmdack;`
79			`input [data_size - 1 : 0]dcache_datain;`
80			`input dcache_hit;`
81			`input dcache_miss;`
82			`input [data_size - 1 : 0]icache_datain;`
83			`input icache_hit;`
84			`input icache_miss;`
85			`input [data_size - 1 : 0]dma_datain;`
86			`input dma_busy;`
87			`input [data_size - 1 : 0]timer_host_datain;`
88			`input [data_size - 1 : 0]flash_host_datain;`
89			`input [data_size - 1 : 0]uart_host_datain;`
90			`input [data_size - 1 : 0]mem_datain;`
91
92			`// Outputs`
93			`output [padd_size - 1 : 0]paddr;`
94			`output [cmd_size - 1 : 0]cmd;`
95			`output [dqm_size - 1 : 0]dm;`
96			`output dcache_request;`
97			`output icache_request;`
98			`output [data_size - 1 : 0]dma_dataout;`
99			`output [data_size - 1 : 0]dcache_dataout;`
100			`output [data_size - 1 : 0]icache_dataout;`
101			`output [data_size - 1 : 0]timer_host_dataout;`
102			`output halted;`
103			`output [data_size - 1 : 0]flash_host_dataout;`
104			`output [data_size - 1 : 0]uart_host_dataout;`
105			`output [data_size - 1 : 0]mem_dataout;`
106			`output mem_req;`
107			`output mem_rdwr;`
108
109			`// Signal Declarations`
110			`wire reset;`
111			`wire clk0;`
112			`wire pll_lock;`
113			`wire [irq_size - 1 : 0]interrupt;`
114			`wire cmdack;`
115			`wire [data_size - 1 : 0]dcache_datain;`
116			`wire dcache_hit;`
117			`wire dcache_miss;`
118			`wire [data_size - 1 : 0]icache_datain;`
119			`wire icache_hit;`
120			`wire icache_miss;`
121			`wire [data_size - 1 : 0]dma_datain;`
122			`wire dma_busy;`
123			`wire [data_size - 1 : 0]timer_host_datain;`
124			`wire [data_size - 1 : 0]flash_host_datain;`
125			`wire [data_size - 1 : 0]uart_host_datain;`
126			`wire [data_size - 1 : 0]mem_datain;`
127			`wire ready;`
128
129
130			`wire [padd_size - 1 : 0]paddr;`
131			`reg [cmd_size - 1 : 0]cmd;`
132			`reg [dqm_size - 1 : 0]dm;`
133			`wire dcache_request;`
134			`wire icache_request;`
135			`wire [data_size - 1 : 0]dma_dataout;`
136			`wire [data_size - 1 : 0]dcache_dataout;`
137			`wire [data_size - 1 : 0]icache_dataout;`
138			`wire [data_size - 1 : 0]timer_host_dataout;`
139			`wire halted;`
140			`wire [data_size - 1 : 0]flash_host_dataout;`
141			`wire [data_size - 1 : 0]uart_host_dataout;`
142			`wire [data_size - 1 : 0]mem_dataout;`
143			`wire mem_req;`
144			`wire mem_rdwr;`
145
146			`reg [data_size - 1 : 0]rdma_datain;`
147			`reg rdcache_miss;`
148			`reg rdcache_hit;`
149			`reg [data_size - 1 : 0]rdcache_datain;`
150			`reg ricache_miss;`
151			`reg ricache_hit;`
152			`reg [data_size - 1 : 0]ricache_datain;`
153			`reg [irq_size - 1 : 0]rinterrupt;`
154
155
156			`// Assignment statments`
157
158
159			`// Signal Declerations`
160			`wire [AddrWidth - 1 : 0] instraddress;`
161			`wire [DataWidth - 1 : 0] aludataout;`
162			`wire pcinen;`
163			`wire [AddrWidth - 1 : 0] operandaddress;`
164			`wire [OpcodeWidth - 1 : 0] opcode;`
165			`wire [DataWidth - 1 : 0] datain;`
166			`wire irinen;`
167			`wire [DataWidth - 1 : 0] accdataout;`
168			`wire accneg;`
169			`wire acczero;`
170			`wire accinen;`
171			`wire [StateSize - 1 : 0] currentstate;`
172			`wire [DataWidth - 1 : 0] mux16out;`
173			`wire [AddrWidth - 1 : 0] address;`
174			`wire addresssel;`
175			`wire alusrcbsel;`
176			`wire walusrcbsel;`
177			`wire accouten;`
178
179			`wire memreq;`
180			`wire rdwrbar;`
181
182			`reg Rd_req;`
183			`reg Wr_req;`
184			`wire [DataWidth - 1 : 0] dataout;`
185			`wire Halted;`
186			`//wire [DataWidth - 1 : 0] datain;`
187
188
189			`// Assignments`
190			`assign halted = Halted;`
191			`assign ready = cmdack;`
192			`assign paddr = address;`
193			`assign datain = dcache_hit ? datain : 32'bz;`
194			`assign mem_dataout = accouten? accdataout: 32'bz;`
195			`assign Halted = (opcode == 7) ? 1'b1 : 1'b0;`
196
197			`assign walusrcbsel = alusrcbsel;`
198
199			`assign dcache_request = Rd_req \| Wr_req;`
200			`assign icache_request = Rd_req \| Wr_req;`
201
202
203			`assign mem_req = memreq;`
204			`assign mem_rdwr = rdwrbar;`
205
206			`assign dma_dataout = mem_dataout;`
207			`assign flash_host_dataout = mem_dataout;`
208			`assign dcache_dataout = mem_dataout;`
209			`assign icache_dataout = mem_dataout;`
210			`assign timer_host_dataout = mem_dataout;`
211			`assign uart_host_dataout = mem_dataout;`
212
213			`always @(rdwrbar or memreq)`
214			`begin`
215			`if((memreq == 1'b1) && (rdwrbar == 1'b1))`
216			`begin`
217			`Rd_req = 1'b1;`
218			`Wr_req = 1'b0;`
219			`end`
220			`else`
221			`if((memreq == 1'b1) && (rdwrbar == 1'b0))`
222			`begin`
223			`Rd_req = 1'b0;`
224			`Wr_req = 1'b1;`
225			`end`
226			`else`
227			`begin`
228			`Rd_req = 1'b0;`
229			`Wr_req = 1'b0;`
230			`end`
231			`end`
232
233
234			`always @(memreq or Wr_req or Rd_req)`
235			`begin`
236			`case({memreq, Wr_req, Rd_req})`
237
238			`3'b100: cmd <= 3'b000; // NOP`
239			`3'b101: cmd <= 3'b001; // ReadA`
240			`3'b110: cmd <= 3'b010; // WriteA`
241			`3'b111: cmd <= 3'b011; // Refresh`
242			`3'b000: cmd <= 3'b100; // Preacharge`
243			`3'b001: cmd <= 3'b101; // Load Mode Register`
244			`3'b010: cmd <= 3'b110; // Load Timing Register`
245			`3'b011: cmd <= 3'b111; // Load Refresh Counter`
246			`endcase`
247
248			`end`
249
250			`always @(posedge reset or posedge clk0)`
251			`begin`
252			`if (reset == 1'b1)`
253			`begin`
254			`dm <= 4'h0;`
255			`end`
256			`else`
257			`begin`
258			`dm <= {1'b1,rinterrupt};`
259			`end`
260			`end`
261
262
263			`always @(posedge reset or posedge clk0)`
264			`begin`
265			`if(reset == 1'b1)`
266			`begin`
267			`rdma_datain <= 32'h0;`
268			`rdcache_miss <= 1'b0;`
269			`rdcache_hit <= 1'b0;`
270			`rdcache_datain <= 32'h0;`
271			`ricache_miss <= 1'b0;`
272			`ricache_hit <= 1'b0;`
273			`ricache_datain <= 32'h0;`
274			`rinterrupt <= 3'b0;`
275			`end`
276			`else`
277			`begin`
278			`rdma_datain <= dma_datain;`
279			`rdcache_miss <= dcache_miss;`
280			`rdcache_hit <= dcache_hit & rdcache_hit;`
281			`rdcache_datain <= dcache_datain;`
282			`ricache_miss <= icache_miss;`
283			`ricache_hit <= icache_hit & ricache_hit;`
284			`ricache_datain <= icache_datain;`
285			`rinterrupt <= interrupt;`
286			`end`
287			`end`
288
289
290
291
292
293			`/*************************** Instantiation ************************/`
294
295			`// RISC CPU's Program Counter Instantiation`
296			`PC ProgramCounter ( // INPUT`
297			`.clock(clk0),`
298			`.reset(reset),`
299			`.PCInEn(pcinen),`
300			`.PCDataIn(aludataout[23:0]),`
301			`// OUTPUT`
302			`.PCDataOut(instraddress)`
303			`);`
304
305
306			`// RISC CPU's Instruction Register Instantiation`
307			`IR InstructionRegister ( // Input`
308			`.clock(clk0),`
309			`.reset(reset),`
310			`.IRInEn(irinen),`
311			`.IRDataIn(mem_datain),`
312			`// Output`
313			`.OperandOut(operandaddress),`
314			`.OpCodeOut(opcode)`
315			`);`
316
317
318			`// RISC CPU's Accumulator Instantiation`
319			`ACC Accumulator ( // Input`
320			`.clock(clk0),`
321			`.reset(reset),`
322			`.ACCInEn(accinen),`
323			`.ACCDataIn(aludataout),`
324			`// Output`
325			`.ACCNeg(accneg),`
326			`.ACCZero(acczero),`
327			`.ACCDataOut(accdataout)`
328			`);`
329
330
331
332			`// RISC CPU's Arithmatic Logic Unit Instantiation`
333			`ALU ALU ( // Input`
334			`.ALUSrcA(accdataout),`
335			`.ALUSrcB(mux16out),`
336			`.OpCode(opcode),`
337			`.CurrentState(currentstate),`
338			`// Output`
339			`.ALUDataOut(aludataout)`
340			`);`
341
342
343			`MUX12 Mux12 ( // Input`
344			`.A_in(operandaddress),`
345			`.B_in(instraddress),`
346			`.A_Select(addresssel),`
347			`// Output`
348			`.Out(address)`
349			`);`
350
351
352			`MUX16 Mux16 ( // Input`
353			`.A_in(address),`
354			`.B_in(mem_datain),`
355			`.A_Select(walusrcbsel),`
356			`// Output`
357			`.Out(mux16out)`
358			`);`
359
360
361
362			`// RISC CPU's Control Unit Instantiation`
363			`CNTRL ControlUnit ( // Input`
364			`.clock(clk0),`
365			`.reset(reset),`
366			`.OpCode(opcode),`
367			`.ACCNeg(accneg),`
368			`.ACCZero(acczero),`
369			`.Grant(pll_lock),`
370			`// Output`
371			`.NextState(currentstate),`
372			`.PCInEn(pcinen),`
373			`.IRInEn(irinen),`
374			`.ACCInEn(accinen),`
375			`.ACCOutEn(accouten),`
376			`.MemReq(memreq),`
377			`.RdWrBar(rdwrbar),`
378			`.AddressSel(addresssel),`
379			`.ALUSrcBSel(alusrcbsel)`
380			`);`
381
382			`endmodule`