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-- This file is owned and controlled by Xilinx and must be used solely --
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-- for design, simulation, implementation and creation of design files --
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-- limited to Xilinx devices or technologies. Use with non-Xilinx --
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-- devices or technologies is expressly prohibited and immediately --
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-- terminates your license. --
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-- --
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-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
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-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
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-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
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-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
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-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
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-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
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-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
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-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
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-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
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-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
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-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
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-- PARTICULAR PURPOSE. --
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-- --
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-- Xilinx products are not intended for use in life support appliances, --
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-- devices, or systems. Use in such applications are expressly --
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-- prohibited. --
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-- --
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-- (c) Copyright 1995-2014 Xilinx, Inc. --
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-- All rights reserved. --
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- Generated from core with identifier: xilinx.com:ip:blk_mem_gen:7.2 --
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-- --
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-- The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port --
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-- Block Memory and Single Port Block Memory LogiCOREs, but is not a --
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-- direct drop-in replacement. It should be used in all new Xilinx --
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-- designs. The core supports RAM and ROM functions over a wide range of --
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-- widths and depths. Use this core to generate block memories with --
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-- symmetric or asymmetric read and write port widths, as well as cores --
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-- which can perform simultaneous write operations to separate --
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-- locations, and simultaneous read operations from the same location. --
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-- For more information on differences in interface and feature support --
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-- between this core and the Dual Port Block Memory and Single Port --
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-- Block Memory LogiCOREs, please consult the data sheet. --
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--------------------------------------------------------------------------------
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-- Synthesized Netlist Wrapper
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-- This file is provided to wrap around the synthesized netlist (if appropriate)
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-- Interfaces:
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-- CLK.ACLK
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-- AXI4 Interconnect Clock Input
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-- RST.ARESETN
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-- AXI4 Interconnect Reset Input
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-- AXI_SLAVE_S_AXI
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-- AXI_SLAVE
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-- AXILite_SLAVE_S_AXI
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-- AXILite_SLAVE
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-- BRAM_PORTA
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-- BRAM_PORTA
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-- BRAM_PORTB
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-- BRAM_PORTB
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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ENTITY FONT_MEM IS
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PORT (
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clka : IN STD_LOGIC;
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wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
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dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
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);
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END FONT_MEM;
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ARCHITECTURE spartan3e OF FONT_MEM IS
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BEGIN
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-- WARNING: This file provides an entity declaration with empty architecture, it
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-- does not support direct instantiation. Please use an instantiation
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-- template (VHO) to instantiate the IP within a design.
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END spartan3e;
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