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[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.accelerator/] [dctqidct/] [1.0/] [hdl/] [common_da/] [Mux2to1.vhd] - Blame information for rev 145

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1 145 lanttu
------------------------------------------------------------------------------
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-- Author               : Timo Alho
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-- e-mail               : timo.a.alho@tut.fi
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-- Date                 : 15.06.2004 19:03:50
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-- File                 : Mux2to1.vhd
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-- Design               : VHDL Entity Mux2to1.rtl
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------------------------------------------------------------------------------
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-- Description  : Generic 2->1 multiplexer
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------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_arith.ALL;
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ENTITY Mux2to1 IS
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   GENERIC(
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      dataw_g : integer := 16
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   );
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   PORT(
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      in0     : IN     std_logic_vector (dataw_g-1 DOWNTO 0);
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      in1     : IN     std_logic_vector (dataw_g-1 DOWNTO 0);
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      sel     : IN     std_logic;
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      mux_out : OUT    std_logic_vector (dataw_g-1 DOWNTO 0)
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   );
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-- Declarations
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END Mux2to1 ;
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--
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ARCHITECTURE rtl OF Mux2to1 IS
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BEGIN
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  -- purpose: selects input
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  -- type   : combinational
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  -- inputs : sel, in0, in1
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  -- outputs: 
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  selector : PROCESS (sel, in0, in1)
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  BEGIN  -- PROCESS selector
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    IF (sel = '0') THEN
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      mux_out <= in0;
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    ELSE
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      mux_out <= in1;
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    END IF;
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  END PROCESS selector;
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END rtl;
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