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[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.accelerator/] [dctqidct/] [1.0/] [hdl/] [dct/] [DCT_control.vhd] - Blame information for rev 145

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------------------------------------------------------------------------------
-- Author        : Timo Alho
-- e-mail        : timo.a.alho@tut.fi
-- Date          : 11.08.2004 13:28:09
-- File          : DCT_control.vhd
-- Design        : VHDL Entity for dct.DCT_control.symbol
-- Generated by Mentor Graphics' HDL Designer 2003.1 (Build 399)
------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
LIBRARY dct;
USE dct.DCT_pkg.all;
LIBRARY common_da;
 
ENTITY DCT_control IS
   PORT(
      clk              : IN     std_logic;
      next_block_ready : IN     std_logic;
      rst_n            : IN     std_logic;
      wr_new_data      : IN     std_logic;
      DC               : OUT    std_logic;
      load_dct_input   : OUT    std_logic;
      load_dct_output  : OUT    std_logic;
      out_clk_en       : OUT    std_logic;
      rdaddr           : OUT    std_logic_vector (5 DOWNTO 0);
      ready_for_rx     : OUT    std_logic;
      sel_input        : OUT    std_logic;
      start_dct        : OUT    std_logic;
      stop_dct         : OUT    std_logic;
      we               : OUT    std_logic;
      wr_out           : OUT    std_logic;
      wraddr           : OUT    std_logic_vector (5 DOWNTO 0)
   );
 
-- Declarations
 
END DCT_control ;
 
------------------------------------------------------------------------------
-- Author        : Timo Alho
-- e-mail        : timo.a.alho@tut.fi
-- Date          : 11.08.2004 13:28:10
-- File          : DCT_control.vhd
-- Design        : VHDL Architecture for dct.DCT_control.symbol
-- Generated by Mentor Graphics' HDL Designer 2003.1 (Build 399)
------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
LIBRARY dct;
USE dct.DCT_pkg.all;
 
ARCHITECTURE fsm OF DCT_control IS
 
   -- Architecture Declarations
   signal wait_counter_r : unsigned (4 downto 0);
   signal col_nr_r : unsigned(2 downto 0);
   signal row_rd_nr_r : unsigned(2 downto 0);
   signal row_wr_nr_r : unsigned(2 downto 0);
 
   signal in_counter_r : unsigned(2 downto 0);
   --signal in_counter_next : unsigned(2 downto 0);
 
   signal out_counter_r : unsigned(2 downto 0);
   --signal out_counter_next : unsigned(2 downto 0);
 
   signal output_ready : std_logic;
 
   signal load_rows : std_logic;
   signal load_columns : std_logic;
   signal save_result : std_logic;
   signal result_out : std_logic;
   signal col_ready : std_logic;
 
   TYPE CSM_STATE_TYPE IS (
      start,
      start_col_calc,
      wait_col_calc,
      stop_last_row,
      wait_row_calc,
      wait_data,
      stop_and_start_next_col,
      stop_col_calc,
      stop_last_col,
      dummy0,
      start_row_calc,
      stop_row_calc,
      wait_output_free,
      stop_and_start_next_row,
      dummy1,
      wt_nxt
   );
   TYPE CSM1_STATE_TYPE IS (
      o_ready,
      wr_col_to_ram,
      result_to_buffer,
      result_to_buffer2,
      res_out1,
      wait_output
   );
   TYPE CSM2_STATE_TYPE IS (
      i_ready,
      i_load_row,
      i_load_column,
      wait_ram_rd,
      wait_load,
      wait_1st_data
   );
 
 
   -- Declare current and next state signals
   SIGNAL csm_current_state : CSM_STATE_TYPE ;
   SIGNAL csm_next_state : CSM_STATE_TYPE ;
   SIGNAL csm1_current_state : CSM1_STATE_TYPE ;
   SIGNAL csm1_next_state : CSM1_STATE_TYPE ;
   SIGNAL csm2_current_state : CSM2_STATE_TYPE ;
   SIGNAL csm2_next_state : CSM2_STATE_TYPE ;
 
   -- Declare any pre-registered internal signals
   SIGNAL DC_int : std_logic  ;
   SIGNAL wr_out_int : std_logic  ;
 
BEGIN
 
   ----------------------------------------------------------------------------
   csm_clocked : PROCESS(
      clk,
      rst_n
   )
   ----------------------------------------------------------------------------
   BEGIN
      IF (rst_n = '0') THEN
         csm_current_state <= start;
         -- Reset Values
         col_nr_r <= (others => '0');
         row_rd_nr_r <= (others => '0');
         row_wr_nr_r <= (others => '0');
         wait_counter_r <= (others => '0');
      ELSIF (clk'EVENT AND clk = '1') THEN
         csm_current_state <= csm_next_state;
         -- Default Assignment To Internals
 
         -- Combined Actions for internal signals only
         CASE csm_current_state IS
         WHEN start_col_calc =>
            wait_counter_r <= (others => '0');
         WHEN wait_col_calc =>
            row_rd_nr_r <= (others => '0');
            wait_counter_r <= wait_counter_r + 1;
         WHEN stop_last_row =>
            row_rd_nr_r <= (others => '0');
            col_nr_r <= (others => '0');
         WHEN wait_row_calc =>
            --wait until row is processed
            wait_counter_r <= wait_counter_r + 1;
         WHEN stop_and_start_next_col =>
            col_nr_r <= col_nr_r + 1;
            row_wr_nr_r <= col_nr_r;
            wait_counter_r <= (others => '0');
         WHEN stop_col_calc =>
            col_nr_r <= col_nr_r + 1;
            row_wr_nr_r <= col_nr_r;
         WHEN stop_last_col =>
            col_nr_r <= (others => '0');
            row_wr_nr_r <= col_nr_r;
            wait_counter_r <= (others => '0');
            --load current block's QP parameter to output
         WHEN dummy0 =>
            --wait until last element of first row is read from memory
            wait_counter_r <= wait_counter_r+1;
         WHEN start_row_calc =>
            row_rd_nr_r <= row_rd_nr_r + 1;
            wait_counter_r <= (others => '0');
         WHEN stop_row_calc =>
            --stop calculation of current row
            col_nr_r <= col_nr_r + 1;
         WHEN stop_and_start_next_row =>
            row_rd_nr_r <= row_rd_nr_r + 1;
            col_nr_r <= col_nr_r + 1;
            wait_counter_r <= (others => '0');
         WHEN OTHERS =>
            NULL;
         END CASE;
 
      END IF;
 
   END PROCESS csm_clocked;
 
   ----------------------------------------------------------------------------
   csm_nextstate : PROCESS (
      col_nr_r,
      col_ready,
      csm_current_state,
      next_block_ready,
      wait_counter_r
   )
   ----------------------------------------------------------------------------
   BEGIN
      CASE csm_current_state IS
      WHEN start =>
            csm_next_state <= wait_data;
      WHEN start_col_calc =>
            csm_next_state <= wait_col_calc;
      WHEN wait_col_calc =>
         IF (col_nr_r =7 AND
         wait_counter_r = DCT_inputw_co) THEN
            csm_next_state <= stop_last_col;
         ELSIF (col_ready = '1' AND
         wait_counter_r = DCT_inputw_co) THEN
            csm_next_state <= stop_and_start_next_col;
         ELSIF (wait_counter_r = DCT_inputw_co) THEN
            csm_next_state <= stop_col_calc;
         ELSE
            csm_next_state <= wait_col_calc;
         END IF;
      WHEN stop_last_row =>
         IF (col_ready = '1' AND next_block_ready = '1') THEN
            csm_next_state <= start_col_calc;
         ELSE
            csm_next_state <= wt_nxt;
         END IF;
      WHEN wait_row_calc =>
         IF (wait_counter_r = DCT_dataw_co AND
         col_nr_r = 7) THEN
            csm_next_state <= stop_last_row;
         ELSIF (wait_counter_r = DCT_dataw_co AND
         next_block_ready = '1') THEN
            csm_next_state <= stop_and_start_next_row;
         ELSIF (wait_counter_r = DCT_dataw_co) THEN
            csm_next_state <= stop_row_calc;
         ELSE
            csm_next_state <= wait_row_calc;
         END IF;
      WHEN wait_data =>
         IF (col_ready = '1') THEN
            csm_next_state <= start_col_calc;
         ELSE
            csm_next_state <= wait_data;
         END IF;
      WHEN stop_and_start_next_col =>
            csm_next_state <= wait_col_calc;
      WHEN stop_col_calc =>
         IF (col_ready = '1') THEN
            csm_next_state <= start_col_calc;
         ELSE
            csm_next_state <= wait_data;
         END IF;
      WHEN stop_last_col =>
            csm_next_state <= dummy0;
      WHEN dummy0 =>
         IF (wait_counter_r = 2) THEN
            csm_next_state <= dummy1;
         ELSE
            csm_next_state <= dummy0;
         END IF;
      WHEN start_row_calc =>
            csm_next_state <= wait_row_calc;
      WHEN stop_row_calc =>
            csm_next_state <= wait_output_free;
      WHEN wait_output_free =>
         IF (next_block_ready = '1') THEN
            csm_next_state <= start_row_calc;
         ELSE
            csm_next_state <= wait_output_free;
         END IF;
      WHEN stop_and_start_next_row =>
            csm_next_state <= wait_row_calc;
      WHEN dummy1 =>
         IF (next_block_ready = '1') THEN
            csm_next_state <= start_row_calc;
         ELSE
            csm_next_state <= dummy1;
         END IF;
      WHEN wt_nxt =>
         IF (next_block_ready = '1') THEN
            csm_next_state <= wait_data;
         ELSE
            csm_next_state <= wt_nxt;
         END IF;
      WHEN OTHERS =>
         csm_next_state <= start;
      END CASE;
 
   END PROCESS csm_nextstate;
 
   ----------------------------------------------------------------------------
   csm_output : PROCESS (
      col_nr_r,
      csm_current_state,
      wait_counter_r
   )
   ----------------------------------------------------------------------------
   BEGIN
      -- Default Assignment
      start_dct <= '0';
      stop_dct <= '0';
      -- Default Assignment To Internals
      load_columns <= '0';
      load_rows <= '0';
      result_out <= '0';
      save_result <= '0';
 
      -- Combined Actions
      CASE csm_current_state IS
      WHEN start =>
         load_columns <= '1';
      WHEN start_col_calc =>
         --start calculation of column
         start_dct <= '1';
         if (col_nr_r /= 7) then
         load_columns <= '1';
         end if;
      WHEN wait_col_calc =>
         --wait few clock cycles while column is being processed
         if (col_nr_r = 7 AND wait_counter_r = 5) then
         --last column is being processed so we can start loading input "buffer" with values of first row
         load_rows <= '1';
         end if;
      WHEN stop_last_row =>
         --stop calculation of the last row
         stop_dct <= '1';
         result_out <= '1';
      WHEN wait_data =>
         --wait until there is new data available
      WHEN stop_and_start_next_col =>
         --stop calculation of current column, and start calculation of next column
         if (col_nr_r /=6) then
         load_columns <= '1';
         end if;
         start_dct <=  '1';
         stop_dct <= '1';
         save_result <= '1';
      WHEN stop_col_calc =>
         --stop calculation of current column
         stop_dct <= '1';
         save_result <= '1';
      WHEN stop_last_col =>
         --stop calculation of last column
         stop_dct <= '1';
         save_result <= '1';
      WHEN start_row_calc =>
         --start calculation of row
         start_dct <= '1';
         if (col_nr_r /=7) then
           load_rows <= '1';
         else
           load_columns <= '1';
         end if;
      WHEN stop_row_calc =>
         stop_dct <= '1';
         result_out <= '1';
      WHEN wait_output_free =>
         --we must wait until next block is capable of receiving data
      WHEN stop_and_start_next_row =>
         --stop calculation of current row, and start next row
         start_dct <= '1';
         stop_dct <= '1';
         result_out <= '1';
         if (col_nr_r /= 6) then
           load_rows <= '1';
         else
           load_columns <= '1';
         end if;
      WHEN OTHERS =>
         NULL;
      END CASE;
 
   END PROCESS csm_output;
 
   ----------------------------------------------------------------------------
   csm1_clocked : PROCESS(
      clk,
      rst_n
   )
   ----------------------------------------------------------------------------
   BEGIN
      IF (rst_n = '0') THEN
         csm1_current_state <= o_ready;
         -- Reset Values
         DC <= '0';
         wr_out <= '0';
         out_counter_r <= (others => '0');
      ELSIF (clk'EVENT AND clk = '1') THEN
         csm1_current_state <= csm1_next_state;
         -- Registered output assignments
         DC <= DC_int;
         wr_out <= wr_out_int;
 
         -- Default Assignment To Internals
 
         -- Combined Actions for internal signals only
         CASE csm1_current_state IS
         WHEN o_ready =>
            out_counter_r <= (others => '0');
         WHEN wr_col_to_ram =>
            out_counter_r <= out_counter_r + 1;
         WHEN res_out1 =>
            out_counter_r <= out_counter_r + 1;
         WHEN OTHERS =>
            NULL;
         END CASE;
 
      END IF;
 
   END PROCESS csm1_clocked;
 
   ----------------------------------------------------------------------------
   csm1_nextstate : PROCESS (
      csm1_current_state,
      next_block_ready,
      out_counter_r,
      result_out,
      save_result
   )
   ----------------------------------------------------------------------------
   BEGIN
      CASE csm1_current_state IS
      WHEN o_ready =>
         IF (save_result = '1') THEN
            csm1_next_state <= result_to_buffer;
         ELSIF (result_out = '1') THEN
            csm1_next_state <= result_to_buffer2;
         ELSE
            csm1_next_state <= o_ready;
         END IF;
      WHEN wr_col_to_ram =>
         IF (out_counter_r = 7) THEN
            csm1_next_state <= o_ready;
         ELSE
            csm1_next_state <= wr_col_to_ram;
         END IF;
      WHEN result_to_buffer =>
            csm1_next_state <= wr_col_to_ram;
      WHEN result_to_buffer2 =>
         IF (next_block_ready = '1') THEN
            csm1_next_state <= res_out1;
         ELSE
            csm1_next_state <= wait_output;
         END IF;
      WHEN res_out1 =>
         IF (out_counter_r = 7) THEN
            csm1_next_state <= o_ready;
         ELSE
            csm1_next_state <= res_out1;
         END IF;
      WHEN wait_output =>
         IF (next_block_ready = '1') THEN
            csm1_next_state <= res_out1;
         ELSE
            csm1_next_state <= wait_output;
         END IF;
      WHEN OTHERS =>
         csm1_next_state <= o_ready;
      END CASE;
 
   END PROCESS csm1_nextstate;
 
   ----------------------------------------------------------------------------
   csm1_output : PROCESS (
      col_nr_r,
      csm1_current_state,
      out_counter_r
   )
   ----------------------------------------------------------------------------
   BEGIN
      -- Default Assignment
      DC_int <= '0';
      load_dct_output <= '0';
      out_clk_en <= '0';
      we <= '0';
      wr_out_int <= '0';
      -- Default Assignment To Internals
      output_ready <= '0';
 
      -- Combined Actions
      CASE csm1_current_state IS
      WHEN o_ready =>
         output_ready <= '1';
      WHEN wr_col_to_ram =>
         we <= '1';
         out_clk_en <= '1';
      WHEN result_to_buffer =>
         load_dct_output <= '1';
      WHEN result_to_buffer2 =>
         load_dct_output <= '1';
      WHEN res_out1 =>
         out_clk_en <= '1';
         wr_out_int <= '1';
         if (col_nr_r = 1 AND out_counter_r = 0) then
         DC_int <= '1';
         end if;
      WHEN OTHERS =>
         NULL;
      END CASE;
 
   END PROCESS csm1_output;
 
   ----------------------------------------------------------------------------
   csm2_clocked : PROCESS(
      clk,
      rst_n
   )
   ----------------------------------------------------------------------------
   BEGIN
      IF (rst_n = '0') THEN
         csm2_current_state <= i_ready;
         -- Reset Values
         in_counter_r <= (others => '0');
      ELSIF (clk'EVENT AND clk = '1') THEN
         csm2_current_state <= csm2_next_state;
         -- Default Assignment To Internals
 
         -- Combined Actions for internal signals only
         CASE csm2_current_state IS
         WHEN i_ready =>
            in_counter_r <= (OTHERS => '0');
         WHEN i_load_row =>
            in_counter_r <= in_counter_r + 1;
         WHEN i_load_column =>
            if (wr_new_data = '1') then
              in_counter_r <= in_counter_r + 1;
            end if;
         WHEN wait_ram_rd =>
            in_counter_r <= in_counter_r + 1;
         WHEN wait_1st_data =>
            if (wr_new_data = '1') then
             in_counter_r <= in_counter_r + 1;
            end if;
         WHEN OTHERS =>
            NULL;
         END CASE;
 
      END IF;
 
   END PROCESS csm2_clocked;
 
   ----------------------------------------------------------------------------
   csm2_nextstate : PROCESS (
      csm2_current_state,
      in_counter_r,
      load_columns,
      load_rows,
      wr_new_data
   )
   ----------------------------------------------------------------------------
   BEGIN
      CASE csm2_current_state IS
      WHEN i_ready =>
         IF (load_columns = '1') THEN
            csm2_next_state <= wait_1st_data;
         ELSIF (load_rows = '1') THEN
            csm2_next_state <= wait_ram_rd;
         ELSE
            csm2_next_state <= i_ready;
         END IF;
      WHEN i_load_row =>
         IF (in_counter_r = 7) THEN
            csm2_next_state <= wait_load;
         ELSE
            csm2_next_state <= i_load_row;
         END IF;
      WHEN i_load_column =>
         IF (in_counter_r = 7 AND wr_new_data = '1') THEN
            csm2_next_state <= i_ready;
         ELSE
            csm2_next_state <= i_load_column;
         END IF;
      WHEN wait_ram_rd =>
            csm2_next_state <= i_load_row;
      WHEN wait_load =>
            csm2_next_state <= i_ready;
      WHEN wait_1st_data =>
         IF (wr_new_data = '1') THEN
            csm2_next_state <= i_load_column;
         ELSE
            csm2_next_state <= wait_1st_data;
         END IF;
      WHEN OTHERS =>
         csm2_next_state <= i_ready;
      END CASE;
 
   END PROCESS csm2_nextstate;
 
   ----------------------------------------------------------------------------
   csm2_output : PROCESS (
      csm2_current_state,
      wr_new_data
   )
   ----------------------------------------------------------------------------
   BEGIN
      -- Default Assignment
      load_dct_input <= '0';
      ready_for_rx <= '0';
      sel_input <= '0';
      -- Default Assignment To Internals
      col_ready <= '0';
 
      -- Combined Actions
      CASE csm2_current_state IS
      WHEN i_ready =>
         col_ready <= '1';
      WHEN i_load_row =>
         sel_input <= '0'; -- load data from ram
         load_dct_input <= '1';
      WHEN i_load_column =>
         sel_input <= '1';
         if (wr_new_data = '1') then
           load_dct_input <= '1';
         end if;
      WHEN wait_ram_rd =>
         sel_input <= '0';
      WHEN wait_load =>
         sel_input <= '0';
         load_dct_input <= '1';
      WHEN wait_1st_data =>
         sel_input <= '1';
         ready_for_rx <= '1';
         if (wr_new_data = '1') then
          load_dct_input <= '1';
         end if;
      WHEN OTHERS =>
         NULL;
      END CASE;
 
   END PROCESS csm2_output;
 
   -- Concurrent Statements
wraddr <= conv_std_logic_vector(row_wr_nr_r & out_counter_r, 6);
rdaddr <= conv_std_logic_vector(in_counter_r & row_rd_nr_r, 6);
 
END fsm;

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Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.accelerator/] [dctqidct/] [1.0/] [hdl/] [dct/] [DCT_control.vhd] - Blame information for rev 145

Line No.	Rev	Author	Line
1	145	lanttu	`------------------------------------------------------------------------------`
2			`-- Author : Timo Alho`
3			`-- e-mail : timo.a.alho@tut.fi`
4			`-- Date : 11.08.2004 13:28:09`
5			`-- File : DCT_control.vhd`
6			`-- Design : VHDL Entity for dct.DCT_control.symbol`
7			`-- Generated by Mentor Graphics' HDL Designer 2003.1 (Build 399)`
8			`------------------------------------------------------------------------------`
9			`LIBRARY ieee;`
10			`USE ieee.std_logic_1164.all;`
11			`USE ieee.std_logic_arith.all;`
12			`LIBRARY dct;`
13			`USE dct.DCT_pkg.all;`
14			`LIBRARY common_da;`
15
16			`ENTITY DCT_control IS`
17			`PORT(`
18			`clk : IN std_logic;`
19			`next_block_ready : IN std_logic;`
20			`rst_n : IN std_logic;`
21			`wr_new_data : IN std_logic;`
22			`DC : OUT std_logic;`
23			`load_dct_input : OUT std_logic;`
24			`load_dct_output : OUT std_logic;`
25			`out_clk_en : OUT std_logic;`
26			`rdaddr : OUT std_logic_vector (5 DOWNTO 0);`
27			`ready_for_rx : OUT std_logic;`
28			`sel_input : OUT std_logic;`
29			`start_dct : OUT std_logic;`
30			`stop_dct : OUT std_logic;`
31			`we : OUT std_logic;`
32			`wr_out : OUT std_logic;`
33			`wraddr : OUT std_logic_vector (5 DOWNTO 0)`
34			`);`
35
36			`-- Declarations`
37
38			`END DCT_control ;`
39
40			`------------------------------------------------------------------------------`
41			`-- Author : Timo Alho`
42			`-- e-mail : timo.a.alho@tut.fi`
43			`-- Date : 11.08.2004 13:28:10`
44			`-- File : DCT_control.vhd`
45			`-- Design : VHDL Architecture for dct.DCT_control.symbol`
46			`-- Generated by Mentor Graphics' HDL Designer 2003.1 (Build 399)`
47			`------------------------------------------------------------------------------`
48			`LIBRARY ieee;`
49			`USE ieee.std_logic_1164.all;`
50			`USE ieee.std_logic_arith.all;`
51			`LIBRARY dct;`
52			`USE dct.DCT_pkg.all;`
53
54			`ARCHITECTURE fsm OF DCT_control IS`
55
56			`-- Architecture Declarations`
57			`signal wait_counter_r : unsigned (4 downto 0);`
58			`signal col_nr_r : unsigned(2 downto 0);`
59			`signal row_rd_nr_r : unsigned(2 downto 0);`
60			`signal row_wr_nr_r : unsigned(2 downto 0);`
61
62			`signal in_counter_r : unsigned(2 downto 0);`
63			`--signal in_counter_next : unsigned(2 downto 0);`
64
65			`signal out_counter_r : unsigned(2 downto 0);`
66			`--signal out_counter_next : unsigned(2 downto 0);`
67
68			`signal output_ready : std_logic;`
69
70			`signal load_rows : std_logic;`
71			`signal load_columns : std_logic;`
72			`signal save_result : std_logic;`
73			`signal result_out : std_logic;`
74			`signal col_ready : std_logic;`
75
76			`TYPE CSM_STATE_TYPE IS (`
77			`start,`
78			`start_col_calc,`
79			`wait_col_calc,`
80			`stop_last_row,`
81			`wait_row_calc,`
82			`wait_data,`
83			`stop_and_start_next_col,`
84			`stop_col_calc,`
85			`stop_last_col,`
86			`dummy0,`
87			`start_row_calc,`
88			`stop_row_calc,`
89			`wait_output_free,`
90			`stop_and_start_next_row,`
91			`dummy1,`
92			`wt_nxt`
93			`);`
94			`TYPE CSM1_STATE_TYPE IS (`
95			`o_ready,`
96			`wr_col_to_ram,`
97			`result_to_buffer,`
98			`result_to_buffer2,`
99			`res_out1,`
100			`wait_output`
101			`);`
102			`TYPE CSM2_STATE_TYPE IS (`
103			`i_ready,`
104			`i_load_row,`
105			`i_load_column,`
106			`wait_ram_rd,`
107			`wait_load,`
108			`wait_1st_data`
109			`);`
110
111
112			`-- Declare current and next state signals`
113			`SIGNAL csm_current_state : CSM_STATE_TYPE ;`
114			`SIGNAL csm_next_state : CSM_STATE_TYPE ;`
115			`SIGNAL csm1_current_state : CSM1_STATE_TYPE ;`
116			`SIGNAL csm1_next_state : CSM1_STATE_TYPE ;`
117			`SIGNAL csm2_current_state : CSM2_STATE_TYPE ;`
118			`SIGNAL csm2_next_state : CSM2_STATE_TYPE ;`
119
120			`-- Declare any pre-registered internal signals`
121			`SIGNAL DC_int : std_logic ;`
122			`SIGNAL wr_out_int : std_logic ;`
123
124			`BEGIN`
125
126			`----------------------------------------------------------------------------`
127			`csm_clocked : PROCESS(`
128			`clk,`
129			`rst_n`
130			`)`
131			`----------------------------------------------------------------------------`
132			`BEGIN`
133			`IF (rst_n = '0') THEN`
134			`csm_current_state <= start;`
135			`-- Reset Values`
136			`col_nr_r <= (others => '0');`
137			`row_rd_nr_r <= (others => '0');`
138			`row_wr_nr_r <= (others => '0');`
139			`wait_counter_r <= (others => '0');`
140			`ELSIF (clk'EVENT AND clk = '1') THEN`
141			`csm_current_state <= csm_next_state;`
142			`-- Default Assignment To Internals`
143
144			`-- Combined Actions for internal signals only`
145			`CASE csm_current_state IS`
146			`WHEN start_col_calc =>`
147			`wait_counter_r <= (others => '0');`
148			`WHEN wait_col_calc =>`
149			`row_rd_nr_r <= (others => '0');`
150			`wait_counter_r <= wait_counter_r + 1;`
151			`WHEN stop_last_row =>`
152			`row_rd_nr_r <= (others => '0');`
153			`col_nr_r <= (others => '0');`
154			`WHEN wait_row_calc =>`
155			`--wait until row is processed`
156			`wait_counter_r <= wait_counter_r + 1;`
157			`WHEN stop_and_start_next_col =>`
158			`col_nr_r <= col_nr_r + 1;`
159			`row_wr_nr_r <= col_nr_r;`
160			`wait_counter_r <= (others => '0');`
161			`WHEN stop_col_calc =>`
162			`col_nr_r <= col_nr_r + 1;`
163			`row_wr_nr_r <= col_nr_r;`
164			`WHEN stop_last_col =>`
165			`col_nr_r <= (others => '0');`
166			`row_wr_nr_r <= col_nr_r;`
167			`wait_counter_r <= (others => '0');`
168			`--load current block's QP parameter to output`
169			`WHEN dummy0 =>`
170			`--wait until last element of first row is read from memory`
171			`wait_counter_r <= wait_counter_r+1;`
172			`WHEN start_row_calc =>`
173			`row_rd_nr_r <= row_rd_nr_r + 1;`
174			`wait_counter_r <= (others => '0');`
175			`WHEN stop_row_calc =>`
176			`--stop calculation of current row`
177			`col_nr_r <= col_nr_r + 1;`
178			`WHEN stop_and_start_next_row =>`
179			`row_rd_nr_r <= row_rd_nr_r + 1;`
180			`col_nr_r <= col_nr_r + 1;`
181			`wait_counter_r <= (others => '0');`
182			`WHEN OTHERS =>`
183			`NULL;`
184			`END CASE;`
185
186			`END IF;`
187
188			`END PROCESS csm_clocked;`
189
190			`----------------------------------------------------------------------------`
191			`csm_nextstate : PROCESS (`
192			`col_nr_r,`
193			`col_ready,`
194			`csm_current_state,`
195			`next_block_ready,`
196			`wait_counter_r`
197			`)`
198			`----------------------------------------------------------------------------`
199			`BEGIN`
200			`CASE csm_current_state IS`
201			`WHEN start =>`
202			`csm_next_state <= wait_data;`
203			`WHEN start_col_calc =>`
204			`csm_next_state <= wait_col_calc;`
205			`WHEN wait_col_calc =>`
206			`IF (col_nr_r =7 AND`
207			`wait_counter_r = DCT_inputw_co) THEN`
208			`csm_next_state <= stop_last_col;`
209			`ELSIF (col_ready = '1' AND`
210			`wait_counter_r = DCT_inputw_co) THEN`
211			`csm_next_state <= stop_and_start_next_col;`
212			`ELSIF (wait_counter_r = DCT_inputw_co) THEN`
213			`csm_next_state <= stop_col_calc;`
214			`ELSE`
215			`csm_next_state <= wait_col_calc;`
216			`END IF;`
217			`WHEN stop_last_row =>`
218			`IF (col_ready = '1' AND next_block_ready = '1') THEN`
219			`csm_next_state <= start_col_calc;`
220			`ELSE`
221			`csm_next_state <= wt_nxt;`
222			`END IF;`
223			`WHEN wait_row_calc =>`
224			`IF (wait_counter_r = DCT_dataw_co AND`
225			`col_nr_r = 7) THEN`
226			`csm_next_state <= stop_last_row;`
227			`ELSIF (wait_counter_r = DCT_dataw_co AND`
228			`next_block_ready = '1') THEN`
229			`csm_next_state <= stop_and_start_next_row;`
230			`ELSIF (wait_counter_r = DCT_dataw_co) THEN`
231			`csm_next_state <= stop_row_calc;`
232			`ELSE`
233			`csm_next_state <= wait_row_calc;`
234			`END IF;`
235			`WHEN wait_data =>`
236			`IF (col_ready = '1') THEN`
237			`csm_next_state <= start_col_calc;`
238			`ELSE`
239			`csm_next_state <= wait_data;`
240			`END IF;`
241			`WHEN stop_and_start_next_col =>`
242			`csm_next_state <= wait_col_calc;`
243			`WHEN stop_col_calc =>`
244			`IF (col_ready = '1') THEN`
245			`csm_next_state <= start_col_calc;`
246			`ELSE`
247			`csm_next_state <= wait_data;`
248			`END IF;`
249			`WHEN stop_last_col =>`
250			`csm_next_state <= dummy0;`
251			`WHEN dummy0 =>`
252			`IF (wait_counter_r = 2) THEN`
253			`csm_next_state <= dummy1;`
254			`ELSE`
255			`csm_next_state <= dummy0;`
256			`END IF;`
257			`WHEN start_row_calc =>`
258			`csm_next_state <= wait_row_calc;`
259			`WHEN stop_row_calc =>`
260			`csm_next_state <= wait_output_free;`
261			`WHEN wait_output_free =>`
262			`IF (next_block_ready = '1') THEN`
263			`csm_next_state <= start_row_calc;`
264			`ELSE`
265			`csm_next_state <= wait_output_free;`
266			`END IF;`
267			`WHEN stop_and_start_next_row =>`
268			`csm_next_state <= wait_row_calc;`
269			`WHEN dummy1 =>`
270			`IF (next_block_ready = '1') THEN`
271			`csm_next_state <= start_row_calc;`
272			`ELSE`
273			`csm_next_state <= dummy1;`
274			`END IF;`
275			`WHEN wt_nxt =>`
276			`IF (next_block_ready = '1') THEN`
277			`csm_next_state <= wait_data;`
278			`ELSE`
279			`csm_next_state <= wt_nxt;`
280			`END IF;`
281			`WHEN OTHERS =>`
282			`csm_next_state <= start;`
283			`END CASE;`
284
285			`END PROCESS csm_nextstate;`
286
287			`----------------------------------------------------------------------------`
288			`csm_output : PROCESS (`
289			`col_nr_r,`
290			`csm_current_state,`
291			`wait_counter_r`
292			`)`
293			`----------------------------------------------------------------------------`
294			`BEGIN`
295			`-- Default Assignment`
296			`start_dct <= '0';`
297			`stop_dct <= '0';`
298			`-- Default Assignment To Internals`
299			`load_columns <= '0';`
300			`load_rows <= '0';`
301			`result_out <= '0';`
302			`save_result <= '0';`
303
304			`-- Combined Actions`
305			`CASE csm_current_state IS`
306			`WHEN start =>`
307			`load_columns <= '1';`
308			`WHEN start_col_calc =>`
309			`--start calculation of column`
310			`start_dct <= '1';`
311			`if (col_nr_r /= 7) then`
312			`load_columns <= '1';`
313			`end if;`
314			`WHEN wait_col_calc =>`
315			`--wait few clock cycles while column is being processed`
316			`if (col_nr_r = 7 AND wait_counter_r = 5) then`
317			`--last column is being processed so we can start loading input "buffer" with values of first row`
318			`load_rows <= '1';`
319			`end if;`
320			`WHEN stop_last_row =>`
321			`--stop calculation of the last row`
322			`stop_dct <= '1';`
323			`result_out <= '1';`
324			`WHEN wait_data =>`
325			`--wait until there is new data available`
326			`WHEN stop_and_start_next_col =>`
327			`--stop calculation of current column, and start calculation of next column`
328			`if (col_nr_r /=6) then`
329			`load_columns <= '1';`
330			`end if;`
331			`start_dct <= '1';`
332			`stop_dct <= '1';`
333			`save_result <= '1';`
334			`WHEN stop_col_calc =>`
335			`--stop calculation of current column`
336			`stop_dct <= '1';`
337			`save_result <= '1';`
338			`WHEN stop_last_col =>`
339			`--stop calculation of last column`
340			`stop_dct <= '1';`
341			`save_result <= '1';`
342			`WHEN start_row_calc =>`
343			`--start calculation of row`
344			`start_dct <= '1';`
345			`if (col_nr_r /=7) then`
346			`load_rows <= '1';`
347			`else`
348			`load_columns <= '1';`
349			`end if;`
350			`WHEN stop_row_calc =>`
351			`stop_dct <= '1';`
352			`result_out <= '1';`
353			`WHEN wait_output_free =>`
354			`--we must wait until next block is capable of receiving data`
355			`WHEN stop_and_start_next_row =>`
356			`--stop calculation of current row, and start next row`
357			`start_dct <= '1';`
358			`stop_dct <= '1';`
359			`result_out <= '1';`
360			`if (col_nr_r /= 6) then`
361			`load_rows <= '1';`
362			`else`
363			`load_columns <= '1';`
364			`end if;`
365			`WHEN OTHERS =>`
366			`NULL;`
367			`END CASE;`
368
369			`END PROCESS csm_output;`
370
371			`----------------------------------------------------------------------------`
372			`csm1_clocked : PROCESS(`
373			`clk,`
374			`rst_n`
375			`)`
376			`----------------------------------------------------------------------------`
377			`BEGIN`
378			`IF (rst_n = '0') THEN`
379			`csm1_current_state <= o_ready;`
380			`-- Reset Values`
381			`DC <= '0';`
382			`wr_out <= '0';`
383			`out_counter_r <= (others => '0');`
384			`ELSIF (clk'EVENT AND clk = '1') THEN`
385			`csm1_current_state <= csm1_next_state;`
386			`-- Registered output assignments`
387			`DC <= DC_int;`
388			`wr_out <= wr_out_int;`
389
390			`-- Default Assignment To Internals`
391
392			`-- Combined Actions for internal signals only`
393			`CASE csm1_current_state IS`
394			`WHEN o_ready =>`
395			`out_counter_r <= (others => '0');`
396			`WHEN wr_col_to_ram =>`
397			`out_counter_r <= out_counter_r + 1;`
398			`WHEN res_out1 =>`
399			`out_counter_r <= out_counter_r + 1;`
400			`WHEN OTHERS =>`
401			`NULL;`
402			`END CASE;`
403
404			`END IF;`
405
406			`END PROCESS csm1_clocked;`
407
408			`----------------------------------------------------------------------------`
409			`csm1_nextstate : PROCESS (`
410			`csm1_current_state,`
411			`next_block_ready,`
412			`out_counter_r,`
413			`result_out,`
414			`save_result`
415			`)`
416			`----------------------------------------------------------------------------`
417			`BEGIN`
418			`CASE csm1_current_state IS`
419			`WHEN o_ready =>`
420			`IF (save_result = '1') THEN`
421			`csm1_next_state <= result_to_buffer;`
422			`ELSIF (result_out = '1') THEN`
423			`csm1_next_state <= result_to_buffer2;`
424			`ELSE`
425			`csm1_next_state <= o_ready;`
426			`END IF;`
427			`WHEN wr_col_to_ram =>`
428			`IF (out_counter_r = 7) THEN`
429			`csm1_next_state <= o_ready;`
430			`ELSE`
431			`csm1_next_state <= wr_col_to_ram;`
432			`END IF;`
433			`WHEN result_to_buffer =>`
434			`csm1_next_state <= wr_col_to_ram;`
435			`WHEN result_to_buffer2 =>`
436			`IF (next_block_ready = '1') THEN`
437			`csm1_next_state <= res_out1;`
438			`ELSE`
439			`csm1_next_state <= wait_output;`
440			`END IF;`
441			`WHEN res_out1 =>`
442			`IF (out_counter_r = 7) THEN`
443			`csm1_next_state <= o_ready;`
444			`ELSE`
445			`csm1_next_state <= res_out1;`
446			`END IF;`
447			`WHEN wait_output =>`
448			`IF (next_block_ready = '1') THEN`
449			`csm1_next_state <= res_out1;`
450			`ELSE`
451			`csm1_next_state <= wait_output;`
452			`END IF;`
453			`WHEN OTHERS =>`
454			`csm1_next_state <= o_ready;`
455			`END CASE;`
456
457			`END PROCESS csm1_nextstate;`
458
459			`----------------------------------------------------------------------------`
460			`csm1_output : PROCESS (`
461			`col_nr_r,`
462			`csm1_current_state,`
463			`out_counter_r`
464			`)`
465			`----------------------------------------------------------------------------`
466			`BEGIN`
467			`-- Default Assignment`
468			`DC_int <= '0';`
469			`load_dct_output <= '0';`
470			`out_clk_en <= '0';`
471			`we <= '0';`
472			`wr_out_int <= '0';`
473			`-- Default Assignment To Internals`
474			`output_ready <= '0';`
475
476			`-- Combined Actions`
477			`CASE csm1_current_state IS`
478			`WHEN o_ready =>`
479			`output_ready <= '1';`
480			`WHEN wr_col_to_ram =>`
481			`we <= '1';`
482			`out_clk_en <= '1';`
483			`WHEN result_to_buffer =>`
484			`load_dct_output <= '1';`
485			`WHEN result_to_buffer2 =>`
486			`load_dct_output <= '1';`
487			`WHEN res_out1 =>`
488			`out_clk_en <= '1';`
489			`wr_out_int <= '1';`
490			`if (col_nr_r = 1 AND out_counter_r = 0) then`
491			`DC_int <= '1';`
492			`end if;`
493			`WHEN OTHERS =>`
494			`NULL;`
495			`END CASE;`
496
497			`END PROCESS csm1_output;`
498
499			`----------------------------------------------------------------------------`
500			`csm2_clocked : PROCESS(`
501			`clk,`
502			`rst_n`
503			`)`
504			`----------------------------------------------------------------------------`
505			`BEGIN`
506			`IF (rst_n = '0') THEN`
507			`csm2_current_state <= i_ready;`
508			`-- Reset Values`
509			`in_counter_r <= (others => '0');`
510			`ELSIF (clk'EVENT AND clk = '1') THEN`
511			`csm2_current_state <= csm2_next_state;`
512			`-- Default Assignment To Internals`
513
514			`-- Combined Actions for internal signals only`
515			`CASE csm2_current_state IS`
516			`WHEN i_ready =>`
517			`in_counter_r <= (OTHERS => '0');`
518			`WHEN i_load_row =>`
519			`in_counter_r <= in_counter_r + 1;`
520			`WHEN i_load_column =>`
521			`if (wr_new_data = '1') then`
522			`in_counter_r <= in_counter_r + 1;`
523			`end if;`
524			`WHEN wait_ram_rd =>`
525			`in_counter_r <= in_counter_r + 1;`
526			`WHEN wait_1st_data =>`
527			`if (wr_new_data = '1') then`
528			`in_counter_r <= in_counter_r + 1;`
529			`end if;`
530			`WHEN OTHERS =>`
531			`NULL;`
532			`END CASE;`
533
534			`END IF;`
535
536			`END PROCESS csm2_clocked;`
537
538			`----------------------------------------------------------------------------`
539			`csm2_nextstate : PROCESS (`
540			`csm2_current_state,`
541			`in_counter_r,`
542			`load_columns,`
543			`load_rows,`
544			`wr_new_data`
545			`)`
546			`----------------------------------------------------------------------------`
547			`BEGIN`
548			`CASE csm2_current_state IS`
549			`WHEN i_ready =>`
550			`IF (load_columns = '1') THEN`
551			`csm2_next_state <= wait_1st_data;`
552			`ELSIF (load_rows = '1') THEN`
553			`csm2_next_state <= wait_ram_rd;`
554			`ELSE`
555			`csm2_next_state <= i_ready;`
556			`END IF;`
557			`WHEN i_load_row =>`
558			`IF (in_counter_r = 7) THEN`
559			`csm2_next_state <= wait_load;`
560			`ELSE`
561			`csm2_next_state <= i_load_row;`
562			`END IF;`
563			`WHEN i_load_column =>`
564			`IF (in_counter_r = 7 AND wr_new_data = '1') THEN`
565			`csm2_next_state <= i_ready;`
566			`ELSE`
567			`csm2_next_state <= i_load_column;`
568			`END IF;`
569			`WHEN wait_ram_rd =>`
570			`csm2_next_state <= i_load_row;`
571			`WHEN wait_load =>`
572			`csm2_next_state <= i_ready;`
573			`WHEN wait_1st_data =>`
574			`IF (wr_new_data = '1') THEN`
575			`csm2_next_state <= i_load_column;`
576			`ELSE`
577			`csm2_next_state <= wait_1st_data;`
578			`END IF;`
579			`WHEN OTHERS =>`
580			`csm2_next_state <= i_ready;`
581			`END CASE;`
582
583			`END PROCESS csm2_nextstate;`
584
585			`----------------------------------------------------------------------------`
586			`csm2_output : PROCESS (`
587			`csm2_current_state,`
588			`wr_new_data`
589			`)`
590			`----------------------------------------------------------------------------`
591			`BEGIN`
592			`-- Default Assignment`
593			`load_dct_input <= '0';`
594			`ready_for_rx <= '0';`
595			`sel_input <= '0';`
596			`-- Default Assignment To Internals`
597			`col_ready <= '0';`
598
599			`-- Combined Actions`
600			`CASE csm2_current_state IS`
601			`WHEN i_ready =>`
602			`col_ready <= '1';`
603			`WHEN i_load_row =>`
604			`sel_input <= '0'; -- load data from ram`
605			`load_dct_input <= '1';`
606			`WHEN i_load_column =>`
607			`sel_input <= '1';`
608			`if (wr_new_data = '1') then`
609			`load_dct_input <= '1';`
610			`end if;`
611			`WHEN wait_ram_rd =>`
612			`sel_input <= '0';`
613			`WHEN wait_load =>`
614			`sel_input <= '0';`
615			`load_dct_input <= '1';`
616			`WHEN wait_1st_data =>`
617			`sel_input <= '1';`
618			`ready_for_rx <= '1';`
619			`if (wr_new_data = '1') then`
620			`load_dct_input <= '1';`
621			`end if;`
622			`WHEN OTHERS =>`
623			`NULL;`
624			`END CASE;`
625
626			`END PROCESS csm2_output;`
627
628			`-- Concurrent Statements`
629			`wraddr <= conv_std_logic_vector(row_wr_nr_r & out_counter_r, 6);`
630			`rdaddr <= conv_std_logic_vector(in_counter_r & row_rd_nr_r, 6);`
631
632			`END fsm;`