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-- Author : Timo Alho
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-- e-mail : timo.a.alho@tut.fi
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-- Date : 21.06.2004 11:33:04
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-- File : Rom_idct_odd.vhd
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-- Design : VHDL Entity Rom_idct_odd.rtl
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------------------------------------------------------------------------------
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-- Description : Pre-calculated 1D-IDCT coefficients for odd-half of idct
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-- kernel
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------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_arith.ALL;
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ENTITY Rom_idct_odd IS
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GENERIC(
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coeffw_g : integer := 14
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);
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PORT(
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addr_in : IN std_logic_vector (3 DOWNTO 0);
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clk : IN std_logic;
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data_out : OUT std_logic_vector (4*coeffw_g-1 DOWNTO 0)
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);
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-- Declarations
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END Rom_idct_odd ;
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--
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ARCHITECTURE rtl OF Rom_idct_odd IS
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TYPE Rom16x4x15 IS ARRAY (0 TO 15) OF signed(15*4-1 DOWNTO 0);
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CONSTANT ROM_IDCT_ODD : Rom16x4x15 := (
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conv_signed(0, 15) & conv_signed(0, 15) & conv_signed(0, 15) & conv_signed(0, 15),
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conv_signed(4096, 15) & conv_signed(4096, 15) & conv_signed(4096, 15) & conv_signed(4096, 15),
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conv_signed(5352, 15) & conv_signed(2217, 15) & conv_signed(-2217, 15) & conv_signed(-5352, 15),
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conv_signed(9448, 15) & conv_signed(6313, 15) & conv_signed(1879, 15) & conv_signed(-1256, 15),
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conv_signed(4096, 15) & conv_signed(-4096, 15) & conv_signed(-4096, 15) & conv_signed(4096, 15),
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conv_signed(8192, 15) & conv_signed(0, 15) & conv_signed(0, 15) & conv_signed(8192, 15),
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conv_signed(9448, 15) & conv_signed(-1879, 15) & conv_signed(-6313, 15) & conv_signed(-1256, 15),
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conv_signed(13544, 15) & conv_signed(2217, 15) & conv_signed(-2217, 15) & conv_signed(2840, 15),
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conv_signed(2217, 15) & conv_signed(-5352, 15) & conv_signed(5352, 15) & conv_signed(-2217, 15),
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conv_signed(6313, 15) & conv_signed(-1256, 15) & conv_signed(9448, 15) & conv_signed(1879, 15),
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conv_signed(7568, 15) & conv_signed(-3135, 15) & conv_signed(3135, 15) & conv_signed(-7568, 15),
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conv_signed(11664, 15) & conv_signed(961, 15) & conv_signed(7231, 15) & conv_signed(-3472, 15),
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conv_signed(6313, 15) & conv_signed(-9448, 15) & conv_signed(1256, 15) & conv_signed(1879, 15),
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conv_signed(10409, 15) & conv_signed(-5352, 15) & conv_signed(5352, 15) & conv_signed(5975, 15),
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conv_signed(11664, 15) & conv_signed(-7231, 15) & conv_signed(-961, 15) & conv_signed(-3472, 15),
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conv_signed(15760, 15) & conv_signed(-3135, 15) & conv_signed(3135, 15) & conv_signed(624, 15));
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SIGNAL addr_r : std_logic_vector(3 DOWNTO 0);
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BEGIN
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clocked : PROCESS (clk)
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BEGIN -- PROCESS clocked
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IF clk'event AND clk = '1' THEN -- rising clock edge
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addr_r <= addr_in;
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END IF;
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END PROCESS clocked;
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access_rom : PROCESS (addr_r)
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VARIABLE address : integer;
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BEGIN
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address := conv_integer(unsigned(addr_r));
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data_out <= conv_std_logic_vector(ROM_IDCT_ODD(address), 4*coeffw_g);
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END PROCESS access_rom;
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END rtl;
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