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Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.communication/] [hibi/] [3.0/] [ip_xact/] [hibi_orbus.3.0.xml] - Blame information for rev 145

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Line No. Rev Author Line
1 145 lanttu
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        TUT
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        ip.hwp.communication
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        hibi_orbus
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        3.0
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                        master
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                        HIBI bus <---> wrapper master interface
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                        false
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                                                AV
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                                                        0
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                                                        0
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                                                bus_av_out
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31 
                                                        0
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                                                        0
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34
35
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37
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                                                COMM
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                                                        4
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                                                        0
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                                                bus_comm_out
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                                                        4
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                                                        0
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52
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                                                DATA
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                                                        31
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                                                        0
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                                                bus_data_out
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                                                        31
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                                                        0
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66
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68
69
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                                                FULL
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                                                        0
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                                                        0
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                                                bus_full_out
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                                                        0
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                                                        0
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                                                LOCK
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                                                        0
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                                                        0
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                                                bus_lock_out
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                                                        0
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                                                        0
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100
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                        8
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                        little
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                        slave_0
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                        HIBI bus <---> wrapper slave interface
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111
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                        false
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                                                AV
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                                                        0
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                                                        0
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                                                bus_av_0_in
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                                                        0
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                                                        0
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128
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131
132 
                                                COMM
133
134 
                                                        4
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                                                        0
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137
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139 
                                                bus_comm_0_in
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                                                        4
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                                                        0
143
144
145
146
147
148 
                                                DATA
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                                                        31
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                                                        0
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153
154
155 
                                                bus_data_0_in
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157 
                                                        31
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                                                        0
159
160
161
162
163
164 
                                                FULL
165
166 
                                                        0
167 
                                                        0
168
169
170
171 
                                                bus_full_0_in
172
173 
                                                        0
174 
                                                        0
175
176
177
178
179
180 
                                                LOCK
181
182 
                                                        0
183 
                                                        0
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185
186
187 
                                                bus_lock_0_in
188
189 
                                                        0
190 
                                                        0
191
192
193
194
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                        8
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                        little
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199 
                        slave_1
200 
                        HIBI bus <---> wrapper slave interface
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202
203
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205
206 
                        false
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208
209
210 
                                                AV
211
212 
                                                        0
213 
                                                        0
214
215
216
217 
                                                bus_av_1_in
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219 
                                                        0
220 
                                                        0
221
222
223
224
225
226 
                                                COMM
227
228 
                                                        4
229 
                                                        0
230
231
232
233 
                                                bus_comm_1_in
234
235 
                                                        4
236 
                                                        0
237
238
239
240
241
242 
                                                DATA
243
244 
                                                        31
245 
                                                        0
246
247
248
249 
                                                bus_data_1_in
250
251 
                                                        31
252 
                                                        0
253
254
255
256
257
258 
                                                FULL
259
260 
                                                        0
261 
                                                        0
262
263
264
265 
                                                bus_full_1_in
266
267 
                                                        0
268 
                                                        0
269
270
271
272
273
274 
                                                LOCK
275
276 
                                                        0
277 
                                                        0
278
279
280
281 
                                                bus_lock_1_in
282
283 
                                                        0
284 
                                                        0
285
286
287
288
289 
                        8
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                        little
291
292
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                        slave_2
294 
                        HIBI bus <---> wrapper slave interface
295
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297
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300 
                        false
301
302
303
304 
                                                AV
305
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                                                        0
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                                                        0
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309
310
311 
                                                bus_av_2_in
312
313 
                                                        0
314 
                                                        0
315
316
317
318
319
320 
                                                COMM
321
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                                                        4
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                                                        0
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325
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327 
                                                bus_comm_2_in
328
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                                                        4
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                                                        0
331
332
333
334
335
336 
                                                DATA
337
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                                                        31
339 
                                                        0
340
341
342
343 
                                                bus_data_2_in
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                                                        31
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                                                        0
347
348
349
350
351
352 
                                                FULL
353
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                                                        0
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                                                        0
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357
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359 
                                                bus_full_2_in
360
361 
                                                        0
362 
                                                        0
363
364
365
366
367
368 
                                                LOCK
369
370 
                                                        0
371 
                                                        0
372
373
374
375 
                                                bus_lock_2_in
376
377 
                                                        0
378 
                                                        0
379
380
381
382
383 
                        8
384 
                        little
385
386
387 
                        slave_3
388 
                        HIBI bus <---> wrapper slave interface
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390
391
392
393
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                        false
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396
397
398 
                                                AV
399
400 
                                                        0
401 
                                                        0
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403
404
405 
                                                bus_av_3_in
406
407 
                                                        0
408 
                                                        0
409
410
411
412
413
414 
                                                COMM
415
416 
                                                        4
417 
                                                        0
418
419
420
421 
                                                bus_comm_3_in
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                                                        4
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                                                        0
425
426
427
428
429
430 
                                                DATA
431
432 
                                                        31
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                                                        0
434
435
436
437 
                                                bus_data_3_in
438
439 
                                                        31
440 
                                                        0
441
442
443
444
445
446 
                                                FULL
447
448 
                                                        0
449 
                                                        0
450
451
452
453 
                                                bus_full_3_in
454
455 
                                                        0
456 
                                                        0
457
458
459
460
461
462 
                                                LOCK
463
464 
                                                        0
465 
                                                        0
466
467
468
469 
                                                bus_lock_3_in
470
471 
                                                        0
472 
                                                        0
473
474
475
476
477 
                        8
478 
                        little
479
480
481
482
483
484 
                                rtl
485 
                                ::
486 
                                hibi_orbus_small
487
488 
                                        hdlSources
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490
491
492
493
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                                bus_av_0_in
495
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                                        in
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498 
                                                0
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                                                0
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501
502 
                                                '0'
503
504
505
506
507
508 
                                bus_av_1_in
509
510 
                                        in
511
512 
                                                0
513 
                                                0
514
515
516 
                                                '0'
517
518
519
520
521
522 
                                bus_av_2_in
523
524 
                                        in
525
526 
                                                '0'
527
528
529
530
531
532 
                                bus_av_3_in
533
534 
                                        in
535
536 
                                                '0'
537
538
539
540
541
542 
                                bus_av_out
543
544 
                                        out
545
546 
                                                0
547 
                                                0
548
549
550
551
552
553 
                                bus_comm_0_in
554
555 
                                        in
556
557 
                                                4
558 
                                                0
559
560
561 
                                                (others => '0')
562
563
564
565
566
567 
                                bus_comm_1_in
568
569 
                                        in
570
571 
                                                4
572 
                                                0
573
574
575 
                                                (others => '0')
576
577
578
579
580
581 
                                bus_comm_2_in
582
583 
                                        in
584
585 
                                                4
586 
                                                0
587
588
589 
                                                (others => '0')
590
591
592
593
594
595 
                                bus_comm_3_in
596
597 
                                        in
598
599 
                                                4
600 
                                                0
601
602
603 
                                                (others => '0')
604
605
606
607
608
609 
                                bus_comm_out
610
611 
                                        out
612
613 
                                                4
614 
                                                0
615
616
617
618
619
620 
                                bus_data_0_in
621
622 
                                        in
623
624 
                                                31
625 
                                                0
626
627
628 
                                                (others => '0')
629
630
631
632
633
634 
                                bus_data_1_in
635
636 
                                        in
637
638 
                                                31
639 
                                                0
640
641
642 
                                                (others => '0')
643
644
645
646
647
648 
                                bus_data_2_in
649
650 
                                        in
651
652 
                                                31
653 
                                                0
654
655
656 
                                                (others => '0')
657
658
659
660
661
662 
                                bus_data_3_in
663
664 
                                        in
665
666 
                                                31
667 
                                                0
668
669
670 
                                                (others => '0')
671
672
673
674
675
676 
                                bus_data_out
677
678 
                                        out
679
680 
                                                31
681 
                                                0
682
683
684
685
686
687 
                                bus_full_0_in
688
689 
                                        in
690
691 
                                                0
692 
                                                0
693
694
695 
                                                '0'
696
697
698
699
700
701 
                                bus_full_1_in
702
703 
                                        in
704
705 
                                                '0'
706
707
708
709
710
711 
                                bus_full_2_in
712
713 
                                        in
714
715 
                                                '0'
716
717
718
719
720
721 
                                bus_full_3_in
722
723 
                                        in
724
725 
                                                '0'
726
727
728
729
730
731 
                                bus_full_out
732
733 
                                        out
734
735 
                                                0
736 
                                                0
737
738
739
740
741
742 
                                bus_lock_0_in
743
744 
                                        in
745
746 
                                                0
747 
                                                0
748
749
750 
                                                '0'
751
752
753
754
755
756 
                                bus_lock_1_in
757
758 
                                        in
759
760 
                                                '0'
761
762
763
764
765
766 
                                bus_lock_2_in
767
768 
                                        in
769
770 
                                                '0'
771
772
773
774
775
776 
                                bus_lock_3_in
777
778 
                                        in
779
780 
                                                '0'
781
782
783
784
785
786 
                                bus_lock_out
787
788 
                                        out
789
790 
                                                0
791 
                                                0
792
793
794
795
796
797
798
799 
                                comm_width_g
800 
                                HIBI command width
801 
                                5
802
803
804 
                                data_width_g
805 
                                HIBI data width
806 
                                32
807
808
809
810
811
812 
                        hdlSources
813 
                        VHDL for HIBI orbus to connect four hibi wrappers
814
815 
                                ../vhd/hibi_orbus_small.vhd
816 
                                vhdlSource
817 
                                false
818 
                                hibi
819
820
821 
                                vhdlSource
822 
                                vcom
823 
                                 -work hibi -check_synthesis -quiet
824 
                                false
825
826
827
828
829
830
831 
                                IP
832 
                                HW
833 
                                Parameterizable
834
835
836
837

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