OpenCores
URL https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk

Subversion Repositories funbase_ip_library

[/] [funbase_ip_library/] [trunk/] [TUT/] [ip.hwp.communication/] [n2h2/] [1.0/] [tb/] [system/] [src_cpu1/] [main.c] - Blame information for rev 145

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 145 lanttu 
/*
2 
 * main.c
3 
 *
4 
 *  Created on: 22.2.2011
5 
 *      Author: lehton87
6 
 */
7 
 
8 
#include <stdio.h>
9 
#include <stdlib.h>
10 
#include <string.h>
11 
#include <io.h>
12 
#include <unistd.h>
13 
 
14 
#include "system.h"
15 
#include "N2H_registers_and_macros.h"
16 
#include "tut_n2h_regs.h"
17 
#include "n2h_isr_fifo.h"
18 
 
19 
#include "support.h"
20 
 
21 
 
22 
int main()
23 
{
24 
  int n_received = 0;
25 
  int rx_data[20];
26 
  int rx_amount = 8;
27 
  int tx_amount = 8;
28 
  int send      = 0;
29 
 
30 
  int channels[8] = {0, 0, 0, 0, 0, 0, 0, 0};
31 
 
32 
  N2H_isr_fifo* n2h_isr_fifo = n2h_isr_fifo_create();
33 
 
34 
  // Init N2H interrupt
35 
  n2h_isr_init(n2h_isr_fifo);
36 
 
37 
  int tx_data1[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08};
38 
  int tx_data2[] = {0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18};
39 
  int tx_data3[] = {0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28};
40 
  int tx_data4[] = {0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38};
41 
 
42 
  usleep(20);
43 
 
44 
  printf("CPU1: starts\n");
45 
 
46 
  memcpy((int*)N2H_REGISTERS_TX_BUFFER_START, (int*)tx_data1,
47 
         tx_amount*sizeof(int));
48 
 
49 
  memcpy((int*)(N2H_REGISTERS_TX_BUFFER_START + tx_amount*sizeof(int)),
50 
         (int*)tx_data2, tx_amount*sizeof(int));
51 
 
52 
  memcpy((int*)(N2H_REGISTERS_TX_BUFFER_START + 2*tx_amount*sizeof(int)),
53 
         (int*)tx_data3, tx_amount*sizeof(int));
54 
 
55 
  memcpy((int*)(N2H_REGISTERS_TX_BUFFER_START + 3*tx_amount*sizeof(int)),
56 
         (int*)tx_data4, tx_amount*sizeof(int));
57 
 
58 
 
59 
  //
60 
  // Add/remove some these sends if you want more/less traffic
61 
  //
62 
 
63 
  // poll until tx is empty and then send
64 
  while(((IORD(N2H2_CHAN_BASE, 4) >> 16) & 0x1) == 0) {/* idle */}
65 
  n2h_send(N2H_REGISTERS_TX_BUFFER_START, tx_amount, 0x001);
66 
 
67 
  /*
68 
 
69 
  while(((IORD(N2H2_CHAN_BASE, 4) >> 16) & 0x1) == 0) {}
70 
  n2h_send(N2H_REGISTERS_TX_BUFFER_START, tx_amount, 0x401);
71 
 
72 
  while(((IORD(N2H2_CHAN_BASE, 4) >> 16) & 0x1) == 0) {}
73 
  n2h_send(N2H_REGISTERS_TX_BUFFER_START + tx_amount*sizeof(int),
74 
           tx_amount, 0x000);
75 
 
76 
  while(((IORD(N2H2_CHAN_BASE, 4) >> 16) & 0x1) == 0) {}
77 
  n2h_send(N2H_REGISTERS_TX_BUFFER_START + tx_amount*sizeof(int),
78 
           tx_amount, 0x400);
79 
 
80 
  while(((IORD(N2H2_CHAN_BASE, 4) >> 16) & 0x1) == 0) {}
81 
  n2h_send(N2H_REGISTERS_TX_BUFFER_START + 2*tx_amount*sizeof(int),
82 
           tx_amount, 0x002);
83 
 
84 
  while(((IORD(N2H2_CHAN_BASE, 4) >> 16) & 0x1) == 0) {}
85 
  n2h_send(N2H_REGISTERS_TX_BUFFER_START + 2*tx_amount*sizeof(int),
86 
           tx_amount, 0x402);
87 
 
88 
  while(((IORD(N2H2_CHAN_BASE, 4) >> 16) & 0x1) == 0) {}
89 
  n2h_send(N2H_REGISTERS_TX_BUFFER_START + 3*tx_amount*sizeof(int),
90 
           tx_amount, 0x003);
91 
 
92 
  while(((IORD(N2H2_CHAN_BASE, 4) >> 16) & 0x1) == 0) {}
93 
  n2h_send(N2H_REGISTERS_TX_BUFFER_START + 3*tx_amount*sizeof(int),
94 
           tx_amount, 0x403);
95 
  */
96 
 
97 
  //
98 
 
99 
  while(1)
100 
    {
101 
      if(n2h_isr_fifo_size(n2h_isr_fifo))
102 
        {
103 
          N2H_isr_info* info = n2h_isr_fifo_pop(n2h_isr_fifo);
104 
 
105 
          switch(info->isr_type)
106 
            {
107 
            case RX_READY:
108 
 
109 
              printf("CPU1: received %ith packet to channel %i\n",
110 
                     ++n_received, info->rx_channel);
111 
 
112 
 
113 
              if(channels[info->rx_channel] == 2)
114 
                {
115 
                  channels[info->rx_channel] = 0;
116 
                  break;
117 
                }
118 
 
119 
              memcpy((int*)rx_data, (int*)(N2H_REGISTERS_RX_BUFFER_START +
120 
                                           info->rx_channel * rx_amount*
121 
                                           sizeof(int)),
122 
                     rx_amount*sizeof(int));
123 
 
124 
              printf("CPU1: read data from channel %i : %X %X %X %X %X "
125 
                     "%X %X %X\n",
126 
                     info->rx_channel, rx_data[0], rx_data[1], rx_data[2],
127 
                     rx_data[3], rx_data[4], rx_data[5], rx_data[6],
128 
                     rx_data[7]);
129 
 
130 
              channels[info->rx_channel] = 0;
131 
 
132 
              // Init rx chan half the time
133 
              int src = (rand() % 2 == 0) ? 0x00 : 0x20;
134 
              if(rand() % 2 == 0)
135 
                {
136 
                  int i = 0;
137 
 
138 
                  for(i = 0; i < 5; ++i)
139 
                    {
140 
                      if(channels[i] == 0)
141 
                        {
142 
                          channels[i] = 1;
143 
                          n2h_init_rx(i, 8*i*sizeof(int), 8, 0x200 + i + src);
144 
                          break;
145 
                        }
146 
                    }
147 
                }
148 
 
149 
              send++;
150 
 
151 
              int fre = 0;
152 
              int x = 0;
153 
              for(; x < 8; ++x) {if(channels[x]== 0) fre++;}
154 
              printf("CPU1: %i to send, %i in FIFO, %i channels free\n",
155 
                     send, n2h_isr_fifo_size(n2h_isr_fifo), fre);
156 
 
157 
              break;
158 
 
159 
            case RX_UNKNOWN:
160 
              {
161 
                int cha = 0;
162 
 
163 
                for(cha = 0; cha < 8; ++cha)
164 
                  {
165 
                    if(channels[cha] == 0)
166 
                      {
167 
                        channels[cha] = (info->dst_address == 0x3FF) ? 2 : 1;
168 
 
169 
                        printf("CPU1: received data to unconfigured "
170 
                               "address 0x%X, assigning to channel %i\n",
171 
                       info->dst_address, cha);
172 
 
173 
                        if(!(0x200 <= info->dst_address &&
174 
                             info->dst_address <= 0x3FF))
175 
                          {
176 
                            printf("CPU1: %i is invalid address, FAILURE\n",
177 
                                   info->dst_address);
178 
                          }
179 
 
180 
                        // Initialize some channel to receive
181 
                        n2h_init_rx(cha, cha * rx_amount*sizeof(int), rx_amount,
182 
                                    info->dst_address);
183 
 
184 
                        break;
185 
                      }
186 
                  }
187 
 
188 
                int fre = 0;
189 
                int x = 0;
190 
                for(; x < 8; ++x) {if(channels[x]== 0) fre++;}
191 
                printf("CPU1: %i to send, %i in FIFO, %i channels free\n",
192 
                       send, n2h_isr_fifo_size(n2h_isr_fifo), fre);
193 
 
194 
              }
195 
              break;
196 
 
197 
            case TX_IGNORED:
198 
              {
199 
                printf("CPU1: A transfer was ignored because it overlapped"
200 
                       " previous one\n");
201 
 
202 
                int fre = 0;
203 
                int x = 0;
204 
                for(; x < 8; ++x) {if(channels[x]== 0) fre++;}
205 
                printf("CPU1: %i to send, %i in FIFO, %i channels free\n",
206 
                       send, n2h_isr_fifo_size(n2h_isr_fifo), fre);
207 
              }
208 
              break;
209 
 
210 
            }
211 
 
212 
          // Free memory
213 
          free(info); info = NULL;
214 
        }
215 
      else if(send > 0 && (((IORD(N2H2_CHAN_BASE, 4) >> 16) & 0x1) == 1))
216 
        {
217 
          // Send packet to a random target's random address
218 
          int target_addr;
219 
          int tx_data[8];
220 
          int tx_slot = (rand() % 8);
221 
          int cha;
222 
 
223 
          if(rand() % 2 == 0)
224 
            {
225 
              target_addr = 0x010 + tx_slot;
226 
            }
227 
          else
228 
            {
229 
              target_addr = 0x410 + tx_slot;
230 
            }
231 
 
232 
          for(cha = 0; cha < 8; ++cha)
233 
            tx_data[cha] = 0x81000000 | ((cha+1) << 16) | target_addr;
234 
 
235 
          memcpy((int*)(N2H_REGISTERS_TX_BUFFER_START +
236 
                        tx_slot*tx_amount*sizeof(int)),
237 
                 (int*)tx_data, tx_amount*sizeof(int));
238 
 
239 
          printf("CPU1: sending packet to 0x%X\n", target_addr);
240 
 
241 
          n2h_send(N2H_REGISTERS_TX_BUFFER_START +
242 
                   tx_slot*tx_amount*sizeof(int),
243 
                   tx_amount, target_addr);
244 
 
245 
          send--;
246 
 
247 
 
248 
          // Overlapping with previous one hopefully
249 
          if((rand() % 100) < 50)
250 
            {
251 
              n2h_send(N2H_REGISTERS_TX_BUFFER_START +
252 
                       tx_slot*tx_amount*sizeof(int),
253 
                       tx_amount, 0x5FF);
254 
              printf("CPU1: sending hazard packet\n");
255 
            }
256 
          int fre = 0;
257 
          int x = 0;
258 
          for(; x < 8; ++x) {if(channels[x]== 0) fre++;}
259 
          printf("CPU1: %i to send, %i in FIFO, %i channels free\n",
260 
                 send, n2h_isr_fifo_size(n2h_isr_fifo), fre);
261 
        }
262 
    }
263 
 
264 
  //
265 
 
266 
  printf("CPU1: retires!\n");
267 
  while(1); return 0;
268 
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.