URL https://opencores.org/ocsvn/ha1588/ha1588/trunk

Subversion Repositories ha1588

[/] [ha1588/] [trunk/] [sys/] [altera_qsys/] [system.qsys] - Blame information for rev 75

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   name="$${FILENAME}"
   displayName="$${FILENAME}"
   version="1.0"
   description=""
   tags=""
   categories="System" />
 
{
   element $${FILENAME}
   {
   }
   element clk_0
   {
      datum _sortIndex
      {
         value = "0";
         type = "int";
      }
   }
   element ha1588_avl_0
   {
      datum _sortIndex
      {
         value = "1";
         type = "int";
      }
   }
   element mgc_axi4_inline_monitor_0
   {
      datum _sortIndex
      {
         value = "4";
         type = "int";
      }
   }
   element mgc_axi4_master_0
   {
      datum _sortIndex
      {
         value = "2";
         type = "int";
      }
   }
   element mgc_axi4_slave_0
   {
      datum _sortIndex
      {
         value = "3";
         type = "int";
      }
   }
   element ha1588_avl_0.reg_interface
   {
      datum baseAddress
      {
         value = "65536";
         type = "String";
      }
   }
}
]]>
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
   name="ha1588_avl_0_rtc_interface"
   internal="ha1588_avl_0.rtc_interface"
   type="conduit"
   dir="end" />
 
   name="ha1588_avl_0_tsu_interface"
   internal="ha1588_avl_0.tsu_interface"
   type="conduit"
   dir="end" />
 
   name="clk_0_clk_in_reset"
   internal="clk_0.clk_in_reset"
   type="reset"
   dir="end" />
 
  
  
  
  
 
 
  
  
 
 
   kind="mgc_axi4_master"
   version="10.1.3.1"
   enabled="1"
   name="mgc_axi4_master_0">
  
  
  
  
  
  
  
  
 
 
   kind="mgc_axi4_inline_monitor"
   version="10.1.3.1"
   enabled="1"
   name="mgc_axi4_inline_monitor_0">
  
  
  
  
  
  
  
  
 
 
   kind="mgc_axi4_slave"
   version="10.1.3.1"
   enabled="1"
   name="mgc_axi4_slave_0">
  
  
  
  
  
  
  
  
 
 
   kind="clock"
   version="12.1"
   start="clk_0.clk"
   end="ha1588_avl_0.clock" />
 
   kind="reset"
   version="12.1"
   start="clk_0.clk_reset"
   end="ha1588_avl_0.clock_reset" />
 
   kind="avalon"
   version="12.1"
   start="mgc_axi4_master_0.altera_axi4_master"
   end="ha1588_avl_0.reg_interface">
  
  
 
 
   kind="clock"
   version="12.1"
   start="clk_0.clk"
   end="mgc_axi4_master_0.clock_sink" />
 
   kind="reset"
   version="12.1"
   start="clk_0.clk_reset"
   end="mgc_axi4_master_0.reset_sink" />
 
   kind="clock"
   version="12.1"
   start="clk_0.clk"
   end="mgc_axi4_inline_monitor_0.clock_sink" />
 
   kind="reset"
   version="12.1"
   start="clk_0.clk_reset"
   end="mgc_axi4_inline_monitor_0.reset_sink" />
 
   kind="avalon"
   version="12.1"
   start="mgc_axi4_inline_monitor_0.altera_axi4_master"
   end="ha1588_avl_0.reg_interface">
  
  
 
 
   kind="clock"
   version="12.1"
   start="clk_0.clk"
   end="mgc_axi4_slave_0.clock_sink" />
 
   kind="reset"
   version="12.1"
   start="clk_0.clk_reset"
   end="mgc_axi4_slave_0.reset_sink" />
 
   kind="avalon"
   version="12.1"
   start="mgc_axi4_master_0.altera_axi4_master"
   end="mgc_axi4_slave_0.altera_axi4_slave">
  
  
 


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Subversion Repositories ha1588

[/] [ha1588/] [trunk/] [sys/] [altera_qsys/] [system.qsys] - Blame information for rev 75

Line No.	Rev	Author	Line
1	73	ash_riple
2
3
4			`name="$${FILENAME}"`
5			`displayName="$${FILENAME}"`
6			`version="1.0"`
7			`description=""`
8			`tags=""`
9			`categories="System" />`
10
11			`{`
12			`element $${FILENAME}`
13			`{`
14			`}`
15			`element clk_0`
16			`{`
17			`datum _sortIndex`
18			`{`
19			`value = "0";`
20			`type = "int";`
21			`}`
22			`}`
23			`element ha1588_avl_0`
24			`{`
25			`datum _sortIndex`
26			`{`
27			`value = "1";`
28			`type = "int";`
29			`}`
30			`}`
31			`element mgc_axi4_inline_monitor_0`
32			`{`
33			`datum _sortIndex`
34			`{`
35			`value = "4";`
36			`type = "int";`
37			`}`
38			`}`
39			`element mgc_axi4_master_0`
40			`{`
41			`datum _sortIndex`
42			`{`
43			`value = "2";`
44			`type = "int";`
45			`}`
46			`}`
47			`element mgc_axi4_slave_0`
48			`{`
49			`datum _sortIndex`
50			`{`
51			`value = "3";`
52			`type = "int";`
53			`}`
54			`}`
55			`element ha1588_avl_0.reg_interface`
56			`{`
57			`datum baseAddress`
58			`{`
59			`value = "65536";`
60			`type = "String";`
61			`}`
62			`}`
63			`}`
64			`]]>`
65
66
67
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69
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82
83			`name="ha1588_avl_0_rtc_interface"`
84			`internal="ha1588_avl_0.rtc_interface"`
85			`type="conduit"`
86			`dir="end" />`
87
88			`name="ha1588_avl_0_tsu_interface"`
89			`internal="ha1588_avl_0.tsu_interface"`
90			`type="conduit"`
91			`dir="end" />`
92
93			`name="clk_0_clk_in_reset"`
94			`internal="clk_0.clk_in_reset"`
95			`type="reset"`
96			`dir="end" />`
97
98
99
100
101
102
103
104
105
106
107
108			`kind="mgc_axi4_master"`
109			`version="10.1.3.1"`
110			`enabled="1"`
111			`name="mgc_axi4_master_0">`
112
113
114
115
116
117
118
119
120
121
122			`kind="mgc_axi4_inline_monitor"`
123			`version="10.1.3.1"`
124			`enabled="1"`
125			`name="mgc_axi4_inline_monitor_0">`
126
127
128
129
130
131
132
133
134
135
136			`kind="mgc_axi4_slave"`
137			`version="10.1.3.1"`
138			`enabled="1"`
139			`name="mgc_axi4_slave_0">`
140
141
142
143
144
145
146
147
148
149
150			`kind="clock"`
151			`version="12.1"`
152			`start="clk_0.clk"`
153			`end="ha1588_avl_0.clock" />`
154
155			`kind="reset"`
156			`version="12.1"`
157			`start="clk_0.clk_reset"`
158			`end="ha1588_avl_0.clock_reset" />`
159
160			`kind="avalon"`
161			`version="12.1"`
162			`start="mgc_axi4_master_0.altera_axi4_master"`
163			`end="ha1588_avl_0.reg_interface">`
164
165
166
167
168			`kind="clock"`
169			`version="12.1"`
170			`start="clk_0.clk"`
171			`end="mgc_axi4_master_0.clock_sink" />`
172
173			`kind="reset"`
174			`version="12.1"`
175			`start="clk_0.clk_reset"`
176			`end="mgc_axi4_master_0.reset_sink" />`
177
178			`kind="clock"`
179			`version="12.1"`
180			`start="clk_0.clk"`
181			`end="mgc_axi4_inline_monitor_0.clock_sink" />`
182
183			`kind="reset"`
184			`version="12.1"`
185			`start="clk_0.clk_reset"`
186			`end="mgc_axi4_inline_monitor_0.reset_sink" />`
187
188			`kind="avalon"`
189			`version="12.1"`
190			`start="mgc_axi4_inline_monitor_0.altera_axi4_master"`
191			`end="ha1588_avl_0.reg_interface">`
192
193
194
195
196			`kind="clock"`
197			`version="12.1"`
198			`start="clk_0.clk"`
199			`end="mgc_axi4_slave_0.clock_sink" />`
200
201			`kind="reset"`
202			`version="12.1"`
203			`start="clk_0.clk_reset"`
204			`end="mgc_axi4_slave_0.reset_sink" />`
205
206			`kind="avalon"`
207			`version="12.1"`
208			`start="mgc_axi4_master_0.altera_axi4_master"`
209			`end="mgc_axi4_slave_0.altera_axi4_slave">`
210
211
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