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-- VHDL data flow description generated from `fsub_bopo`

--              date : Sat Sep  8 02:00:55 2001

-- Entity Declaration

ENTITY fsub_bopo IS

  PORT (

  a : in BIT;   -- a

  b : in BIT;   -- b

  bin : in BIT; -- bin

  d : out BIT;  -- d

  bout : out BIT;       -- bout

  vdd : in BIT; -- vdd

  vss : in BIT  -- vss

  );

END fsub_bopo;

-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF fsub_bopo IS

BEGIN

  ASSERT ((vdd and not (vss)) = '1')

    REPORT "power supply is missing on fsub1"

    SEVERITY WARNING;

bout <= ((not (a) and b) or (bin and (not (a) or b)));

d <= (a xor b xor bin);

END;