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-- VHDL data flow description generated from `control_dataout`

--              date : Mon Aug 27 07:31:43 2001

-- Entity Declaration

ENTITY control_dataout IS

  PORT (

  clk : in BIT; -- clk

  rst : in BIT; -- rst

  cp_ready : in BIT;    -- cp_ready

  emp_bufout : in BIT;  -- emp_bufout

  en_bufout : out BIT;  -- en_bufout

  req_cp : out BIT;     -- req_cp

  cp_sended : out BIT;  -- cp_sended

  n_block : out BIT;    -- n_block

  vdd : in BIT; -- vdd

  vss : in BIT  -- vss

  );

END control_dataout;

-- Architecture Declaration

ARCHITECTURE VBE OF control_dataout IS

  SIGNAL current_state : REG_VECTOR(2 DOWNTO 0) REGISTER;       -- current_state

  SIGNAL current_state_s4 : BIT;                -- current_state_s4

  SIGNAL next_state_s4 : BIT;           -- next_state_s4

  SIGNAL current_state_s3 : BIT;                -- current_state_s3

  SIGNAL next_state_s3 : BIT;           -- next_state_s3

  SIGNAL current_state_s2 : BIT;                -- current_state_s2

  SIGNAL next_state_s2 : BIT;           -- next_state_s2

  SIGNAL current_state_s1 : BIT;                -- current_state_s1

  SIGNAL next_state_s1 : BIT;           -- next_state_s1

  SIGNAL current_state_s0 : BIT;                -- current_state_s0

  SIGNAL next_state_s0 : BIT;           -- next_state_s0

  SIGNAL next_state : BIT_VECTOR(2 DOWNTO 0);   -- next_state

BEGIN

  next_state(0) <= next_state_s4;

  next_state(1) <= (next_state_s2 OR next_state_s3);

  next_state(2) <= (next_state_s1 OR next_state_s3);

  next_state_s0 <= ((current_state_s0 AND NOT(cp_ready)) OR (

current_state_s4 AND emp_bufout));

  current_state_s0 <= (NOT(current_state(2)) AND NOT(current_state(1))

AND NOT(current_state(0)));

  next_state_s1 <= (current_state_s0 AND cp_ready);

  current_state_s1 <= (current_state(2) AND NOT(current_state(1)));

  next_state_s2 <= (current_state_s1 OR (current_state_s2 AND NOT(

emp_bufout)));

  current_state_s2 <= (NOT(current_state(2)) AND current_state(1));

  next_state_s3 <= (current_state_s2 AND emp_bufout);

  current_state_s3 <= (current_state(2) AND current_state(1));

  next_state_s4 <= (current_state_s3 OR (current_state_s4 AND NOT(

emp_bufout)));

  current_state_s4 <= current_state(0);

  label0 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1')

  BEGIN

    current_state(0) <= GUARDED (next_state(0) AND NOT(rst));

  END BLOCK label0;

  label1 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1')

  BEGIN

    current_state(1) <= GUARDED (next_state(1) AND NOT(rst));

  END BLOCK label1;

  label2 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1')

  BEGIN

    current_state(2) <= GUARDED (next_state(2) AND NOT(rst));

  END BLOCK label2;

n_block <= ((current_state_s1 AND NOT(rst)) OR (

current_state_s2 AND NOT(rst)));

cp_sended <= NOT(rst OR (current_state_s0 AND NOT(rst)) OR (

current_state_s2 AND NOT(rst) AND emp_bufout) OR (

current_state_s4 AND NOT(rst) AND emp_bufout));

req_cp <= (rst OR (current_state_s0 AND NOT(rst) AND NOT(

cp_ready)) OR (current_state_s4 AND NOT(rst) AND

emp_bufout));

en_bufout <= ((current_state_s0 AND NOT(rst) AND cp_ready) OR

(current_state_s2 AND NOT(rst) AND emp_bufout));

END;