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--   File Name    : dec1to4.vbe                               --

--   Description  : The 32-bit 1-to-4 decoder                 --

--   Purpose      : To be used by ASIMUT and SCMAP            --

--   Date         : Aug 30, 2001                              --

--   Version      : 1.1                                       --

--   Author       : Sigit Dewantoro                            --

--   Address      : VLSI RG, Dept. of Electrical Engineering  --

--                  ITB, Bandung, Indonesia                   --

--   E-mail       : sigit@vlsi.itb.ac.id                      --

entity dec1to3 is

port(

  a       : in       bit_vector(31 downto 0);

  sel     : in       bit_vector(1 downto 0);

  clk     : in       bit;

  rst     : in       bit;

  o1,o2,o3,o4   : out      bit_vector(31 downto 0);

  vdd     : in       bit;

  vss     : in       bit

  );

end dec1to3;

architecture vbe of dec1to3 is

signal reg1   : reg_vector(31 downto 0) register;

signal reg2   : reg_vector(31 downto 0) register;

signal reg3   : reg_vector(31 downto 0) register;

signal reg4   : reg_vectro (31 downto 0) register;

signal o11    : bit_vector(31 downto 0);

signal o22    : bit_vector(31 downto 0);

signal o33    : bit_vectro(31 downto 0);

signal o44    : bit_vector (31 downto 0);

begin

  assert ((vdd and not (vss)) = '1')

    report "power supply is missing on dec1to2"

    severity warning;

  o11 <= a when(sel="00") else not reg1;

  o22 <= a when(sel="01") else not reg2;

  o33 <= a when(sel="10") else not reg3;

  o44 <= a when (sel="11") else not reg4;

  REG1 : BLOCK ((clk = '1') and not clk'STABLE)

     BEGIN

     reg1 <= GUARDED X"1111_1111" when(rst='1') else not o11;

  END BLOCK REG1;

  REG2 : BLOCK ((clk = '1') and not clk'STABLE)

     BEGIN

     reg2 <= GUARDED X"1111_1111" when(rst='1') else not o22;

  END BLOCK REG2;

  REG3: BLOCK ((clk = '1' and not clk'STABLE)

        BEGIN

        reg3 < GUARDED X"1111_1111" when (rst) else not o33;

 END BLOCK REG3;

  REG4: BLOCK ((clk = '1' and not clk'stable)

        begin

        reg4 <= guarded X"1111_1111" when rst else not o44;

 end block reg4;

  o1 <= not reg1;

  o2 <= not reg2;

  o3 <= not reg3;

  o4 <= not reg4;

end;