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-- VHDL data flow description generated from `in_key_bop`

--              date : Sat Sep  1 20:10:30 2001

-- Entity Declaration

ENTITY in_key_bop IS

  PORT (

  clk : in BIT; -- clk

  rst : in BIT; -- rst

  key_sended : in BIT;  -- key_sended

  en_bufin : out BIT;   -- en_bufin

  req_key : out BIT;    -- req_key

  ikey_ready : out BIT; -- ikey_ready

  n_block : out BIT;    -- n_block

  vdd : in BIT; -- vdd

  vss : in BIT  -- vss

  );

END in_key_bop;

-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF in_key_bop IS

  SIGNAL current_state : REG_VECTOR(2 DOWNTO 0) REGISTER;       -- current_state

  SIGNAL aux6 : BIT;            -- aux6

  SIGNAL auxinit1 : BIT;                -- auxinit1

BEGIN

  auxinit1 <= (not (current_state (2)) and not (rst) and key_sended and not

((current_state (1) and current_state (0))));

  aux6 <= (not (rst) and (not (current_state (0)) or current_state (2)));

  label0 : BLOCK ((clk and not (clk'STABLE)) = '1')

  BEGIN

    current_state (0) <= GUARDED ((not (current_state (0)) and not (current_state (1)) and current_state

(2)) or not (aux6));

  END BLOCK label0;

  label1 : BLOCK ((clk and not (clk'STABLE)) = '1')

  BEGIN

    current_state (1) <= GUARDED ((not (rst) and not (current_state (1)) and current_state (2))

or (not (current_state (0)) and not (rst) and not (current_state

(2)) and current_state (1)));

  END BLOCK label1;

  label2 : BLOCK ((clk and not (clk'STABLE)) = '1')

  BEGIN

    current_state (2) <= GUARDED auxinit1;

  END BLOCK label2;

n_block <= aux6;

ikey_ready <= (not (rst) and current_state (0) and not (current_state (2))

and current_state (1));

req_key <= (rst or current_state (2) or (not (key_sended) and not ((current_state

(1) and current_state (0)))));

en_bufin <= auxinit1;

END;