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-- VHDL data flow description generated from `ecb_bop`

--              date : Sat Sep  1 20:15:14 2001

-- Entity Declaration

ENTITY ecb_bop IS

  PORT (

  active : in BIT;      -- active

  clk : in BIT; -- clk

  cke : in BIT; -- cke

  key_ready : in BIT;   -- key_ready

  finish : in BIT;      -- finish

  req_cp : in BIT;      -- req_cp

  e : in BIT;   -- e

  e_mesin : out BIT;    -- e_mesin

  s_mesin : out BIT;    -- s_mesin

  s_gen_key : out BIT;  -- s_gen_key

  emp_buf : out BIT;    -- emp_buf

  cp_ready : out BIT;   -- cp_ready

  cke_b_mode : out BIT; -- cke_b_mode

  en_in : out BIT;      -- en_in

  en_iv : out BIT;      -- en_iv

  en_rcbc : out BIT;    -- en_rcbc

  en_out : out BIT;     -- en_out

  sel1 : out bit_vector(1 DOWNTO 0) ;   -- sel1

  sel2 : out bit_vector(1 DOWNTO 0) ;   -- sel2

  sel3 : out bit_vector(1 DOWNTO 0) ;   -- sel3

  vdd : in BIT; -- vdd

  vss : in BIT  -- vss

  );

END ecb_bop;

-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF ecb_bop IS

  SIGNAL current_state : REG_VECTOR(2 DOWNTO 0) REGISTER;       -- current_state

  SIGNAL aux16 : BIT;           -- aux16

  SIGNAL aux14 : BIT;           -- aux14

  SIGNAL auxinit1 : BIT;                -- auxinit1

  SIGNAL auxinit2 : BIT;                -- auxinit2

  SIGNAL aux18 : BIT;           -- aux18

  SIGNAL aux19 : BIT;           -- aux19

BEGIN

  aux19 <= (not (current_state (2)) or (not (req_cp) and current_state (0)));

  aux18 <= (not (active) and current_state (1));

  auxinit2 <= (not (active) and not (current_state (2)) and (current_state

(0) or not ((finish or current_state (1)))));

  auxinit1 <= (not (active) and (not (current_state (2)) or cke or current_state

(1) or current_state (0)));

  aux14 <= (not (active) and (not (current_state (2)) or current_state (0)));

  aux16 <= (key_ready and not ((not (current_state (2)) or current_state

(0))));

  label0 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')

  BEGIN

    current_state (0) <= GUARDED (not (active) and ((current_state (2) and current_state (0))

or (current_state (1) and (not (current_state (2)) or key_ready))));

  END BLOCK label0;

  label1 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')

  BEGIN

    current_state (1) <= GUARDED ((not (active) and not ((current_state (1) or current_state (0)))

and ((cke and current_state (2)) or (not (current_state (2))

and finish))) or (aux18 and ((not (current_state (0)) and not

(key_ready)) or aux19)));

  END BLOCK label1;

  label2 : BLOCK ((not (clk) and not (clk'STABLE)) = '1')

  BEGIN

    current_state (2) <= GUARDED (active or (not (current_state (1)) and current_state (2)) or

(current_state (1) and not (aux16)));

  END BLOCK label2;

sel3 (0) <= '0';

sel3 (1) <= '1';

sel2 (0) <= '0';

sel2 (1) <= '1';

sel1 (0) <= aux14;

sel1 (1) <= not (aux14);

en_out <= (not (active) and not (current_state (1)) and not (current_state

(0)) and not (current_state (2)) and finish);

en_rcbc <= '0';

en_iv <= '0';

en_in <= (aux18 and aux16);

cke_b_mode <= auxinit1;

cp_ready <= (aux18 and aux19);

emp_buf <= auxinit2;

s_gen_key <= auxinit1;

s_mesin <= auxinit2;

e_mesin <= e;

END;