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-- File Name    : ecb.fsm
-- Version      : v1.2
-- Description  : finite state mechine description of ecb mode
-- Purpose      : to generate behaviral description of ecb mode
-- Author       : Sigit Dewantoro
-- Address      : IS Laboratory, Labtek VIII, ITB, Jl. Ganesha 10, Bandung, Indonesia
-- Email        : sigit@students.ee.itb.ac.id, sigit@ic.vlsi.itb.ac.id
-- Date         : August 23th, 2001
 
entity ecb is
PORT (
        active          : in BIT;
        clk             : in BIT;
        cke             : in BIT;
        key_ready       : in BIT;
        finish          : in BIT;
        req_cp          : in BIT;
        E               : in BIT;
        E_mesin         : out BIT;
        s_mesin         : out BIT;
        s_gen_key       : out BIT;
        emp_buf         : out BIT;
        cp_ready        : out BIT;
        cke_b_mode      : out BIT;
        en_in           : out BIT;
        en_iv           : out BIT;
        en_rcbc         : out BIT;
        en_out          : out BIT;
        sel1            : out BIT_VECTOR (1 downto 0);
        sel2            : out BIT_VECTOR (1 downto 0);
        sel3            : out BIT_VECTOR (1 downto 0);
        vdd             : in BIT;
        vss             : in BIT
     );
end ecb;
 
architecture STATE_MACHINE of ecb is
        type STATE_TYPE is (S0, S1, S2, S3, S4, S5, S6);
 
        -- pragma CLOCK clk
        -- pragma CURRENT_STATE CURRENT_STATE
        -- pragma NEXT_STATE NEXT_STATE
 
        signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;
 
        begin
        process (CURRENT_STATE, active, cke, key_ready, finish, req_cp)
                begin
                if active then
                        NEXT_STATE <= S0;
                        E_mesin <= E;
                        s_mesin <= '0';
                        s_gen_key <= '0';
                        emp_buf <= '0';
                        cp_ready <= '0';
                        cke_b_mode <= '0';
                        en_in <= '0';
                        en_iv <= '0';
                        en_rcbc <= '0';
                        en_out <= '0';
                        sel1 <= "10";
                        sel2 <= "10";
                        sel3 <= "10";
                else
                        case CURRENT_STATE is
 
                -- ***********************************************************************
 
                        when S0 =>
                        if cke then
                                NEXT_STATE <= S1;
                                E_mesin <= E;
                                s_mesin <= '0';
                                s_gen_key <= '1';
                                emp_buf <= '0';
                                cp_ready <= '0';
                                cke_b_mode <= '1';
                                en_in <= '0';
                                en_iv <= '0';
                                en_rcbc <= '0';
                                en_out <= '0';
                                sel1 <= "10";
                                sel2 <= "10";
                                sel3 <= "10";
                        else
                                NEXT_STATE <= S0;
                                E_mesin <= E;
                                s_mesin <= '0';
                                s_gen_key <= '0';
                                emp_buf <= '0';
                                cp_ready <= '0';
                                cke_b_mode <= '0';
                                en_in <= '0';
                                en_iv <= '0';
                                en_rcbc <= '0';
                                en_out <= '0';
                                sel1 <= "10";
                                sel2 <= "10";
                                sel3 <= "10";
                        end if;
 
                -- ***********************************************************************
 
                        when S1 =>
                        if key_ready then
                                NEXT_STATE <= S2;
                                E_mesin <= E;
                                s_mesin <= '0';
                                s_gen_key <= '1';
                                emp_buf <= '0';
                                cp_ready <= '0';
                                cke_b_mode <= '1';
                                en_in <= '1';
                                en_iv <= '0';
                                en_rcbc <= '0';
                                en_out <= '0';
                                sel1 <= "10";
                                sel2 <= "10";
                                sel3 <= "10";
                        else
                                NEXT_STATE <= S1;
                                E_mesin <= E;
                                s_mesin <= '0';
                                s_gen_key <= '1';
                                emp_buf <= '0';
                                cp_ready <= '0';
                                cke_b_mode <= '1';
                                en_in <= '0';
                                en_iv <= '0';
                                en_rcbc <= '0';
                                en_out <= '0';
                                sel1 <= "10";
                                sel2 <= "10";
                                sel3 <= "10";
                        end if;
 
                -- ***********************************************************************
 
                        when S2 =>
                        NEXT_STATE <= S3;
                        E_mesin <= E;
                        s_mesin <= '1';
                        s_gen_key <= '1';
                        emp_buf <= '1';
                        cp_ready <= '0';
                        cke_b_mode <= '1';
                        en_in <= '0';
                        en_iv <= '0';
                        en_rcbc <= '0';
                        en_out <= '0';
                        sel1 <= "01";
                        sel2 <= "10";
                        sel3 <= "10";
 
                -- ***********************************************************************
 
                        when S3 =>
                        if finish then
                                NEXT_STATE <= S4;
                                E_mesin <= E;
                                s_mesin <= '0';
                                s_gen_key <= '1';
                                emp_buf <= '0';
                                cp_ready <= '0';
                                cke_b_mode <= '1';
                                en_in <= '0';
                                en_iv <= '0';
                                en_rcbc <= '0';
                                en_out <= '1';
                                sel1 <= "01";
                                sel2 <= "10";
                                sel3 <= "10";
                        else
                                NEXT_STATE <= S3;
                                E_mesin <= E;
                                s_mesin <= '1';
                                s_gen_key <= '1';
                                emp_buf <= '1';
                                cp_ready <= '0';
                                cke_b_mode <= '1';
                                en_in <= '0';
                                en_iv <= '0';
                                en_rcbc <= '0';
                                en_out <= '0';
                                sel1 <= "01";
                                sel2 <= "10";
                                sel3 <= "10";
                        end if;
 
                -- ***********************************************************************
 
                        when S4 =>
                        NEXT_STATE <= S5;
                        E_mesin <= E;
                        s_mesin <= '0';
                        s_gen_key <= '1';
                        emp_buf <= '0';
                        cp_ready <= '1';
                        cke_b_mode <= '1';
                        en_in <= '0';
                        en_iv <= '0';
                        en_rcbc <= '0';
                        en_out <= '0';
                        sel1 <= "01";
                        sel2 <= "10";
                        sel3 <= "10";
 
                -- ***********************************************************************
 
                        when S5 =>
                        if req_cp then
                                NEXT_STATE <= S6;
                                E_mesin <= E;
                                s_mesin <= '0';
                                s_gen_key <= '1';
                                emp_buf <= '0';
                                cp_ready <= '0';
                                cke_b_mode <= '1';
                                en_in <= '0';
                                en_iv <= '0';
                                en_rcbc <= '0';
                                en_out <= '0';
                                sel1 <= "01";
                                sel2 <= "10";
                                sel3 <= "10";
                        else
                                NEXT_STATE <= S5;
                                E_mesin <= E;
                                s_mesin <= '0';
                                s_gen_key <= '1';
                                emp_buf <= '0';
                                cp_ready <= '1';
                                cke_b_mode <= '1';
                                en_in <= '0';
                                en_iv <= '0';
                                en_rcbc <= '0';
                                en_out <= '0';
                                sel1 <= "01";
                                sel2 <= "10";
                                sel3 <= "10";
                        end if;
 
                -- ***********************************************************************
 
                        when S6 =>
                        NEXT_STATE <= S6;
                        E_mesin <= E;
                        s_mesin <= '0';
                        s_gen_key <= '1';
                        emp_buf <= '0';
                        cp_ready <= '0';
                        cke_b_mode <= '1';
                        en_in <= '0';
                        en_iv <= '0';
                        en_rcbc <= '0';
                        en_out <= '0';
                        sel1 <= "01";
                        sel2 <= "10";
                        sel3 <= "10";
 
                -- ***********************************************************************
 
                        end case;
                end if;
        end process;
 
        process(clk)
                begin
                if(clk = '0' and clk'event) then
                        CURRENT_STATE <= NEXT_STATE;
                end if;
       end process;
 
end STATE_MACHINE;

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[/] [idea/] [trunk/] [fsm/] [main control/] [ecb.fsm] - Blame information for rev 6

Line No.	Rev	Author	Line
1	6	marta	`-- File Name : ecb.fsm`
2			`-- Version : v1.2`
3			`-- Description : finite state mechine description of ecb mode`
4			`-- Purpose : to generate behaviral description of ecb mode`
5			`-- Author : Sigit Dewantoro`
6			`-- Address : IS Laboratory, Labtek VIII, ITB, Jl. Ganesha 10, Bandung, Indonesia`
7			`-- Email : sigit@students.ee.itb.ac.id, sigit@ic.vlsi.itb.ac.id`
8			`-- Date : August 23th, 2001`
9
10			`entity ecb is`
11			`PORT (`
12			`active : in BIT;`
13			`clk : in BIT;`
14			`cke : in BIT;`
15			`key_ready : in BIT;`
16			`finish : in BIT;`
17			`req_cp : in BIT;`
18			`E : in BIT;`
19			`E_mesin : out BIT;`
20			`s_mesin : out BIT;`
21			`s_gen_key : out BIT;`
22			`emp_buf : out BIT;`
23			`cp_ready : out BIT;`
24			`cke_b_mode : out BIT;`
25			`en_in : out BIT;`
26			`en_iv : out BIT;`
27			`en_rcbc : out BIT;`
28			`en_out : out BIT;`
29			`sel1 : out BIT_VECTOR (1 downto 0);`
30			`sel2 : out BIT_VECTOR (1 downto 0);`
31			`sel3 : out BIT_VECTOR (1 downto 0);`
32			`vdd : in BIT;`
33			`vss : in BIT`
34			`);`
35			`end ecb;`
36
37			`architecture STATE_MACHINE of ecb is`
38			`type STATE_TYPE is (S0, S1, S2, S3, S4, S5, S6);`
39
40			`-- pragma CLOCK clk`
41			`-- pragma CURRENT_STATE CURRENT_STATE`
42			`-- pragma NEXT_STATE NEXT_STATE`
43
44			`signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;`
45
46			`begin`
47			`process (CURRENT_STATE, active, cke, key_ready, finish, req_cp)`
48			`begin`
49			`if active then`
50			`NEXT_STATE <= S0;`
51			`E_mesin <= E;`
52			`s_mesin <= '0';`
53			`s_gen_key <= '0';`
54			`emp_buf <= '0';`
55			`cp_ready <= '0';`
56			`cke_b_mode <= '0';`
57			`en_in <= '0';`
58			`en_iv <= '0';`
59			`en_rcbc <= '0';`
60			`en_out <= '0';`
61			`sel1 <= "10";`
62			`sel2 <= "10";`
63			`sel3 <= "10";`
64			`else`
65			`case CURRENT_STATE is`
66
67			`-- ***********************************************************************`
68
69			`when S0 =>`
70			`if cke then`
71			`NEXT_STATE <= S1;`
72			`E_mesin <= E;`
73			`s_mesin <= '0';`
74			`s_gen_key <= '1';`
75			`emp_buf <= '0';`
76			`cp_ready <= '0';`
77			`cke_b_mode <= '1';`
78			`en_in <= '0';`
79			`en_iv <= '0';`
80			`en_rcbc <= '0';`
81			`en_out <= '0';`
82			`sel1 <= "10";`
83			`sel2 <= "10";`
84			`sel3 <= "10";`
85			`else`
86			`NEXT_STATE <= S0;`
87			`E_mesin <= E;`
88			`s_mesin <= '0';`
89			`s_gen_key <= '0';`
90			`emp_buf <= '0';`
91			`cp_ready <= '0';`
92			`cke_b_mode <= '0';`
93			`en_in <= '0';`
94			`en_iv <= '0';`
95			`en_rcbc <= '0';`
96			`en_out <= '0';`
97			`sel1 <= "10";`
98			`sel2 <= "10";`
99			`sel3 <= "10";`
100			`end if;`
101
102			`-- ***********************************************************************`
103
104			`when S1 =>`
105			`if key_ready then`
106			`NEXT_STATE <= S2;`
107			`E_mesin <= E;`
108			`s_mesin <= '0';`
109			`s_gen_key <= '1';`
110			`emp_buf <= '0';`
111			`cp_ready <= '0';`
112			`cke_b_mode <= '1';`
113			`en_in <= '1';`
114			`en_iv <= '0';`
115			`en_rcbc <= '0';`
116			`en_out <= '0';`
117			`sel1 <= "10";`
118			`sel2 <= "10";`
119			`sel3 <= "10";`
120			`else`
121			`NEXT_STATE <= S1;`
122			`E_mesin <= E;`
123			`s_mesin <= '0';`
124			`s_gen_key <= '1';`
125			`emp_buf <= '0';`
126			`cp_ready <= '0';`
127			`cke_b_mode <= '1';`
128			`en_in <= '0';`
129			`en_iv <= '0';`
130			`en_rcbc <= '0';`
131			`en_out <= '0';`
132			`sel1 <= "10";`
133			`sel2 <= "10";`
134			`sel3 <= "10";`
135			`end if;`
136
137			`-- ***********************************************************************`
138
139			`when S2 =>`
140			`NEXT_STATE <= S3;`
141			`E_mesin <= E;`
142			`s_mesin <= '1';`
143			`s_gen_key <= '1';`
144			`emp_buf <= '1';`
145			`cp_ready <= '0';`
146			`cke_b_mode <= '1';`
147			`en_in <= '0';`
148			`en_iv <= '0';`
149			`en_rcbc <= '0';`
150			`en_out <= '0';`
151			`sel1 <= "01";`
152			`sel2 <= "10";`
153			`sel3 <= "10";`
154
155			`-- ***********************************************************************`
156
157			`when S3 =>`
158			`if finish then`
159			`NEXT_STATE <= S4;`
160			`E_mesin <= E;`
161			`s_mesin <= '0';`
162			`s_gen_key <= '1';`
163			`emp_buf <= '0';`
164			`cp_ready <= '0';`
165			`cke_b_mode <= '1';`
166			`en_in <= '0';`
167			`en_iv <= '0';`
168			`en_rcbc <= '0';`
169			`en_out <= '1';`
170			`sel1 <= "01";`
171			`sel2 <= "10";`
172			`sel3 <= "10";`
173			`else`
174			`NEXT_STATE <= S3;`
175			`E_mesin <= E;`
176			`s_mesin <= '1';`
177			`s_gen_key <= '1';`
178			`emp_buf <= '1';`
179			`cp_ready <= '0';`
180			`cke_b_mode <= '1';`
181			`en_in <= '0';`
182			`en_iv <= '0';`
183			`en_rcbc <= '0';`
184			`en_out <= '0';`
185			`sel1 <= "01";`
186			`sel2 <= "10";`
187			`sel3 <= "10";`
188			`end if;`
189
190			`-- ***********************************************************************`
191
192			`when S4 =>`
193			`NEXT_STATE <= S5;`
194			`E_mesin <= E;`
195			`s_mesin <= '0';`
196			`s_gen_key <= '1';`
197			`emp_buf <= '0';`
198			`cp_ready <= '1';`
199			`cke_b_mode <= '1';`
200			`en_in <= '0';`
201			`en_iv <= '0';`
202			`en_rcbc <= '0';`
203			`en_out <= '0';`
204			`sel1 <= "01";`
205			`sel2 <= "10";`
206			`sel3 <= "10";`
207
208			`-- ***********************************************************************`
209
210			`when S5 =>`
211			`if req_cp then`
212			`NEXT_STATE <= S6;`
213			`E_mesin <= E;`
214			`s_mesin <= '0';`
215			`s_gen_key <= '1';`
216			`emp_buf <= '0';`
217			`cp_ready <= '0';`
218			`cke_b_mode <= '1';`
219			`en_in <= '0';`
220			`en_iv <= '0';`
221			`en_rcbc <= '0';`
222			`en_out <= '0';`
223			`sel1 <= "01";`
224			`sel2 <= "10";`
225			`sel3 <= "10";`
226			`else`
227			`NEXT_STATE <= S5;`
228			`E_mesin <= E;`
229			`s_mesin <= '0';`
230			`s_gen_key <= '1';`
231			`emp_buf <= '0';`
232			`cp_ready <= '1';`
233			`cke_b_mode <= '1';`
234			`en_in <= '0';`
235			`en_iv <= '0';`
236			`en_rcbc <= '0';`
237			`en_out <= '0';`
238			`sel1 <= "01";`
239			`sel2 <= "10";`
240			`sel3 <= "10";`
241			`end if;`
242
243			`-- ***********************************************************************`
244
245			`when S6 =>`
246			`NEXT_STATE <= S6;`
247			`E_mesin <= E;`
248			`s_mesin <= '0';`
249			`s_gen_key <= '1';`
250			`emp_buf <= '0';`
251			`cp_ready <= '0';`
252			`cke_b_mode <= '1';`
253			`en_in <= '0';`
254			`en_iv <= '0';`
255			`en_rcbc <= '0';`
256			`en_out <= '0';`
257			`sel1 <= "01";`
258			`sel2 <= "10";`
259			`sel3 <= "10";`
260
261			`-- ***********************************************************************`
262
263			`end case;`
264			`end if;`
265			`end process;`
266
267			`process(clk)`
268			`begin`
269			`if(clk = '0' and clk'event) then`
270			`CURRENT_STATE <= NEXT_STATE;`
271			`end if;`
272			`end process;`
273
274			`end STATE_MACHINE;`