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-- File Name    : register.fsm

-- Description  : finite state mechine description of register block

-- Author       : Sigit Dewantoro

-- Date         : July 3rd, 2001

entity ecb is

PORT (

        a               : in BIT;

        clk             : in BIT;

        cke             : in BIT;

        clr             : in BIT;

        en              : in BIT;

        b               : out BIT

     );

end ecb;

architecture STATE_MACHINE of ecb is

        type STATE_TYPE is (S0, S1, S2, S3);

        -- pragma CLOCK clk

        -- pragma CURRENT_STATE CURRENT_STATE

        -- pragma NEXT_STATE NEXT_STATE

        signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;

        begin

        process (CURRENT_STATE, en, clr, cke)

                begin

                if (clr or en) then

                        NEXT_STATE <= S0;

                else

                case CURRENT_STATE is

        -- ***********************************************************************

                when S0 =>

                if clr then

                        NEXT_STATE <= S1;

                        b <= '0';

                else

                        if cke then

                                NEXT_STATE <= S2;

                                b <= a;

                        end if;

                end if;

        -- ***********************************************************************

                when S1 =>

                NEXT_STATE <= S3;

        -- ***********************************************************************

                when S2 =>

                NEXT_STATE <= S3;

                end case;

                end if;

        end process;

        process(clk)

                begin

                if(clk = '0' and not clk' stable) then

                        CURRENT_STATE <= NEXT_STATE;

                end if;

       end process;

end STATE_MACHINE;