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[/] [mips_fault_tolerant/] [trunk/] [source/] [main.vhd] - Blame information for rev 38

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1 37 jimi39
----------------------------------------------------------------------------------
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-- Company: 
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-- Engineer:       Lazaridis Dimitris
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-- 
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-- Create Date:    02:56:56 05/29/2012 
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-- Design Name: 
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-- Module Name:    main - Behavioral 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
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-- Description: 
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity main is
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Port
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(
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         Clk : in  std_logic;
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                        Rst : in  std_logic;
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                        vector_on : in std_logic_vector(2 downto 0);
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                        sel_top : in  std_logic;
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                        Err : out STD_LOGIC;
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                        pass : out std_logic;
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                        Bus_r : out std_logic_vector(31 downto 0)
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);
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end main;
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architecture Behavioral of main is
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component ALU is
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Port (     clk : in  std_logic;
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                rst,Mult_en,sel_top : in  STD_LOGIC;
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           A_in : in  std_logic_vector(31 downto 0);
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           B_in : in  std_logic_vector(31 downto 0);
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                          I : in  std_logic_vector(31 downto 0);
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                          immed_addr : std_logic_vector(15 downto 0);
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           ALUOp : in  std_logic_vector(2 downto 0);
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                          ALUmux : in  std_logic_vector(1 downto 0);
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                          From_i_op : IN std_logic_vector(1 downto 0);
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                          From_i_mux : IN std_logic_vector(1 downto 0);
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                          lui : in  STD_LOGIC;
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                          ALUSrcA : in std_logic;
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                          ALUSrcB : in  STD_LOGIC_VECTOR(1 downto 0);
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                          N  : in std_logic_vector(31 downto 0);
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                          M : out std_logic_vector(31 downto 0);
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                          Alu_out_exit : out  std_logic_vector(31 downto 0);
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                          Hi_out : out std_logic_vector(31 downto 0);
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                          Lo_out : out std_logic_vector(31 downto 0);
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                          Zero,pass : out std_logic
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);
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end component;
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component fsm is
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Port (     clk : in  STD_LOGIC;
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           rst : in  STD_LOGIC;
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                          RegDst, RegWrite, ALUSrcA, MemRead, MemWrite, Mult_en, IorD, IRWrite, PCWrite,
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           EqNq,ALUsw : out std_logic;
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           instr_31_26,immed_addr : in std_logic_vector(5 downto 0);
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           ALUOp,ALUSrcB,PCSource,ALUmux : OUT std_logic_vector(1 downto 0);
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                          ALUop_sw,RFmux : out std_logic_vector(2 downto 0)
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                        );
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end component;
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component Imem_block is
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port (
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        clk : in std_logic;
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                  rst : in std_logic;
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                  npc : in std_logic_vector(31 downto 0);
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        MemRead : in  STD_LOGIC;
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                  PCWrite : in  STD_LOGIC;
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                  IRWrite : in  STD_LOGIC;
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                  Opcode   : out std_logic_vector(5 downto 0);
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                  rs       : out std_logic_vector(4 downto 0);
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                  rt       : out std_logic_vector(4 downto 0);
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                  rd       : out std_logic_vector(4 downto 0);
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        immed_addr : out std_logic_vector(15 downto 0);
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                  Err : out STD_LOGIC;
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                  N : out std_logic_vector(31 downto 0);
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                  Ext_sz_c  : out std_logic;
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                  From_i_op : out std_logic_vector(1 downto 0);
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                  From_i_mux : out std_logic_vector(1 downto 0);
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                  lui : out  STD_LOGIC
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                );
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end component;
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component Reg_block is
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port (
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      Clk : in std_logic;
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                rst : in  STD_LOGIC;
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                vector_on : in std_logic_vector(2 downto 0);
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                Reg_Write : in std_logic;
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                Reg_Imm_not : in std_logic;
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                rs : in std_logic_vector(4 downto 0);
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                rt : in std_logic_vector(4 downto 0);
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                rd : in std_logic_vector(4 downto 0);
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                Ext_sz_c   : in std_logic;
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                immed_addr : in std_logic_vector(15 downto 0);
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                Bus_W : in std_logic_vector(31 downto 0);
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                A2Alu : out std_logic_vector(31 downto 0);
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                B2Alu : out std_logic_vector(31 downto 0);
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      I2Alu : out std_logic_vector(31 downto 0)
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);
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end component;
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component Dm is
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port (
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      clk    : in std_logic;
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                rst : in std_logic;
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      Alu_in :in std_logic_vector(31 downto 0);
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                MDR_in : in std_logic_vector(31 downto 0);
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                --op_code: in std_logic_vector(5 downto 0);
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                MemWrite : in std_logic;
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                MemRead : in std_logic;
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                IorD : in std_logic;
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                MDR_out : out std_logic_vector(31 downto 0)
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      --E  : out std_logic_vector(1 downto 0) 
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);
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end component;
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component Mux_out_block is
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port (
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      clk   : in std_logic;
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                Zero_in,EqNq : in std_logic;
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                RFmux : in std_logic_vector(2 downto 0);
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      Hi_in : in std_logic_vector(31 downto 0);
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      Lo_in : in std_logic_vector(31 downto 0);
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      Alu_in: in std_logic_vector(31 downto 0);
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      Mdr_fr_out : in std_logic_vector(31 downto 0);
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      RF_out: out std_logic_vector(31 downto 0);
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                From_N: in std_logic_vector(31 downto 0);
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                From_A: in std_logic_vector(31 downto 0);
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                From_M: in std_logic_vector(31 downto 0);
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                PCSource: in std_logic_vector(1 downto 0);
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                NPC_out: out std_logic_vector(31 downto 0)
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);
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end component;
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signal RegDst, RegWrite, ALUSrcA, MemRead, MemWrite, Mult_en, IorD, IRWrite, PCWrite,
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           EqNq,Ext_sz_c,No_u,Zero,lui : STD_LOGIC;
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signal No_u2,ALUmux,PCSource,ALUSrcB,From_i_op,From_i_mux : std_logic_vector(1 downto 0);
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signal ALUop_sw,RFmux : std_logic_vector(2 downto 0);
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signal rs,rt,rd : std_logic_vector(4 downto 0);
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signal instr_31_26 : std_logic_vector(5 downto 0);
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signal immed_addr : std_logic_vector(15 downto 0);
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signal Bus_W,A_wire,B_wire,I_wire,npc,MDR_out,Alu_out_exit,
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       N,M,Hi_out,Lo_out : std_logic_vector(31 downto 0);
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begin
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fsm_m:fsm port map(clk=>clk,rst=>rst,RegWrite=>RegWrite,PCSource=>PCSource,
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          ALUSrcB=>ALUSrcB,ALUmux=>ALUmux,
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                    instr_31_26=>instr_31_26,immed_addr=>immed_addr(5 downto 0),RegDst=>RegDst,
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                         ALUOp=>No_u2,ALUSrcA=>ALUSrcA,MemRead=>MemRead,
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                         MemWrite=>MemWrite,Mult_en=>Mult_en,IorD=>IorD,IRWrite=>IRWrite,PCWrite=>PCWrite,
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                         EqNq=>EqNq,ALUsw=>No_u,RFmux=>RFmux,ALUop_sw=>ALUop_sw);
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ALU_m:ALU port map(clk=>clk,rst=>rst,Mult_en=>Mult_en,sel_top=>sel_top,A_in=>A_wire,B_in=>B_wire,
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          I=>I_wire,immed_addr=>immed_addr,
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          ALUOp=>ALUop_sw,ALUmux=>ALUmux,From_i_op=>From_i_op,From_i_mux=>From_i_mux,
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                         lui=>lui,Zero=>Zero,ALUSrcA=>ALUSrcA,ALUSrcB=>ALUSrcB,N=>N,M=>M,Hi_out=>Hi_out,
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                         Lo_out=>Lo_out,Alu_out_exit=>Alu_out_exit,pass=>pass);
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Imem_block_m:Imem_block port map(clk=>clk,rst=>rst,MemRead=>MemRead,PCWrite=>PCWrite,
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                                 IRWrite=>IRWrite,rt=>rt,rd=>rd,rs=>rs,immed_addr=>immed_addr,
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                                                                                        Opcode=>instr_31_26,npc=>npc,Err=>Err,N=>N,Ext_sz_c=>Ext_sz_c,
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                                                                                        From_i_op=>From_i_op,From_i_mux=>From_i_mux,lui=>lui);
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Reg_blog_m:Reg_block port map(Clk=>Clk,rst=>rst,vector_on=>vector_on,Reg_Write=>RegWrite,Reg_Imm_not=>RegDst,
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           rs=>rs,rt=>rt,rd=>rd,Ext_sz_c=>Ext_sz_c,immed_addr=>immed_addr,Bus_W=>Bus_W,
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                          A2Alu=>A_wire,B2Alu=>B_wire,I2Alu=>I_wire);
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Dm_m:Dm port map(clk=>Clk,rst=>rst,Alu_in=>Alu_out_exit,MemWrite=>MemWrite,MemRead=>MemRead,
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                 IorD=>IorD,MDR_in=>B_wire,MDR_out=>MDR_out);
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Mux_out:Mux_out_block port map(clk=>clk,Zero_in=>Zero,EqNq=>EqNq,RFmux=>RFmux,Hi_in=>Hi_out,
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                              Lo_in=>Lo_out,Alu_in=>Alu_out_exit,Mdr_fr_out=>MDR_out,
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                                                                                RF_out=>Bus_W,From_N=>N,From_A=>A_wire,From_M=>M,PCSource=>PCSource,
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                                                                        NPC_out=>npc);
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process(clk)
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begin
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if (RISING_EDGE(clk))then
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Bus_r <= Bus_W;
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end if;
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end process;
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end Behavioral;
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