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[/] [mips_fault_tolerant/] [trunk/] [source/] [mult_lfsr.vhd] - Blame information for rev 47

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Line No. Rev Author Line
1 33 jimi39
library IEEE;
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USE ieee.std_logic_1164.ALL;
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--USE IEEE.std_logic_arith.all;
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--use IEEE.NUMERIC_STD.ALL;
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--use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity mult_lfsr is
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    port (clock_top : in std_logic;
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          reset_top : in std_logic;
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          sel_top   : in std_logic;
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          X_top     : in std_logic_vector(31 DOWNTO 0);
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     Y_top     : in std_logic_vector(31 DOWNTO 0);
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     Hi_to_out : out STD_LOGIC_VECTOR (31 downto 0);
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     Lo_to_out : out STD_LOGIC_VECTOR (31 downto 0);
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          pass      : out std_logic
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        );
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end mult_lfsr;
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architecture Stractural of mult_lfsr is
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component mult_32x32
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  PORT
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    (
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     X :IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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     Y :IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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     P :OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
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     );
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END component;
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component LFSR
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  port  ( clock: in std_logic;
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          reset: in std_logic;
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          sel_top   : in std_logic;
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          data_out: out std_logic_vector(63 downto 0)
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        );
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end component;
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component mux32
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    Port ( A : in std_logic_vector(31 downto 0);
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           B : in std_logic_vector(31 downto 0);
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           SEL : in std_logic;
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           MUX_OUT : out std_logic_vector(31 downto 0));
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end component;
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component misr is
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port (
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  clock    : in std_logic;
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  reset    : in std_logic;
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  sel_top   : in std_logic;
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  data_in   : in std_logic_vector(63 downto 0);
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  pass      : out std_logic
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);
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end component;
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Signal data_out_signal,P_temp,seed_top : std_logic_vector(63 downto 0);
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Signal X_signal : std_logic_vector(31 downto 0);
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Signal Y_signal : std_logic_vector(31 downto 0);
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begin
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u1: lfsr port map (clock=>clock_top,reset=>reset_top,sel_top=>sel_top,data_out=>data_out_signal);
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u2: mux32 port map (A=>X_top,B=>data_out_signal(63 downto 32),SEL=>sel_top,MUX_OUT=>X_signal);
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u3: mux32 port map (A=>Y_top,B=>data_out_signal(31 downto 0),SEL=>sel_top,MUX_OUT=>Y_signal);
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u4: mult_32x32 port map (X=>X_signal,Y=>Y_signal,P=>P_temp);
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u5: misr port map (clock=>clock_top,reset=>reset_top,sel_top=>sel_top,data_in=>P_temp,pass=>pass);
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Hi_to_out <= P_temp(63 downto 32);
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Lo_to_out <= P_temp(31 downto 0);
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end Stractural;
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