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eexuke |
//--------------------------------------------------------------------------------------------------
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// Design : nova
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// Author(s) : Ke Xu
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// Email : eexuke@yahoo.com
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// File : Intra_pred_PE.v
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// Generated : Sep 19, 2005
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// Copyright (C) 2008 Ke Xu
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//-------------------------------------------------------------------------------------------------
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// Description
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// Processing Element for Intra prediction,PE0 ~ PE3
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//-------------------------------------------------------------------------------------------------
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "nova_defines.v"
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module Intra_pred_PE (clk,reset_n,mb_type_general,blk4x4_rec_counter,blk4x4_intra_calculate_counter,
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Intra4x4_predmode,Intra16x16_predmode,Intra_chroma_predmode,
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blkAddrA_availability,blkAddrB_availability,mbAddrA_availability,mbAddrB_availability,
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Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3,
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Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3,
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Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3,
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Intra_mbAddrD_window,
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Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3,
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Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7,
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Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11,
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Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15,
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Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3,
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Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7,
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Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11,
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Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15,
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blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2,
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blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6,
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blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10,
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blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14,
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seed,b,c,
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PE0_out,PE1_out,PE2_out,PE3_out,PE0_sum_out,PE3_sum_out);
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input clk,reset_n;
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input [3:0] mb_type_general;
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input [4:0] blk4x4_rec_counter;
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input [2:0] blk4x4_intra_calculate_counter;
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input [3:0] Intra4x4_predmode;
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input [1:0] Intra16x16_predmode;
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input [1:0] Intra_chroma_predmode;
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input blkAddrA_availability;
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input blkAddrB_availability;
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input mbAddrA_availability;
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input mbAddrB_availability;
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input [15:0] Intra_mbAddrA_window0,Intra_mbAddrA_window1,Intra_mbAddrA_window2,Intra_mbAddrA_window3;
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input [15:0] Intra_mbAddrB_window0,Intra_mbAddrB_window1,Intra_mbAddrB_window2,Intra_mbAddrB_window3;
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input [15:0] Intra_mbAddrC_window0,Intra_mbAddrC_window1,Intra_mbAddrC_window2,Intra_mbAddrC_window3;
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input [15:0] Intra_mbAddrD_window;
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input [15:0] Intra_mbAddrA_reg0, Intra_mbAddrA_reg1, Intra_mbAddrA_reg2, Intra_mbAddrA_reg3;
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input [15:0] Intra_mbAddrA_reg4, Intra_mbAddrA_reg5, Intra_mbAddrA_reg6, Intra_mbAddrA_reg7;
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input [15:0] Intra_mbAddrA_reg8, Intra_mbAddrA_reg9, Intra_mbAddrA_reg10,Intra_mbAddrA_reg11;
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input [15:0] Intra_mbAddrA_reg12,Intra_mbAddrA_reg13,Intra_mbAddrA_reg14,Intra_mbAddrA_reg15;
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input [15:0] Intra_mbAddrB_reg0, Intra_mbAddrB_reg1, Intra_mbAddrB_reg2, Intra_mbAddrB_reg3;
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input [15:0] Intra_mbAddrB_reg4, Intra_mbAddrB_reg5, Intra_mbAddrB_reg6, Intra_mbAddrB_reg7;
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input [15:0] Intra_mbAddrB_reg8, Intra_mbAddrB_reg9, Intra_mbAddrB_reg10,Intra_mbAddrB_reg11;
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input [15:0] Intra_mbAddrB_reg12,Intra_mbAddrB_reg13,Intra_mbAddrB_reg14,Intra_mbAddrB_reg15;
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input [15:0] blk4x4_pred_output0, blk4x4_pred_output1, blk4x4_pred_output2;
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input [15:0] blk4x4_pred_output4, blk4x4_pred_output5, blk4x4_pred_output6;
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input [15:0] blk4x4_pred_output8, blk4x4_pred_output9, blk4x4_pred_output10;
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input [15:0] blk4x4_pred_output12,blk4x4_pred_output13,blk4x4_pred_output14;
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input [15:0] seed;
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input [11:0] b,c;
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output [7:0] PE0_out;
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output [7:0] PE1_out;
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output [7:0] PE2_out;
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output [7:0] PE3_out;
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output [15:0] PE0_sum_out; //for store as 2nd-level seed
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output [15:0] PE3_sum_out; //for store as 2nd-level seed
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reg [15:0] PE0_in0,PE0_in1,PE0_in2,PE0_in3;
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reg PE0_IsShift;
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reg PE0_IsStore;
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reg PE0_IsClip;
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reg PE0_full_bypass;
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reg [4:0] PE0_round_value;
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reg [2:0] PE0_shift_len;
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reg [15:0] PE1_in0,PE1_in1,PE1_in2,PE1_in3;
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reg PE1_IsShift;
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reg PE1_IsStore;
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reg PE1_IsClip;
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reg PE1_full_bypass;
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reg [4:0] PE1_round_value;
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reg [2:0] PE1_shift_len;
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reg [15:0] PE2_in0,PE2_in1,PE2_in2,PE2_in3;
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reg PE2_IsShift;
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reg PE2_IsStore;
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reg PE2_IsClip;
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reg PE2_full_bypass;
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reg [4:0] PE2_round_value;
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reg [2:0] PE2_shift_len;
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reg [15:0] PE3_in0,PE3_in1,PE3_in2,PE3_in3;
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reg PE3_IsShift;
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reg PE3_IsStore;
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reg PE3_IsClip;
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reg PE3_full_bypass;
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reg [4:0] PE3_round_value;
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reg [2:0] PE3_shift_len;
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wire [15:0] PE0_out_reg;
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wire [15:0] PE1_out_reg;
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wire [15:0] PE2_out_reg;
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wire [15:0] PE3_out_reg;
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wire [15:0] PE0_sum_out;
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wire [15:0] PE1_sum_out;
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wire [15:0] PE2_sum_out;
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wire [15:0] PE3_sum_out;
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wire [15:0] b_ext,c_ext;
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assign b_ext = (b[11] == 1'b1)? {4'b1111,b}:{4'b0000,b};
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assign c_ext = (c[11] == 1'b1)? {4'b1111,c}:{4'b0000,c};
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PE PE0 (
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.clk(clk),
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.reset_n(reset_n),
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.in0(PE0_in0),
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.in1(PE0_in1),
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.in2(PE0_in2),
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.in3(PE0_in3),
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.IsShift(PE0_IsShift),
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.IsStore(PE0_IsStore),
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.IsClip(PE0_IsClip),
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.full_bypass(PE0_full_bypass),
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.round_value(PE0_round_value),
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.shift_len(PE0_shift_len),
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.PE_out_reg(PE0_out_reg),
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.PE_out(PE0_out),
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.sum_out(PE0_sum_out)
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);
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PE PE1 (
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.clk(clk),
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.reset_n(reset_n),
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.in0(PE1_in0),
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.in1(PE1_in1),
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.in2(PE1_in2),
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.in3(PE1_in3),
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.IsShift(PE1_IsShift),
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.IsStore(PE1_IsStore),
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.IsClip(PE1_IsClip),
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.full_bypass(PE1_full_bypass),
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.round_value(PE1_round_value),
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.shift_len(PE1_shift_len),
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.PE_out_reg(PE1_out_reg),
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.PE_out(PE1_out),
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.sum_out(PE1_sum_out)
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);
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PE PE2 (
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.clk(clk),
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.reset_n(reset_n),
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.in0(PE2_in0),
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.in1(PE2_in1),
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.in2(PE2_in2),
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.in3(PE2_in3),
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.IsShift(PE2_IsShift),
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.IsStore(PE2_IsStore),
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.IsClip(PE2_IsClip),
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.full_bypass(PE2_full_bypass),
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.round_value(PE2_round_value),
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.shift_len(PE2_shift_len),
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.PE_out_reg(PE2_out_reg),
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.PE_out(PE2_out),
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.sum_out(PE2_sum_out)
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);
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PE PE3 (
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.clk(clk),
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.reset_n(reset_n),
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.in0(PE3_in0),
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.in1(PE3_in1),
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.in2(PE3_in2),
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.in3(PE3_in3),
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.IsShift(PE3_IsShift),
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.IsStore(PE3_IsStore),
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.IsClip(PE3_IsClip),
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.full_bypass(PE3_full_bypass),
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.round_value(PE3_round_value),
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.shift_len(PE3_shift_len),
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.PE_out_reg(PE3_out_reg),
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.PE_out(PE3_out),
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.sum_out(PE3_sum_out)
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);
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//----
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//PE0 |
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//----
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always @ (mb_type_general or blk4x4_rec_counter or blk4x4_intra_calculate_counter
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or Intra4x4_predmode or Intra16x16_predmode or Intra_chroma_predmode
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or blkAddrA_availability or blkAddrB_availability or mbAddrA_availability or mbAddrB_availability
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or Intra_mbAddrA_window0 or Intra_mbAddrA_window1 or Intra_mbAddrA_window2
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or Intra_mbAddrB_window0 or Intra_mbAddrB_window1 or Intra_mbAddrB_window2 or Intra_mbAddrB_window3
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or Intra_mbAddrD_window
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or Intra_mbAddrA_reg0 or Intra_mbAddrA_reg1 or Intra_mbAddrA_reg2 or Intra_mbAddrA_reg3
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or Intra_mbAddrB_reg1 or Intra_mbAddrB_reg2 or Intra_mbAddrB_reg3
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or PE0_out_reg or PE1_out_reg or PE2_out_reg or PE3_out_reg
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or blk4x4_pred_output4 or blk4x4_pred_output5 or blk4x4_pred_output8
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or blk4x4_pred_output9 or blk4x4_pred_output10 or blk4x4_pred_output12
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or seed or b_ext or c_ext)
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//Intra 4x4
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if (mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16)
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case (Intra4x4_predmode)
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`Intra4x4_Vertical:
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begin
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case (blk4x4_intra_calculate_counter)
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4:PE0_in0 <= Intra_mbAddrB_window0;
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3:PE0_in0 <= Intra_mbAddrB_window1;
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2:PE0_in0 <= Intra_mbAddrB_window2;
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1:PE0_in0 <= Intra_mbAddrB_window3;
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default:PE0_in0 <= 0;
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endcase
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PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0;
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PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0;
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PE0_full_bypass <= 1; PE0_round_value <= 0; PE0_shift_len <= 0;
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end
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`Intra4x4_Horizontal:
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begin
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PE0_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window0:0;
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PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0;
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PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0;
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PE0_full_bypass <= 1; PE0_round_value <= 0; PE0_shift_len <= 0;
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end
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`Intra4x4_DC:
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case (blk4x4_intra_calculate_counter)
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4: //A ~ D
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begin
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if (blkAddrB_availability == 1)
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begin
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PE0_in0 <= Intra_mbAddrB_window0; PE0_in1 <= Intra_mbAddrB_window1;
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PE0_in2 <= Intra_mbAddrB_window2; PE0_in3 <= Intra_mbAddrB_window3;
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PE0_IsStore <= 1'b1; PE0_full_bypass <= 1'b0;
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end
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else
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begin
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PE0_in0 <= 0; PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0;
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PE0_IsStore <= 1'b0; PE0_full_bypass <= 1'b1;
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end
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PE0_IsShift <= 0; PE0_IsClip <= 0;
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PE0_round_value <= 0; PE0_shift_len <= 0;
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end
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3:
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begin
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case ({blkAddrB_availability,blkAddrA_availability})
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2'b00:
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begin
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PE0_in0 <= 128; PE0_in1 <= 0;
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PE0_full_bypass <= 1'b1; PE0_round_value <= 0; PE0_shift_len <= 0;
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end
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2'b01,2'b10:
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begin
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PE0_in0 <= (blkAddrB_availability)? PE0_out_reg:0;
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PE0_in1 <= (blkAddrA_availability)? PE1_out_reg:0;
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PE0_full_bypass <= 1'b0; PE0_round_value <= 2; PE0_shift_len <= 2;
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end
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2'b11:
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begin
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PE0_in0 <= PE0_out_reg; PE0_in1 <= PE1_out_reg;
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PE0_full_bypass <= 1'b0; PE0_round_value <= 4; PE0_shift_len <= 3;
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end
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endcase
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PE0_in2 <= 0; PE0_in3 <= 0;
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PE0_IsStore <= 0; PE0_IsShift <= 0; PE0_IsClip <= 0;
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end
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default:
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begin
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PE0_in0 <= 0; PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0;
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|
|
PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0;
|
278 |
|
|
PE0_full_bypass <= 1; PE0_round_value <= 0; PE0_shift_len <= 0;
|
279 |
|
|
end
|
280 |
|
|
endcase
|
281 |
|
|
`Intra4x4_Diagonal_Down_Left:
|
282 |
|
|
begin
|
283 |
|
|
case (blk4x4_intra_calculate_counter)
|
284 |
|
|
4:PE0_in0 <= Intra_mbAddrB_window0;
|
285 |
|
|
3:PE0_in0 <= blk4x4_pred_output4;
|
286 |
|
|
2:PE0_in0 <= blk4x4_pred_output8;
|
287 |
|
|
1:PE0_in0 <= blk4x4_pred_output12;
|
288 |
|
|
default:PE0_in0 <= 0;
|
289 |
|
|
endcase
|
290 |
|
|
PE0_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window2:0;
|
291 |
|
|
PE0_in2 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window1:0;
|
292 |
|
|
PE0_in3 <= 0;
|
293 |
|
|
PE0_IsShift <= (blk4x4_intra_calculate_counter == 4)? 1'b1:1'b0;
|
294 |
|
|
PE0_IsStore <= 1'b0; PE0_IsClip <= 1'b0;
|
295 |
|
|
PE0_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1;
|
296 |
|
|
PE0_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'b00010:5'b0; // +2
|
297 |
|
|
PE0_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'b010:3'b0; // >>2
|
298 |
|
|
end
|
299 |
|
|
`Intra4x4_Diagonal_Down_Right:
|
300 |
|
|
begin
|
301 |
|
|
case (blk4x4_intra_calculate_counter)
|
302 |
|
|
4:begin PE0_in0 <= Intra_mbAddrB_window0; PE0_in1 <= Intra_mbAddrA_window0;
|
303 |
|
|
PE0_in2 <= Intra_mbAddrD_window; end
|
304 |
|
|
3:begin PE0_in0 <= Intra_mbAddrD_window; PE0_in1 <= Intra_mbAddrB_window1;
|
305 |
|
|
PE0_in2 <= Intra_mbAddrB_window0; end
|
306 |
|
|
2:begin PE0_in0 <= Intra_mbAddrB_window0; PE0_in1 <= Intra_mbAddrB_window2;
|
307 |
|
|
PE0_in2 <= Intra_mbAddrB_window1; end
|
308 |
|
|
1:begin PE0_in0 <= Intra_mbAddrB_window1; PE0_in1 <= Intra_mbAddrB_window3;
|
309 |
|
|
PE0_in2 <= Intra_mbAddrB_window2; end
|
310 |
|
|
default:begin PE0_in0 <= 0;PE0_in1 <= 0;PE0_in2 <= 0; end
|
311 |
|
|
endcase
|
312 |
|
|
PE0_in3 <= 0;
|
313 |
|
|
PE0_IsShift <= (blk4x4_intra_calculate_counter == 0)? 1'b0:1'b1;
|
314 |
|
|
PE0_IsStore <= 1'b0; PE0_IsClip <= 1'b0; PE0_full_bypass <= 1'b0;
|
315 |
|
|
PE0_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'b0:5'b00010; // +2
|
316 |
|
|
PE0_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'b0:3'b010; // >>2
|
317 |
|
|
end
|
318 |
|
|
`Intra4x4_Vertical_Right:
|
319 |
|
|
begin
|
320 |
|
|
case (blk4x4_intra_calculate_counter)
|
321 |
|
|
4:begin PE0_in0 <= Intra_mbAddrB_window0;PE0_in1 <= Intra_mbAddrD_window; end
|
322 |
|
|
3:begin PE0_in0 <= Intra_mbAddrB_window0;PE0_in1 <= Intra_mbAddrB_window1;end
|
323 |
|
|
2:begin PE0_in0 <= Intra_mbAddrB_window2;PE0_in1 <= Intra_mbAddrB_window1;end
|
324 |
|
|
1:begin PE0_in0 <= Intra_mbAddrB_window2;PE0_in1 <= Intra_mbAddrB_window3;end
|
325 |
|
|
default:begin PE0_in0 <= 0;PE0_in1 <= 0; end
|
326 |
|
|
endcase
|
327 |
|
|
PE0_in2 <= 0; PE0_in3 <= 0;
|
328 |
|
|
PE0_IsShift <= 1'b0;PE0_IsStore <= 1'b0; PE0_IsClip <= 1'b0; PE0_full_bypass <= 1'b0;
|
329 |
|
|
PE0_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'b0:5'b00001; // +1
|
330 |
|
|
PE0_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'b0:3'b001; // >>1
|
331 |
|
|
end
|
332 |
|
|
`Intra4x4_Horizontal_Down:
|
333 |
|
|
begin
|
334 |
|
|
case (blk4x4_intra_calculate_counter)
|
335 |
|
|
4:begin PE0_in0 <= Intra_mbAddrA_window0;PE0_in1 <= Intra_mbAddrD_window;
|
336 |
|
|
PE0_in2 <= 0;
|
337 |
|
|
PE0_round_value <= 5'b00001; PE0_shift_len <= 3'b001;end
|
338 |
|
|
3:begin PE0_in0 <= Intra_mbAddrA_window0;PE0_in1 <= Intra_mbAddrB_window0;
|
339 |
|
|
PE0_in2 <= Intra_mbAddrD_window;
|
340 |
|
|
PE0_round_value <= 5'b00010; PE0_shift_len <= 3'b010;end
|
341 |
|
|
2:begin PE0_in0 <= Intra_mbAddrD_window; PE0_in1 <= Intra_mbAddrB_window1;
|
342 |
|
|
PE0_in2 <= Intra_mbAddrB_window0;
|
343 |
|
|
PE0_round_value <= 5'b00010; PE0_shift_len <= 3'b010;end
|
344 |
|
|
1:begin PE0_in0 <= Intra_mbAddrB_window0;PE0_in1 <= Intra_mbAddrB_window2;
|
345 |
|
|
PE0_in2 <= Intra_mbAddrB_window1;
|
346 |
|
|
PE0_round_value <= 5'b00010; PE0_shift_len <= 3'b010;end
|
347 |
|
|
default:begin PE0_in0 <= 0;PE0_in1 <= 0;PE0_in2 <= 0;
|
348 |
|
|
PE0_round_value <= 0;PE0_shift_len <= 0; end
|
349 |
|
|
endcase
|
350 |
|
|
PE0_in3 <= 0;
|
351 |
|
|
PE0_IsShift <= (blk4x4_intra_calculate_counter == 3 || blk4x4_intra_calculate_counter == 2
|
352 |
|
|
|| blk4x4_intra_calculate_counter == 1)? 1'b1:1'b0;
|
353 |
|
|
PE0_IsStore <= 1'b0; PE0_IsClip <= 1'b0; PE0_full_bypass <= 1'b0;
|
354 |
|
|
end
|
355 |
|
|
`Intra4x4_Vertical_Left:
|
356 |
|
|
begin
|
357 |
|
|
case (blk4x4_intra_calculate_counter)
|
358 |
|
|
4:PE0_in0 <= Intra_mbAddrB_window0;
|
359 |
|
|
3:PE0_in0 <= blk4x4_pred_output8;
|
360 |
|
|
2:PE0_in0 <= blk4x4_pred_output9;
|
361 |
|
|
1:PE0_in0 <= blk4x4_pred_output10;
|
362 |
|
|
default:PE0_in0 <= 0;
|
363 |
|
|
endcase
|
364 |
|
|
PE0_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window1:0;
|
365 |
|
|
PE0_in2 <= 0; PE0_in3 <= 0;
|
366 |
|
|
PE0_IsShift <= 1'b0; PE0_IsStore <= 1'b0; PE0_IsClip <= 1'b0;
|
367 |
|
|
PE0_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1;
|
368 |
|
|
PE0_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'b00001:5'b0; // +1
|
369 |
|
|
PE0_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'b001:3'b0; // >>1
|
370 |
|
|
end
|
371 |
|
|
`Intra4x4_Horizontal_Up:
|
372 |
|
|
begin
|
373 |
|
|
case (blk4x4_intra_calculate_counter)
|
374 |
|
|
4:begin PE0_in0 <= Intra_mbAddrA_window0; PE0_in1 <= Intra_mbAddrA_window1; end
|
375 |
|
|
3:begin PE0_in0 <= Intra_mbAddrA_window0; PE0_in1 <= Intra_mbAddrA_window2; end
|
376 |
|
|
2:begin PE0_in0 <= blk4x4_pred_output4; PE0_in1 <= 0; end
|
377 |
|
|
1:begin PE0_in0 <= blk4x4_pred_output5; PE0_in1 <= 0; end
|
378 |
|
|
default:begin PE0_in0 <= 0; PE0_in1 <= 0; end
|
379 |
|
|
endcase
|
380 |
|
|
PE0_in2 <= (blk4x4_intra_calculate_counter == 3)? Intra_mbAddrA_window1:0;
|
381 |
|
|
PE0_in3 <= 0;
|
382 |
|
|
PE0_IsShift <= (blk4x4_intra_calculate_counter == 3)? 1'b1:1'b0;
|
383 |
|
|
PE0_IsStore <= 1'b0; PE0_IsClip <= 1'b0;
|
384 |
|
|
PE0_full_bypass <= (blk4x4_intra_calculate_counter == 4 ||
|
385 |
|
|
blk4x4_intra_calculate_counter == 3)? 1'b0:1'b1;
|
386 |
|
|
PE0_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'd1:
|
387 |
|
|
(blk4x4_intra_calculate_counter == 3)? 5'd2:5'd0;
|
388 |
|
|
PE0_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'd1:
|
389 |
|
|
(blk4x4_intra_calculate_counter == 3)? 3'd2:3'd0;
|
390 |
|
|
end
|
391 |
|
|
default:
|
392 |
|
|
begin
|
393 |
|
|
PE0_in0 <= 0; PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0;
|
394 |
|
|
PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0;
|
395 |
|
|
PE0_full_bypass <= 0; PE0_round_value <= 0; PE0_shift_len <= 0;
|
396 |
|
|
end
|
397 |
|
|
endcase
|
398 |
|
|
//Intra16x16
|
399 |
|
|
else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16)
|
400 |
|
|
case (Intra16x16_predmode)
|
401 |
|
|
`Intra16x16_Vertical:
|
402 |
|
|
begin
|
403 |
|
|
case (blk4x4_intra_calculate_counter)
|
404 |
|
|
4:PE0_in0 <= Intra_mbAddrB_window0;
|
405 |
|
|
3:PE0_in0 <= Intra_mbAddrB_window1;
|
406 |
|
|
2:PE0_in0 <= Intra_mbAddrB_window2;
|
407 |
|
|
1:PE0_in0 <= Intra_mbAddrB_window3;
|
408 |
|
|
default:PE0_in0 <= 0;
|
409 |
|
|
endcase
|
410 |
|
|
PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0;
|
411 |
|
|
PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0;
|
412 |
|
|
PE0_full_bypass <= 1; PE0_round_value <= 0; PE0_shift_len <= 0;
|
413 |
|
|
end
|
414 |
|
|
`Intra16x16_Horizontal:
|
415 |
|
|
begin
|
416 |
|
|
PE0_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window0:0;
|
417 |
|
|
PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0;
|
418 |
|
|
PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0;
|
419 |
|
|
PE0_full_bypass <= 1; PE0_round_value <= 0; PE0_shift_len <= 0;
|
420 |
|
|
end
|
421 |
|
|
`Intra16x16_DC:
|
422 |
|
|
if (blk4x4_rec_counter == 0)
|
423 |
|
|
case (blk4x4_intra_calculate_counter)
|
424 |
|
|
4:begin // A2 + B2 + C2 + D2
|
425 |
|
|
PE0_in0 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg0;
|
426 |
|
|
PE0_in1 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg1;
|
427 |
|
|
PE0_in2 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg2;
|
428 |
|
|
PE0_in3 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg3;
|
429 |
|
|
PE0_IsShift <= 0; PE0_IsStore <= 1; PE0_IsClip <= 0;
|
430 |
|
|
PE0_full_bypass <= 0; PE0_round_value <= 0; PE0_shift_len <= 0; end
|
431 |
|
|
3:begin // PE0 output + B1 + C1 + D1
|
432 |
|
|
PE0_in0 <= PE0_out_reg;
|
433 |
|
|
PE0_in1 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg1;
|
434 |
|
|
PE0_in2 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg2;
|
435 |
|
|
PE0_in3 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg3;
|
436 |
|
|
PE0_IsShift <= 0; PE0_IsStore <= 1; PE0_IsClip <= 0;
|
437 |
|
|
PE0_full_bypass <= 0; PE0_round_value <= 0; PE0_shift_len <= 0; end
|
438 |
|
|
2:begin // PE0 output + PE1 output + PE2 output + PE3 output
|
439 |
|
|
PE0_in0 <= PE0_out_reg; PE0_in1 <= PE1_out_reg;
|
440 |
|
|
PE0_in2 <= PE2_out_reg; PE0_in3 <= PE3_out_reg;
|
441 |
|
|
PE0_IsShift <= 0; PE0_IsStore <= 1; PE0_IsClip <= 0;
|
442 |
|
|
PE0_full_bypass <= 0; PE0_round_value <= 0; PE0_shift_len <= 0; end
|
443 |
|
|
1:begin // final DC output
|
444 |
|
|
PE0_in0 <= (!mbAddrA_availability && !mbAddrB_availability)? 16'd128:PE0_out_reg;
|
445 |
|
|
PE0_in1 <= PE1_out_reg; PE0_in2 <= 0; PE0_in3 <= 0;
|
446 |
|
|
PE0_IsShift <= 0; PE0_IsStore <= 1; PE0_IsClip <= 0;
|
447 |
|
|
PE0_full_bypass <= (!mbAddrA_availability && !mbAddrB_availability)? 1'b1 :1'b0;
|
448 |
|
|
PE0_round_value <= ( mbAddrA_availability && mbAddrB_availability)? 5'b10000:5'b01000;
|
449 |
|
|
PE0_shift_len <= ( mbAddrA_availability && mbAddrB_availability)? 3'b101 :3'b100;
|
450 |
|
|
end
|
451 |
|
|
default:begin
|
452 |
|
|
PE0_in0 <= 0; PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0;
|
453 |
|
|
PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0;
|
454 |
|
|
PE0_full_bypass <= 0; PE0_round_value <= 0; PE0_shift_len <= 0; end
|
455 |
|
|
endcase
|
456 |
|
|
else
|
457 |
|
|
begin
|
458 |
|
|
PE0_in0 <= 0; PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0;
|
459 |
|
|
PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0;
|
460 |
|
|
PE0_full_bypass <= 0; PE0_round_value <= 0; PE0_shift_len <= 0;
|
461 |
|
|
end
|
462 |
|
|
`Intra16x16_Plane:
|
463 |
|
|
begin
|
464 |
|
|
if (blk4x4_intra_calculate_counter != 0)
|
465 |
|
|
//blk0,2,4,6,8,10,12,14,calc counter == 3'b100:PE0_in0 <= seed;
|
466 |
|
|
//other cases :PE0_in0 <= left pixel output
|
467 |
|
|
PE0_in0 <= (blk4x4_intra_calculate_counter == 4 && blk4x4_rec_counter[0] == 1'b0)?
|
468 |
|
|
seed:PE0_out_reg;
|
469 |
|
|
else
|
470 |
|
|
PE0_in0 <= 0;
|
471 |
|
|
//blk0,2,8,10,calc counter == 3'b100:PE0_in1 <= c_ext
|
472 |
|
|
//other cases :PE0_in1 <= b_ext
|
473 |
|
|
if (blk4x4_intra_calculate_counter != 0)
|
474 |
|
|
PE0_in1 <= (blk4x4_intra_calculate_counter == 4 && !blk4x4_rec_counter[2] && !blk4x4_rec_counter[0])?
|
475 |
|
|
c_ext:b_ext;
|
476 |
|
|
else
|
477 |
|
|
PE0_in1 <= 0;
|
478 |
|
|
PE0_in2 <= 0; PE0_in3 <= 0;
|
479 |
|
|
PE0_IsShift <= 1'b0;
|
480 |
|
|
PE0_IsStore <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0;
|
481 |
|
|
PE0_IsClip <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0;
|
482 |
|
|
PE0_full_bypass <= 1'b0;
|
483 |
|
|
PE0_round_value <= (blk4x4_intra_calculate_counter != 0)? 5'd16:5'd0;
|
484 |
|
|
PE0_shift_len <= (blk4x4_intra_calculate_counter != 0)? 3'd5 :3'd0;
|
485 |
|
|
end
|
486 |
|
|
endcase
|
487 |
|
|
//Chroma
|
488 |
|
|
else if (mb_type_general[3] == 1'b1 && blk4x4_rec_counter > 15)
|
489 |
|
|
case (Intra_chroma_predmode)
|
490 |
|
|
`Intra_chroma_DC:
|
491 |
|
|
begin
|
492 |
|
|
case ({mbAddrA_availability,mbAddrB_availability})
|
493 |
|
|
2'b00:PE0_in0 <= (blk4x4_intra_calculate_counter == 3)? 15'd128:15'd0;
|
494 |
|
|
2'b01:PE0_in0 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window0:
|
495 |
|
|
(blk4x4_intra_calculate_counter == 3)? PE0_out_reg:0;
|
496 |
|
|
2'b10:PE0_in0 <= (blk4x4_intra_calculate_counter == 3)? PE1_out_reg:0;
|
497 |
|
|
2'b11:
|
498 |
|
|
if (blk4x4_intra_calculate_counter == 4)
|
499 |
|
|
PE0_in0 <= (blk4x4_rec_counter == 18 || blk4x4_rec_counter == 22)?
|
500 |
|
|
0:Intra_mbAddrB_window0;
|
501 |
|
|
else if (blk4x4_intra_calculate_counter == 3)
|
502 |
|
|
PE0_in0 <= PE0_out_reg;
|
503 |
|
|
else
|
504 |
|
|
PE0_in0 <= 0;
|
505 |
|
|
endcase
|
506 |
|
|
case ({mbAddrA_availability,mbAddrB_availability})
|
507 |
|
|
2'b00:PE0_in1 <= 0;
|
508 |
|
|
2'b01:PE0_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window1:0;
|
509 |
|
|
2'b10:PE0_in1 <= 0;
|
510 |
|
|
2'b11:
|
511 |
|
|
if (blk4x4_intra_calculate_counter == 4)
|
512 |
|
|
PE0_in1 <= (blk4x4_rec_counter == 18 || blk4x4_rec_counter == 22)?
|
513 |
|
|
0:Intra_mbAddrB_window1;
|
514 |
|
|
else if (blk4x4_intra_calculate_counter == 3)
|
515 |
|
|
PE0_in1 <= PE1_out_reg;
|
516 |
|
|
else
|
517 |
|
|
PE0_in1 <= 0;
|
518 |
|
|
endcase
|
519 |
|
|
case (mbAddrB_availability)
|
520 |
|
|
1'b0:begin PE0_in2 <= 0; PE0_in3 <= 0; end
|
521 |
|
|
1'b1:
|
522 |
|
|
begin
|
523 |
|
|
if (blk4x4_intra_calculate_counter == 4)
|
524 |
|
|
begin
|
525 |
|
|
PE0_in2 <= ((blk4x4_rec_counter == 18 || blk4x4_rec_counter == 22) && mbAddrA_availability)?
|
526 |
|
|
0:Intra_mbAddrB_window2;
|
527 |
|
|
PE0_in3 <= ((blk4x4_rec_counter == 18 || blk4x4_rec_counter == 22) && mbAddrA_availability)?
|
528 |
|
|
0:Intra_mbAddrB_window3;
|
529 |
|
|
end
|
530 |
|
|
else
|
531 |
|
|
begin PE0_in2 <= 0; PE0_in3 <= 0; end
|
532 |
|
|
end
|
533 |
|
|
endcase
|
534 |
|
|
PE0_IsShift <= 1'b0;
|
535 |
|
|
PE0_IsStore <= (mbAddrB_availability && blk4x4_intra_calculate_counter == 4)? 1'b1:1'b0;
|
536 |
|
|
PE0_IsClip <= 1'b0;
|
537 |
|
|
PE0_full_bypass <= (!mbAddrA_availability && !mbAddrB_availability &&
|
538 |
|
|
blk4x4_intra_calculate_counter == 3)? 1'b1:1'b0;
|
539 |
|
|
case ({mbAddrA_availability,mbAddrB_availability})
|
540 |
|
|
2'b00 :begin PE0_round_value <= 0; PE0_shift_len <= 0; end
|
541 |
|
|
2'b01,2'b10 :begin PE0_round_value <= (blk4x4_intra_calculate_counter == 3)? 5'd2:5'd0;
|
542 |
|
|
PE0_shift_len <= (blk4x4_intra_calculate_counter == 3)? 3'd2:3'd0; end
|
543 |
|
|
2'b11:
|
544 |
|
|
begin
|
545 |
|
|
if (blk4x4_intra_calculate_counter == 3)
|
546 |
|
|
begin
|
547 |
|
|
PE0_round_value <= (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 19 ||
|
548 |
|
|
blk4x4_rec_counter == 20 || blk4x4_rec_counter == 23)? 5'd4:5'd2;
|
549 |
|
|
PE0_shift_len <= (blk4x4_rec_counter == 16 || blk4x4_rec_counter == 19 ||
|
550 |
|
|
blk4x4_rec_counter == 20 || blk4x4_rec_counter == 23)? 3'd3:3'd2;
|
551 |
|
|
end
|
552 |
|
|
else
|
553 |
|
|
begin PE0_round_value <= 0; PE0_shift_len <= 0; end
|
554 |
|
|
end
|
555 |
|
|
endcase
|
556 |
|
|
end
|
557 |
|
|
`Intra_chroma_Horizontal: //---horizontal---
|
558 |
|
|
begin
|
559 |
|
|
PE0_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window0:0;
|
560 |
|
|
PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0;
|
561 |
|
|
PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0;
|
562 |
|
|
PE0_full_bypass <= 1; PE0_round_value <= 0; PE0_shift_len <= 0;
|
563 |
|
|
end
|
564 |
|
|
`Intra_chroma_Vertical: //---vertical---
|
565 |
|
|
begin
|
566 |
|
|
case (blk4x4_intra_calculate_counter)
|
567 |
|
|
4:PE0_in0 <= Intra_mbAddrB_window0;
|
568 |
|
|
3:PE0_in0 <= Intra_mbAddrB_window1;
|
569 |
|
|
2:PE0_in0 <= Intra_mbAddrB_window2;
|
570 |
|
|
1:PE0_in0 <= Intra_mbAddrB_window3;
|
571 |
|
|
default:PE0_in0 <= 0;
|
572 |
|
|
endcase
|
573 |
|
|
PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0;
|
574 |
|
|
PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0;
|
575 |
|
|
PE0_full_bypass <= 1; PE0_round_value <= 0; PE0_shift_len <= 0;
|
576 |
|
|
end
|
577 |
|
|
`Intra_chroma_Plane: //---plane---
|
578 |
|
|
begin
|
579 |
|
|
if (blk4x4_intra_calculate_counter != 0)
|
580 |
|
|
//need seed, blk4x4 = 16 | 18 | 20 | 22
|
581 |
|
|
//do not need seed,blk4x4 = 17 | 19 | 21 | 23
|
582 |
|
|
PE0_in0 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)?
|
583 |
|
|
seed:PE0_out_reg;
|
584 |
|
|
else
|
585 |
|
|
PE0_in0 <= 0;
|
586 |
|
|
if (blk4x4_intra_calculate_counter != 0)
|
587 |
|
|
PE0_in1 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? c_ext:b_ext;
|
588 |
|
|
else
|
589 |
|
|
PE0_in1 <= 0;
|
590 |
|
|
PE0_in2 <= 0; PE0_in3 <= 0;
|
591 |
|
|
PE0_IsShift <= 1'b0;
|
592 |
|
|
PE0_IsStore <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0;
|
593 |
|
|
PE0_IsClip <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0;
|
594 |
|
|
PE0_full_bypass <= 1'b0;
|
595 |
|
|
PE0_round_value <= (blk4x4_intra_calculate_counter != 0)? 5'd16:5'd0;
|
596 |
|
|
PE0_shift_len <= (blk4x4_intra_calculate_counter != 0)? 3'd5 :3'd0;
|
597 |
|
|
end
|
598 |
|
|
endcase
|
599 |
|
|
else
|
600 |
|
|
begin
|
601 |
|
|
PE0_in0 <= 0; PE0_in1 <= 0; PE0_in2 <= 0; PE0_in3 <= 0;
|
602 |
|
|
PE0_IsShift <= 0; PE0_IsStore <= 0; PE0_IsClip <= 0;
|
603 |
|
|
PE0_full_bypass <= 0; PE0_round_value <= 0; PE0_shift_len <= 0;
|
604 |
|
|
end
|
605 |
|
|
//----
|
606 |
|
|
//PE1 |
|
607 |
|
|
//----
|
608 |
|
|
always @ (mb_type_general or blk4x4_rec_counter or blk4x4_intra_calculate_counter
|
609 |
|
|
or Intra4x4_predmode or Intra16x16_predmode or Intra_chroma_predmode
|
610 |
|
|
or blkAddrA_availability or mbAddrA_availability or mbAddrB_availability
|
611 |
|
|
|
612 |
|
|
or Intra_mbAddrA_window0 or Intra_mbAddrA_window1 or Intra_mbAddrA_window2 or Intra_mbAddrA_window3
|
613 |
|
|
or Intra_mbAddrB_window0 or Intra_mbAddrB_window1 or Intra_mbAddrB_window2 or Intra_mbAddrB_window3
|
614 |
|
|
or Intra_mbAddrD_window
|
615 |
|
|
|
616 |
|
|
or Intra_mbAddrA_reg4 or Intra_mbAddrA_reg5 or Intra_mbAddrA_reg6 or Intra_mbAddrA_reg7
|
617 |
|
|
or Intra_mbAddrB_reg0 or Intra_mbAddrB_reg4 or Intra_mbAddrB_reg5 or Intra_mbAddrB_reg6
|
618 |
|
|
or Intra_mbAddrB_reg7 or Intra_mbAddrB_reg8 or Intra_mbAddrB_reg12
|
619 |
|
|
|
620 |
|
|
or PE1_out_reg
|
621 |
|
|
or blk4x4_pred_output0 or blk4x4_pred_output1 or blk4x4_pred_output2
|
622 |
|
|
or blk4x4_pred_output8 or blk4x4_pred_output9 or blk4x4_pred_output12
|
623 |
|
|
or blk4x4_pred_output13 or blk4x4_pred_output14
|
624 |
|
|
or seed or b_ext or c_ext)
|
625 |
|
|
//Intra 4x4
|
626 |
|
|
if (mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16)
|
627 |
|
|
case (Intra4x4_predmode)
|
628 |
|
|
`Intra4x4_Vertical: //---Vertical---
|
629 |
|
|
begin
|
630 |
|
|
case (blk4x4_intra_calculate_counter)
|
631 |
|
|
4:PE1_in0 <= Intra_mbAddrB_window0;
|
632 |
|
|
3:PE1_in0 <= Intra_mbAddrB_window1;
|
633 |
|
|
2:PE1_in0 <= Intra_mbAddrB_window2;
|
634 |
|
|
1:PE1_in0 <= Intra_mbAddrB_window3;
|
635 |
|
|
default:PE1_in0 <= 0;
|
636 |
|
|
endcase
|
637 |
|
|
PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0;
|
638 |
|
|
PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0;
|
639 |
|
|
PE1_full_bypass <= 1; PE1_round_value <= 0; PE1_shift_len <= 0;
|
640 |
|
|
end
|
641 |
|
|
`Intra4x4_Horizontal: //---Horizontal---
|
642 |
|
|
begin
|
643 |
|
|
PE1_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window1:0;
|
644 |
|
|
PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0;
|
645 |
|
|
PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0;
|
646 |
|
|
PE1_full_bypass <= 1; PE1_round_value <= 0; PE1_shift_len <= 0;
|
647 |
|
|
end
|
648 |
|
|
`Intra4x4_DC: //---DC---
|
649 |
|
|
begin
|
650 |
|
|
PE1_in0 <= (blk4x4_intra_calculate_counter == 4 && blkAddrA_availability == 1)?
|
651 |
|
|
Intra_mbAddrA_window0:0;
|
652 |
|
|
PE1_in1 <= (blk4x4_intra_calculate_counter == 4 && blkAddrA_availability == 1)?
|
653 |
|
|
Intra_mbAddrA_window1:0;
|
654 |
|
|
PE1_in2 <= (blk4x4_intra_calculate_counter == 4 && blkAddrA_availability == 1)?
|
655 |
|
|
Intra_mbAddrA_window2:0;
|
656 |
|
|
PE1_in3 <= (blk4x4_intra_calculate_counter == 4 && blkAddrA_availability == 1)?
|
657 |
|
|
Intra_mbAddrA_window3:0;
|
658 |
|
|
PE1_IsStore <= (blk4x4_intra_calculate_counter == 4 && blkAddrA_availability == 1)? 1'b1:1'b0;
|
659 |
|
|
PE1_full_bypass <= 1'b0; PE1_IsShift <= 0; PE1_IsClip <= 0;
|
660 |
|
|
PE1_round_value <= 0; PE1_shift_len <= 0;
|
661 |
|
|
end
|
662 |
|
|
`Intra4x4_Diagonal_Down_Left: //---diagonal down-left---
|
663 |
|
|
begin
|
664 |
|
|
case (blk4x4_intra_calculate_counter)
|
665 |
|
|
4:PE1_in0 <= Intra_mbAddrB_window1;
|
666 |
|
|
3:PE1_in0 <= blk4x4_pred_output8;
|
667 |
|
|
2:PE1_in0 <= blk4x4_pred_output12;
|
668 |
|
|
1:PE1_in0 <= blk4x4_pred_output13;
|
669 |
|
|
default:PE1_in0 <= 0;
|
670 |
|
|
endcase
|
671 |
|
|
PE1_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window3:0;
|
672 |
|
|
PE1_in2 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window2:0;
|
673 |
|
|
PE1_in3 <= 0;
|
674 |
|
|
PE1_IsShift <= (blk4x4_intra_calculate_counter == 4)? 1'b1:1'b0;
|
675 |
|
|
PE1_IsStore <= 1'b0; PE1_IsClip <= 1'b0;
|
676 |
|
|
PE1_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1;
|
677 |
|
|
PE1_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'b00010:5'b0; // +2
|
678 |
|
|
PE1_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'b010 :3'b0; // >>2
|
679 |
|
|
end
|
680 |
|
|
`Intra4x4_Diagonal_Down_Right: //---diagonal down-right---
|
681 |
|
|
begin
|
682 |
|
|
case (blk4x4_intra_calculate_counter)
|
683 |
|
|
4:PE1_in0 <= Intra_mbAddrD_window;
|
684 |
|
|
3:PE1_in0 <= blk4x4_pred_output0;
|
685 |
|
|
2:PE1_in0 <= blk4x4_pred_output1;
|
686 |
|
|
1:PE1_in0 <= blk4x4_pred_output2;
|
687 |
|
|
default:PE1_in0 <= 0;
|
688 |
|
|
endcase
|
689 |
|
|
PE1_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window1:0;
|
690 |
|
|
PE1_in2 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window0:0;
|
691 |
|
|
PE1_in3 <= 0;
|
692 |
|
|
PE1_IsShift <= (blk4x4_intra_calculate_counter == 0)? 1'b0:1'b1;
|
693 |
|
|
PE1_IsStore <= 1'b0; PE1_IsClip <= 1'b0;
|
694 |
|
|
PE1_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1;
|
695 |
|
|
PE1_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'b0:5'b00010; // +2
|
696 |
|
|
PE1_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'b0:3'b010; // >>2
|
697 |
|
|
end
|
698 |
|
|
`Intra4x4_Vertical_Right: //---vertical right---
|
699 |
|
|
begin
|
700 |
|
|
case (blk4x4_intra_calculate_counter)
|
701 |
|
|
4:begin PE1_in0 <= Intra_mbAddrB_window0; PE1_in1 <= Intra_mbAddrA_window0;
|
702 |
|
|
PE1_in2 <= Intra_mbAddrD_window; end
|
703 |
|
|
3:begin PE1_in0 <= Intra_mbAddrD_window; PE1_in1 <= Intra_mbAddrB_window1;
|
704 |
|
|
PE1_in2 <= Intra_mbAddrB_window0; end
|
705 |
|
|
2:begin PE1_in0 <= Intra_mbAddrB_window0; PE1_in1 <= Intra_mbAddrB_window2;
|
706 |
|
|
PE1_in2 <= Intra_mbAddrB_window1; end
|
707 |
|
|
1:begin PE1_in0 <= Intra_mbAddrB_window1; PE1_in1 <= Intra_mbAddrB_window3;
|
708 |
|
|
PE1_in2 <= Intra_mbAddrB_window2; end
|
709 |
|
|
default:begin PE1_in0 <= 0;PE1_in1 <= 0;PE1_in2 <= 0; end
|
710 |
|
|
endcase
|
711 |
|
|
PE1_in3 <= 0;
|
712 |
|
|
PE1_IsShift <= (blk4x4_intra_calculate_counter == 0)? 1'b0:1'b1;
|
713 |
|
|
PE1_IsStore <= 1'b0; PE1_IsClip <= 1'b0; PE1_full_bypass <= 1'b0;
|
714 |
|
|
PE1_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'b0:5'b00010; // +2
|
715 |
|
|
PE1_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'b0:3'b010; // >>2
|
716 |
|
|
end
|
717 |
|
|
`Intra4x4_Horizontal_Down: //---horizontal down---
|
718 |
|
|
begin
|
719 |
|
|
case (blk4x4_intra_calculate_counter)
|
720 |
|
|
4:PE1_in0 <= Intra_mbAddrA_window0;
|
721 |
|
|
3:PE1_in0 <= Intra_mbAddrD_window;
|
722 |
|
|
2:PE1_in0 <= blk4x4_pred_output0;
|
723 |
|
|
1:PE1_in0 <= blk4x4_pred_output1;
|
724 |
|
|
default:PE1_in0 <= 0;
|
725 |
|
|
endcase
|
726 |
|
|
PE1_in1 <= (blk4x4_intra_calculate_counter == 4 || blk4x4_intra_calculate_counter == 3)?
|
727 |
|
|
Intra_mbAddrA_window1:0;
|
728 |
|
|
PE1_in2 <= (blk4x4_intra_calculate_counter == 3)? Intra_mbAddrA_window0:0;
|
729 |
|
|
PE1_in3 <= 0;
|
730 |
|
|
PE1_IsShift <= (blk4x4_intra_calculate_counter == 3)? 1'b1:1'b0;
|
731 |
|
|
PE1_IsStore <= 1'b0; PE1_IsClip <= 1'b0;
|
732 |
|
|
PE1_full_bypass <= (blk4x4_intra_calculate_counter == 2 ||
|
733 |
|
|
blk4x4_intra_calculate_counter == 1)? 1'b1:1'b0;
|
734 |
|
|
PE1_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'd1:
|
735 |
|
|
(blk4x4_intra_calculate_counter == 3)? 5'd2:5'd0;
|
736 |
|
|
PE1_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'd1:
|
737 |
|
|
(blk4x4_intra_calculate_counter == 3)? 3'd2:3'd0;
|
738 |
|
|
end
|
739 |
|
|
`Intra4x4_Vertical_Left: //---vertical left---
|
740 |
|
|
begin
|
741 |
|
|
case (blk4x4_intra_calculate_counter)
|
742 |
|
|
4:PE1_in0 <= Intra_mbAddrB_window0;
|
743 |
|
|
3:PE1_in0 <= blk4x4_pred_output12;
|
744 |
|
|
2:PE1_in0 <= blk4x4_pred_output13;
|
745 |
|
|
1:PE1_in0 <= blk4x4_pred_output14;
|
746 |
|
|
default:PE1_in0 <= 0;
|
747 |
|
|
endcase
|
748 |
|
|
PE1_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window2:0;
|
749 |
|
|
PE1_in2 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window1:0;
|
750 |
|
|
PE1_in3 <= 0;
|
751 |
|
|
PE1_IsShift <= (blk4x4_intra_calculate_counter == 4)? 1'b1:1'b0;
|
752 |
|
|
PE1_IsStore <= 1'b0; PE1_IsClip <= 1'b0;
|
753 |
|
|
PE1_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1;
|
754 |
|
|
PE1_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'd2:5'd0; // +2
|
755 |
|
|
PE1_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'd2:3'd0; // >>2
|
756 |
|
|
end
|
757 |
|
|
`Intra4x4_Horizontal_Up: //---horizontal up---
|
758 |
|
|
begin
|
759 |
|
|
case (blk4x4_intra_calculate_counter)
|
760 |
|
|
4:PE1_in0 <= Intra_mbAddrA_window1;
|
761 |
|
|
3:PE1_in0 <= Intra_mbAddrA_window1;
|
762 |
|
|
2:PE1_in0 <= blk4x4_pred_output8;
|
763 |
|
|
1:PE1_in0 <= blk4x4_pred_output9;
|
764 |
|
|
default:PE1_in0 <= 0;
|
765 |
|
|
endcase
|
766 |
|
|
PE1_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window2:
|
767 |
|
|
(blk4x4_intra_calculate_counter == 3)? Intra_mbAddrA_window3:0;
|
768 |
|
|
PE1_in2 <= (blk4x4_intra_calculate_counter == 3)? Intra_mbAddrA_window2:0;
|
769 |
|
|
PE1_in3 <= 0;
|
770 |
|
|
PE1_IsShift <= (blk4x4_intra_calculate_counter == 3)? 1'b1:1'b0;
|
771 |
|
|
PE1_IsStore <= 1'b0; PE1_IsClip <= 1'b0;
|
772 |
|
|
PE1_full_bypass <= (blk4x4_intra_calculate_counter == 2 ||
|
773 |
|
|
blk4x4_intra_calculate_counter == 1)? 1'b1:1'b0;
|
774 |
|
|
PE1_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'd1:
|
775 |
|
|
(blk4x4_intra_calculate_counter == 3)? 5'd2:5'd0;
|
776 |
|
|
PE1_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'd1:
|
777 |
|
|
(blk4x4_intra_calculate_counter == 3)? 3'd2:3'd0;
|
778 |
|
|
end
|
779 |
|
|
default:
|
780 |
|
|
begin
|
781 |
|
|
PE1_in0 <= 0; PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0;
|
782 |
|
|
PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0;
|
783 |
|
|
PE1_full_bypass <= 0; PE1_round_value <= 0; PE1_shift_len <= 0;
|
784 |
|
|
end
|
785 |
|
|
endcase
|
786 |
|
|
//Intra16x16
|
787 |
|
|
else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16)
|
788 |
|
|
case (Intra16x16_predmode)
|
789 |
|
|
`Intra16x16_Vertical: //---Vertical---
|
790 |
|
|
begin
|
791 |
|
|
case (blk4x4_intra_calculate_counter)
|
792 |
|
|
4:PE1_in0 <= Intra_mbAddrB_window0;
|
793 |
|
|
3:PE1_in0 <= Intra_mbAddrB_window1;
|
794 |
|
|
2:PE1_in0 <= Intra_mbAddrB_window2;
|
795 |
|
|
1:PE1_in0 <= Intra_mbAddrB_window3;
|
796 |
|
|
default:PE1_in0 <= 0;
|
797 |
|
|
endcase
|
798 |
|
|
PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0;
|
799 |
|
|
PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0;
|
800 |
|
|
PE1_full_bypass <= 1; PE1_round_value <= 0; PE1_shift_len <= 0;
|
801 |
|
|
end
|
802 |
|
|
`Intra16x16_Horizontal: //---Horizontal---
|
803 |
|
|
begin
|
804 |
|
|
PE1_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window1:0;
|
805 |
|
|
PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0;
|
806 |
|
|
PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0;
|
807 |
|
|
PE1_full_bypass <= 1; PE1_round_value <= 0; PE1_shift_len <= 0;
|
808 |
|
|
end
|
809 |
|
|
`Intra16x16_DC: //---DC---
|
810 |
|
|
if (blk4x4_rec_counter == 0)
|
811 |
|
|
case (blk4x4_intra_calculate_counter)
|
812 |
|
|
4:begin // E2 + F2 + G2 + H2
|
813 |
|
|
PE1_in0 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg4;
|
814 |
|
|
PE1_in1 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg5;
|
815 |
|
|
PE1_in2 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg6;
|
816 |
|
|
PE1_in3 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg7;
|
817 |
|
|
PE1_IsShift <= 0; PE1_IsStore <= 1; PE1_IsClip <= 0;
|
818 |
|
|
PE1_full_bypass <= 0; PE1_round_value <= 0; PE1_shift_len <= 0; end
|
819 |
|
|
3:begin // PE1 output + F1 + G1 + H1
|
820 |
|
|
PE1_in0 <= PE1_out_reg;
|
821 |
|
|
PE1_in1 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg5;
|
822 |
|
|
PE1_in2 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg6;
|
823 |
|
|
PE1_in3 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg7;
|
824 |
|
|
PE1_IsShift <= 0; PE1_IsStore <= 1; PE1_IsClip <= 0;
|
825 |
|
|
PE1_full_bypass <= 0; PE1_round_value <= 0; PE1_shift_len <= 0; end
|
826 |
|
|
2:begin // A1 + E1 + I1 + M1
|
827 |
|
|
PE1_in0 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg0;
|
828 |
|
|
PE1_in1 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg4;
|
829 |
|
|
PE1_in2 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg8;
|
830 |
|
|
PE1_in3 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg12;
|
831 |
|
|
PE1_IsShift <= 0; PE1_IsStore <= 1; PE1_IsClip <= 0;
|
832 |
|
|
PE1_full_bypass <= 0; PE1_round_value <= 0; PE1_shift_len <= 0; end
|
833 |
|
|
default:begin
|
834 |
|
|
PE1_in0 <= 0; PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0;
|
835 |
|
|
PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0;
|
836 |
|
|
PE1_full_bypass <= 0; PE1_round_value <= 0; PE1_shift_len <= 0; end
|
837 |
|
|
endcase
|
838 |
|
|
else
|
839 |
|
|
begin
|
840 |
|
|
PE1_in0 <= 0; PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0;
|
841 |
|
|
PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0;
|
842 |
|
|
PE1_full_bypass <= 0; PE1_round_value <= 0; PE1_shift_len <= 0;
|
843 |
|
|
end
|
844 |
|
|
`Intra16x16_Plane: //---plane---
|
845 |
|
|
begin
|
846 |
|
|
if (blk4x4_intra_calculate_counter != 0)
|
847 |
|
|
//blk0,2,4,6,8,10,12,14,calc counter == 3'b100:PE1_in0 <= seed;
|
848 |
|
|
//other cases :PE1_in0 <= left pixel output
|
849 |
|
|
PE1_in0 <= (blk4x4_intra_calculate_counter == 4 && blk4x4_rec_counter[0] == 1'b0)?
|
850 |
|
|
seed:PE1_out_reg;
|
851 |
|
|
else
|
852 |
|
|
PE1_in0 <= 0;
|
853 |
|
|
if (blk4x4_intra_calculate_counter != 0)
|
854 |
|
|
//blk0,2,8,10,calc counter == 3'b100:PE1_in1 <= c_ext x 2
|
855 |
|
|
//other cases :PE1_in1 <= b_ext
|
856 |
|
|
PE1_in1 <= (blk4x4_intra_calculate_counter == 4 && !blk4x4_rec_counter[2] && !blk4x4_rec_counter[0])?
|
857 |
|
|
{c_ext[14:0],1'b0}:b_ext;
|
858 |
|
|
else
|
859 |
|
|
PE1_in1 <= 0;
|
860 |
|
|
//blk4,6,12,14,calc counter == 3'b100:PE1_in2 <= c_ext;
|
861 |
|
|
//other cases :PE1_in2 <= 0
|
862 |
|
|
PE1_in2 <= (blk4x4_intra_calculate_counter == 4 && blk4x4_rec_counter[2] && !blk4x4_rec_counter[0])?
|
863 |
|
|
c_ext:0;
|
864 |
|
|
PE1_in3 <= 0;
|
865 |
|
|
PE1_IsShift <= 1'b0;
|
866 |
|
|
PE1_IsStore <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0;
|
867 |
|
|
PE1_IsClip <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0;
|
868 |
|
|
PE1_full_bypass <= 1'b0;
|
869 |
|
|
PE1_round_value <= (blk4x4_intra_calculate_counter != 0)? 5'd16:5'd0;
|
870 |
|
|
PE1_shift_len <= (blk4x4_intra_calculate_counter != 0)? 3'd5 :3'd0;
|
871 |
|
|
end
|
872 |
|
|
endcase
|
873 |
|
|
//Chroma
|
874 |
|
|
else if (mb_type_general[3] == 1'b1 && blk4x4_rec_counter > 15)
|
875 |
|
|
case (Intra_chroma_predmode)
|
876 |
|
|
`Intra_chroma_DC: //---DC---
|
877 |
|
|
if (blk4x4_intra_calculate_counter == 4)
|
878 |
|
|
begin
|
879 |
|
|
case ({mbAddrA_availability,mbAddrB_availability})
|
880 |
|
|
2'b00,2'b01:
|
881 |
|
|
begin
|
882 |
|
|
PE1_in0 <= 0; PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0;
|
883 |
|
|
end
|
884 |
|
|
2'b10:
|
885 |
|
|
begin
|
886 |
|
|
PE1_in0 <= Intra_mbAddrA_window0; PE1_in1 <= Intra_mbAddrA_window1;
|
887 |
|
|
PE1_in2 <= Intra_mbAddrA_window2; PE1_in3 <= Intra_mbAddrA_window3;
|
888 |
|
|
end
|
889 |
|
|
2'b11:
|
890 |
|
|
begin
|
891 |
|
|
PE1_in0 <= (blk4x4_rec_counter == 17 || blk4x4_rec_counter == 21)?
|
892 |
|
|
0:Intra_mbAddrA_window0;
|
893 |
|
|
PE1_in1 <= (blk4x4_rec_counter == 17 || blk4x4_rec_counter == 21)?
|
894 |
|
|
0:Intra_mbAddrA_window1;
|
895 |
|
|
PE1_in2 <= (blk4x4_rec_counter == 17 || blk4x4_rec_counter == 21)?
|
896 |
|
|
0:Intra_mbAddrA_window2;
|
897 |
|
|
PE1_in3 <= (blk4x4_rec_counter == 17 || blk4x4_rec_counter == 21)?
|
898 |
|
|
0:Intra_mbAddrA_window3;
|
899 |
|
|
end
|
900 |
|
|
endcase
|
901 |
|
|
PE1_IsShift <= 1'b0; PE1_IsClip <= 1'b0;
|
902 |
|
|
PE1_IsStore <= (mbAddrA_availability)? 1'b1:1'b0;
|
903 |
|
|
PE1_full_bypass <= 1'b0;
|
904 |
|
|
PE1_round_value <= 0; PE1_shift_len <= 0;
|
905 |
|
|
end
|
906 |
|
|
else
|
907 |
|
|
begin
|
908 |
|
|
PE1_in0 <= 0; PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0;
|
909 |
|
|
PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0;
|
910 |
|
|
PE1_full_bypass <= 0; PE1_round_value <= 0; PE1_shift_len <= 0;
|
911 |
|
|
end
|
912 |
|
|
`Intra_chroma_Horizontal: //---horizontal---
|
913 |
|
|
begin
|
914 |
|
|
PE1_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window1:0;
|
915 |
|
|
PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0;
|
916 |
|
|
PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0;
|
917 |
|
|
PE1_full_bypass <= 1; PE1_round_value <= 0; PE1_shift_len <= 0;
|
918 |
|
|
end
|
919 |
|
|
`Intra_chroma_Vertical: //---vertical---
|
920 |
|
|
begin
|
921 |
|
|
case (blk4x4_intra_calculate_counter)
|
922 |
|
|
4:PE1_in0 <= Intra_mbAddrB_window0;
|
923 |
|
|
3:PE1_in0 <= Intra_mbAddrB_window1;
|
924 |
|
|
2:PE1_in0 <= Intra_mbAddrB_window2;
|
925 |
|
|
1:PE1_in0 <= Intra_mbAddrB_window3;
|
926 |
|
|
default:PE1_in0 <= 0;
|
927 |
|
|
endcase
|
928 |
|
|
PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0;
|
929 |
|
|
PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0;
|
930 |
|
|
PE1_full_bypass <= 1; PE1_round_value <= 0; PE1_shift_len <= 0;
|
931 |
|
|
end
|
932 |
|
|
`Intra_chroma_Plane: //---plane---
|
933 |
|
|
begin
|
934 |
|
|
if (blk4x4_intra_calculate_counter != 0)
|
935 |
|
|
//need seed, blk4x4 = 16 | 18 | 20 | 22
|
936 |
|
|
//do not need seed,blk4x4 = 17 | 19 | 21 | 23
|
937 |
|
|
PE1_in0 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)?
|
938 |
|
|
seed:PE1_out_reg;
|
939 |
|
|
else
|
940 |
|
|
PE1_in0 <= 0;
|
941 |
|
|
if (blk4x4_intra_calculate_counter != 0)
|
942 |
|
|
PE1_in1 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)?
|
943 |
|
|
0:b_ext;
|
944 |
|
|
else
|
945 |
|
|
PE1_in1 <= 0;
|
946 |
|
|
//0,2,8,10,the 4th cycle,+2c
|
947 |
|
|
PE1_in2 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)? c_ext:0;
|
948 |
|
|
PE1_in3 <= 0;
|
949 |
|
|
PE1_IsShift <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)?
|
950 |
|
|
1'b1:1'b0;
|
951 |
|
|
PE1_IsStore <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0;
|
952 |
|
|
PE1_IsClip <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0;
|
953 |
|
|
PE1_full_bypass <= 1'b0;
|
954 |
|
|
PE1_round_value <= (blk4x4_intra_calculate_counter != 0)? 5'd16:5'd0;
|
955 |
|
|
PE1_shift_len <= (blk4x4_intra_calculate_counter != 0)? 3'd5 :3'd0;
|
956 |
|
|
end
|
957 |
|
|
endcase
|
958 |
|
|
else
|
959 |
|
|
begin
|
960 |
|
|
PE1_in0 <= 0; PE1_in1 <= 0; PE1_in2 <= 0; PE1_in3 <= 0;
|
961 |
|
|
PE1_IsShift <= 0; PE1_IsStore <= 0; PE1_IsClip <= 0;
|
962 |
|
|
PE1_full_bypass <= 0; PE1_round_value <= 0; PE1_shift_len <= 0;
|
963 |
|
|
end
|
964 |
|
|
|
965 |
|
|
//----
|
966 |
|
|
//PE2 |
|
967 |
|
|
//----
|
968 |
|
|
always @ (mb_type_general or blk4x4_rec_counter or blk4x4_intra_calculate_counter
|
969 |
|
|
or Intra4x4_predmode or Intra16x16_predmode or Intra_chroma_predmode
|
970 |
|
|
or mbAddrA_availability or mbAddrB_availability
|
971 |
|
|
|
972 |
|
|
or Intra_mbAddrA_window0 or Intra_mbAddrA_window1 or Intra_mbAddrA_window2 or Intra_mbAddrA_window3
|
973 |
|
|
or Intra_mbAddrB_window0 or Intra_mbAddrB_window1 or Intra_mbAddrB_window2 or Intra_mbAddrB_window3
|
974 |
|
|
or Intra_mbAddrD_window
|
975 |
|
|
or Intra_mbAddrC_window0 or Intra_mbAddrC_window1
|
976 |
|
|
|
977 |
|
|
or Intra_mbAddrA_reg8 or Intra_mbAddrA_reg9 or Intra_mbAddrA_reg10 or Intra_mbAddrA_reg11
|
978 |
|
|
or Intra_mbAddrB_reg9 or Intra_mbAddrB_reg10 or Intra_mbAddrB_reg11
|
979 |
|
|
or blk4x4_pred_output0 or blk4x4_pred_output1 or blk4x4_pred_output2
|
980 |
|
|
or blk4x4_pred_output4 or blk4x4_pred_output5 or blk4x4_pred_output12
|
981 |
|
|
or blk4x4_pred_output13 or blk4x4_pred_output14
|
982 |
|
|
or PE2_out_reg
|
983 |
|
|
|
984 |
|
|
or seed or b_ext or c_ext)
|
985 |
|
|
//Intra 4x4
|
986 |
|
|
if (mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16)
|
987 |
|
|
case (Intra4x4_predmode)
|
988 |
|
|
`Intra4x4_Vertical: //---Vertical---
|
989 |
|
|
begin
|
990 |
|
|
case (blk4x4_intra_calculate_counter)
|
991 |
|
|
4:PE2_in0 <= Intra_mbAddrB_window0;
|
992 |
|
|
3:PE2_in0 <= Intra_mbAddrB_window1;
|
993 |
|
|
2:PE2_in0 <= Intra_mbAddrB_window2;
|
994 |
|
|
1:PE2_in0 <= Intra_mbAddrB_window3;
|
995 |
|
|
default:PE2_in0 <= 0;
|
996 |
|
|
endcase
|
997 |
|
|
PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0;
|
998 |
|
|
PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0;
|
999 |
|
|
PE2_full_bypass <= 1; PE2_round_value <= 0; PE2_shift_len <= 0;
|
1000 |
|
|
end
|
1001 |
|
|
`Intra4x4_Horizontal: //---Horizontal---
|
1002 |
|
|
begin
|
1003 |
|
|
PE2_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window2:0;
|
1004 |
|
|
PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0;
|
1005 |
|
|
PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0;
|
1006 |
|
|
PE2_full_bypass <= 1; PE2_round_value <= 0; PE2_shift_len <= 0;
|
1007 |
|
|
end
|
1008 |
|
|
//-------------
|
1009 |
|
|
//no PE2 for DC
|
1010 |
|
|
//4'b0010:
|
1011 |
|
|
//-------------
|
1012 |
|
|
`Intra4x4_Diagonal_Down_Left: //---diagonal down-left---
|
1013 |
|
|
begin
|
1014 |
|
|
case (blk4x4_intra_calculate_counter)
|
1015 |
|
|
4:PE2_in0 <= Intra_mbAddrB_window2;
|
1016 |
|
|
3:PE2_in0 <= blk4x4_pred_output12;
|
1017 |
|
|
2:PE2_in0 <= blk4x4_pred_output13;
|
1018 |
|
|
1:PE2_in0 <= blk4x4_pred_output14;
|
1019 |
|
|
default:PE2_in0 <= 0;
|
1020 |
|
|
endcase
|
1021 |
|
|
PE2_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrC_window0:0;
|
1022 |
|
|
PE2_in2 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrB_window3:0;
|
1023 |
|
|
PE2_in3 <= 0;
|
1024 |
|
|
PE2_IsShift <= (blk4x4_intra_calculate_counter == 4)? 1'b1:1'b0;
|
1025 |
|
|
PE2_IsStore <= 1'b0; PE2_IsClip <= 1'b0;
|
1026 |
|
|
PE2_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1;
|
1027 |
|
|
PE2_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'd2:5'd0; // +2
|
1028 |
|
|
PE2_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'd2:3'd0; // >>2
|
1029 |
|
|
end
|
1030 |
|
|
`Intra4x4_Diagonal_Down_Right: //---diagonal down-right---
|
1031 |
|
|
begin
|
1032 |
|
|
case (blk4x4_intra_calculate_counter)
|
1033 |
|
|
4:PE2_in0 <= Intra_mbAddrA_window0;
|
1034 |
|
|
3:PE2_in0 <= blk4x4_pred_output4;
|
1035 |
|
|
2:PE2_in0 <= blk4x4_pred_output0;
|
1036 |
|
|
1:PE2_in0 <= blk4x4_pred_output1;
|
1037 |
|
|
default:PE2_in0 <= 0;
|
1038 |
|
|
endcase
|
1039 |
|
|
PE2_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window2:0;
|
1040 |
|
|
PE2_in2 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window1:0;
|
1041 |
|
|
PE2_in3 <= 0;
|
1042 |
|
|
PE2_IsShift <= (blk4x4_intra_calculate_counter == 0)? 1'b0:1'b1;
|
1043 |
|
|
PE2_IsStore <= 1'b0; PE2_IsClip <= 1'b0;
|
1044 |
|
|
PE2_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1;
|
1045 |
|
|
PE2_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'd0:5'd2; // +2
|
1046 |
|
|
PE2_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'd0:3'd2; // >>2
|
1047 |
|
|
end
|
1048 |
|
|
`Intra4x4_Vertical_Right: //---vertical right---
|
1049 |
|
|
begin
|
1050 |
|
|
case (blk4x4_intra_calculate_counter)
|
1051 |
|
|
4:PE2_in0 <= Intra_mbAddrD_window;
|
1052 |
|
|
3:PE2_in0 <= blk4x4_pred_output0;
|
1053 |
|
|
2:PE2_in0 <= blk4x4_pred_output1;
|
1054 |
|
|
1:PE2_in0 <= blk4x4_pred_output2;
|
1055 |
|
|
default:PE2_in0 <= 0;
|
1056 |
|
|
endcase
|
1057 |
|
|
PE2_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window1:0;
|
1058 |
|
|
PE2_in2 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window0:0;
|
1059 |
|
|
PE2_in3 <= 0;
|
1060 |
|
|
PE2_IsShift <= (blk4x4_intra_calculate_counter == 0)? 1'b0:1'b1;
|
1061 |
|
|
PE2_IsStore <= 1'b0; PE2_IsClip <= 1'b0;
|
1062 |
|
|
PE2_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1;
|
1063 |
|
|
PE2_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'd0:5'd2; // +2
|
1064 |
|
|
PE2_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'd0:3'd2; // >>2
|
1065 |
|
|
end
|
1066 |
|
|
`Intra4x4_Horizontal_Down: //---horizontal down---
|
1067 |
|
|
begin
|
1068 |
|
|
case (blk4x4_intra_calculate_counter)
|
1069 |
|
|
4:PE2_in0 <= Intra_mbAddrA_window1;
|
1070 |
|
|
3:PE2_in0 <= Intra_mbAddrA_window0;
|
1071 |
|
|
2:PE2_in0 <= blk4x4_pred_output4;
|
1072 |
|
|
1:PE2_in0 <= blk4x4_pred_output5;
|
1073 |
|
|
default:PE2_in0 <= 0;
|
1074 |
|
|
endcase
|
1075 |
|
|
PE2_in1 <= (blk4x4_intra_calculate_counter == 4 || blk4x4_intra_calculate_counter == 3)?
|
1076 |
|
|
Intra_mbAddrA_window2:0;
|
1077 |
|
|
PE2_in2 <= (blk4x4_intra_calculate_counter == 3)? Intra_mbAddrA_window1:0;
|
1078 |
|
|
PE2_in3 <= 0;
|
1079 |
|
|
PE2_IsShift <= (blk4x4_intra_calculate_counter == 3)? 1'b1:1'b0;
|
1080 |
|
|
PE2_IsStore <= 1'b0; PE2_IsClip <= 1'b0;
|
1081 |
|
|
PE2_full_bypass <= (blk4x4_intra_calculate_counter == 2 ||
|
1082 |
|
|
blk4x4_intra_calculate_counter == 1)? 1'b1:1'b0;
|
1083 |
|
|
PE2_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'd1:
|
1084 |
|
|
(blk4x4_intra_calculate_counter == 3)? 5'd2:5'd0;
|
1085 |
|
|
PE2_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'd1:
|
1086 |
|
|
(blk4x4_intra_calculate_counter == 3)? 3'd2:3'd0;
|
1087 |
|
|
end
|
1088 |
|
|
`Intra4x4_Vertical_Left: //---vertical left---
|
1089 |
|
|
begin
|
1090 |
|
|
case (blk4x4_intra_calculate_counter)
|
1091 |
|
|
4:PE2_in0 <= Intra_mbAddrB_window1;
|
1092 |
|
|
3:PE2_in0 <= Intra_mbAddrB_window3;
|
1093 |
|
|
2:PE2_in0 <= Intra_mbAddrB_window3;
|
1094 |
|
|
1:PE2_in0 <= Intra_mbAddrC_window1;
|
1095 |
|
|
default:PE2_in0 <= 0;
|
1096 |
|
|
endcase
|
1097 |
|
|
case (blk4x4_intra_calculate_counter)
|
1098 |
|
|
4,3:PE2_in1 <= Intra_mbAddrB_window2;
|
1099 |
|
|
2,1:PE2_in1 <= Intra_mbAddrC_window0;
|
1100 |
|
|
default:PE2_in1 <= 0;
|
1101 |
|
|
endcase
|
1102 |
|
|
PE2_in2 <= 0; PE2_in3 <= 0;
|
1103 |
|
|
PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 1'b0; PE2_full_bypass <= 1'b0;
|
1104 |
|
|
PE2_round_value <= (blk4x4_intra_calculate_counter != 0)? 5'd1:5'd0; // +1
|
1105 |
|
|
PE2_shift_len <= (blk4x4_intra_calculate_counter != 0)? 3'd1:3'd0; // >>1
|
1106 |
|
|
end
|
1107 |
|
|
`Intra4x4_Horizontal_Up: //---horizontal up---
|
1108 |
|
|
begin
|
1109 |
|
|
case (blk4x4_intra_calculate_counter)
|
1110 |
|
|
4,3:PE2_in0 <= Intra_mbAddrA_window2;
|
1111 |
|
|
2,1:PE2_in0 <= blk4x4_pred_output12;
|
1112 |
|
|
default:PE2_in0 <= 0;
|
1113 |
|
|
endcase
|
1114 |
|
|
PE2_in1 <= (blk4x4_intra_calculate_counter == 4 || blk4x4_intra_calculate_counter == 3)?
|
1115 |
|
|
Intra_mbAddrA_window3:0;
|
1116 |
|
|
PE2_in2 <= (blk4x4_intra_calculate_counter == 3)? Intra_mbAddrA_window3:0;
|
1117 |
|
|
PE2_in3 <= 0;
|
1118 |
|
|
PE2_IsShift <= (blk4x4_intra_calculate_counter == 3)? 1'b1:1'b0;
|
1119 |
|
|
PE2_IsStore <= 1'b0; PE2_IsClip <= 1'b0;
|
1120 |
|
|
PE2_full_bypass <= (blk4x4_intra_calculate_counter == 2 ||
|
1121 |
|
|
blk4x4_intra_calculate_counter == 1)? 1'b1:1'b0;
|
1122 |
|
|
PE2_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'd1:
|
1123 |
|
|
(blk4x4_intra_calculate_counter == 3)? 5'd2:5'd0;
|
1124 |
|
|
PE2_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'd1:
|
1125 |
|
|
(blk4x4_intra_calculate_counter == 3)? 3'd2:3'd0;
|
1126 |
|
|
end
|
1127 |
|
|
default:
|
1128 |
|
|
begin
|
1129 |
|
|
PE2_in0 <= 0; PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0;
|
1130 |
|
|
PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0;
|
1131 |
|
|
PE2_full_bypass <= 0; PE2_round_value <= 0; PE2_shift_len <= 0;
|
1132 |
|
|
end
|
1133 |
|
|
endcase
|
1134 |
|
|
//Intra16x16
|
1135 |
|
|
else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16)
|
1136 |
|
|
case (Intra16x16_predmode)
|
1137 |
|
|
`Intra16x16_Vertical: //---Vertical---
|
1138 |
|
|
begin
|
1139 |
|
|
case (blk4x4_intra_calculate_counter)
|
1140 |
|
|
4:PE2_in0 <= Intra_mbAddrB_window0;
|
1141 |
|
|
3:PE2_in0 <= Intra_mbAddrB_window1;
|
1142 |
|
|
2:PE2_in0 <= Intra_mbAddrB_window2;
|
1143 |
|
|
1:PE2_in0 <= Intra_mbAddrB_window3;
|
1144 |
|
|
default:PE2_in0 <= 0;
|
1145 |
|
|
endcase
|
1146 |
|
|
PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0;
|
1147 |
|
|
PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0;
|
1148 |
|
|
PE2_full_bypass <= 1; PE2_round_value <= 0; PE2_shift_len <= 0;
|
1149 |
|
|
end
|
1150 |
|
|
`Intra16x16_Horizontal: //---Horizontal---
|
1151 |
|
|
begin
|
1152 |
|
|
PE2_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window2:0;
|
1153 |
|
|
PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0;
|
1154 |
|
|
PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0;
|
1155 |
|
|
PE2_full_bypass <= 1; PE2_round_value <= 0; PE2_shift_len <= 0;
|
1156 |
|
|
end
|
1157 |
|
|
`Intra16x16_DC: //---DC---
|
1158 |
|
|
if (blk4x4_rec_counter == 0)
|
1159 |
|
|
case (blk4x4_intra_calculate_counter)
|
1160 |
|
|
4:begin // I2 + J2 + K2 + L2
|
1161 |
|
|
PE2_in0 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg8;
|
1162 |
|
|
PE2_in1 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg9;
|
1163 |
|
|
PE2_in2 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg10;
|
1164 |
|
|
PE2_in3 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg11;
|
1165 |
|
|
PE2_IsShift <= 0; PE2_IsStore <= 1; PE2_IsClip <= 0;
|
1166 |
|
|
PE2_full_bypass <= 0; PE2_round_value <= 0; PE2_shift_len <= 0; end
|
1167 |
|
|
3:begin // PE2 output + J1 + K1 + L1
|
1168 |
|
|
PE2_in0 <= PE2_out_reg;
|
1169 |
|
|
PE2_in1 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg9;
|
1170 |
|
|
PE2_in2 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg10;
|
1171 |
|
|
PE2_in3 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg11;
|
1172 |
|
|
PE2_IsShift <= 0; PE2_IsStore <= 1; PE2_IsClip <= 0;
|
1173 |
|
|
PE2_full_bypass <= 0; PE2_round_value <= 0; PE2_shift_len <= 0; end
|
1174 |
|
|
default:begin
|
1175 |
|
|
PE2_in0 <= 0; PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0;
|
1176 |
|
|
PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0;
|
1177 |
|
|
PE2_full_bypass <= 0; PE2_round_value <= 0; PE2_shift_len <= 0; end
|
1178 |
|
|
endcase
|
1179 |
|
|
else
|
1180 |
|
|
begin
|
1181 |
|
|
PE2_in0 <= 0; PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0;
|
1182 |
|
|
PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0;
|
1183 |
|
|
PE2_full_bypass <= 0; PE2_round_value <= 0; PE2_shift_len <= 0;
|
1184 |
|
|
end
|
1185 |
|
|
`Intra16x16_Plane: //---plane---
|
1186 |
|
|
begin
|
1187 |
|
|
if (blk4x4_intra_calculate_counter != 0)
|
1188 |
|
|
//blk0,2,4,6,8,10,12,14,calc counter == 3'b100:PE2_in0 <= seed;
|
1189 |
|
|
//other cases :PE2_in0 <= left pixel output
|
1190 |
|
|
PE2_in0 <= (blk4x4_intra_calculate_counter == 4 && blk4x4_rec_counter[0] == 1'b0)?
|
1191 |
|
|
seed:PE2_out_reg;
|
1192 |
|
|
else
|
1193 |
|
|
PE2_in0 <= 0;
|
1194 |
|
|
if (blk4x4_intra_calculate_counter != 0)
|
1195 |
|
|
//blk0,2,8,10,calc counter == 3'b100:PE2_in1 <= c_ext x 2
|
1196 |
|
|
//other cases :PE2_in1 <= b_ext
|
1197 |
|
|
PE2_in1 <= (blk4x4_intra_calculate_counter == 4 && !blk4x4_rec_counter[2] && !blk4x4_rec_counter[0])?
|
1198 |
|
|
{c_ext[14:0],1'b0}:b_ext;
|
1199 |
|
|
else
|
1200 |
|
|
PE2_in1 <= 0;
|
1201 |
|
|
//blk0,2, 8,10,calc counter == 3'b100:PE2_in2 <= c_ext;
|
1202 |
|
|
//blk4,6,12,14,calc counter == 3'b100:PE2_in2 <= c_ext x 2;
|
1203 |
|
|
//other cases :PE2_in2 <= 0
|
1204 |
|
|
if (blk4x4_intra_calculate_counter == 3'b100 && !blk4x4_rec_counter[0])
|
1205 |
|
|
PE2_in2 <= (blk4x4_rec_counter[2])? {c_ext[14:0],1'b0}:c_ext;
|
1206 |
|
|
else
|
1207 |
|
|
PE2_in2 <= 0;
|
1208 |
|
|
PE2_in3 <= 0;
|
1209 |
|
|
PE2_IsShift <= 1'b0;
|
1210 |
|
|
PE2_IsStore <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0;
|
1211 |
|
|
PE2_IsClip <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0;
|
1212 |
|
|
PE2_full_bypass <= 1'b0;
|
1213 |
|
|
PE2_round_value <= (blk4x4_intra_calculate_counter != 0)? 5'd16:5'd0;
|
1214 |
|
|
PE2_shift_len <= (blk4x4_intra_calculate_counter != 0)? 3'd5 :3'd0;
|
1215 |
|
|
end
|
1216 |
|
|
endcase
|
1217 |
|
|
//Chroma
|
1218 |
|
|
else if (mb_type_general[3] == 1'b1 && blk4x4_rec_counter > 15)
|
1219 |
|
|
case (Intra_chroma_predmode)
|
1220 |
|
|
//--------------------
|
1221 |
|
|
//no PE2 for Chroma DC
|
1222 |
|
|
//2'b00:
|
1223 |
|
|
//--------------------
|
1224 |
|
|
`Intra_chroma_Horizontal: //---horizontal---
|
1225 |
|
|
begin
|
1226 |
|
|
PE2_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window2:0;
|
1227 |
|
|
PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0;
|
1228 |
|
|
PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0;
|
1229 |
|
|
PE2_full_bypass <= 1; PE2_round_value <= 0; PE2_shift_len <= 0;
|
1230 |
|
|
end
|
1231 |
|
|
`Intra_chroma_Vertical: //---vertical---
|
1232 |
|
|
begin
|
1233 |
|
|
case (blk4x4_intra_calculate_counter)
|
1234 |
|
|
4:PE2_in0 <= Intra_mbAddrB_window0;
|
1235 |
|
|
3:PE2_in0 <= Intra_mbAddrB_window1;
|
1236 |
|
|
2:PE2_in0 <= Intra_mbAddrB_window2;
|
1237 |
|
|
1:PE2_in0 <= Intra_mbAddrB_window3;
|
1238 |
|
|
default:PE2_in0 <= 0;
|
1239 |
|
|
endcase
|
1240 |
|
|
PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0;
|
1241 |
|
|
PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0;
|
1242 |
|
|
PE2_full_bypass <= 1; PE2_round_value <= 0; PE2_shift_len <= 0;
|
1243 |
|
|
end
|
1244 |
|
|
`Intra_chroma_Plane: //---plane---
|
1245 |
|
|
begin
|
1246 |
|
|
if (blk4x4_intra_calculate_counter != 0)
|
1247 |
|
|
//need seed, blk4x4 = 16 | 18 | 20 | 22
|
1248 |
|
|
//do not need seed,blk4x4 = 17 | 19 | 21 | 23
|
1249 |
|
|
PE2_in0 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)?
|
1250 |
|
|
seed:PE2_out_reg;
|
1251 |
|
|
else
|
1252 |
|
|
PE2_in0 <= 0;
|
1253 |
|
|
if (blk4x4_intra_calculate_counter != 0)
|
1254 |
|
|
PE2_in1 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)?
|
1255 |
|
|
c_ext:b_ext;
|
1256 |
|
|
else
|
1257 |
|
|
PE2_in1 <= 0;
|
1258 |
|
|
PE2_in2 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)?
|
1259 |
|
|
c_ext:0;
|
1260 |
|
|
PE2_in3 <= 0;
|
1261 |
|
|
PE2_IsShift <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)?
|
1262 |
|
|
1'b1:1'b0;
|
1263 |
|
|
PE2_IsStore <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0;
|
1264 |
|
|
PE2_IsClip <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0;
|
1265 |
|
|
PE2_full_bypass <= 1'b0;
|
1266 |
|
|
PE2_round_value <= (blk4x4_intra_calculate_counter != 0)? 5'd16:5'd0;
|
1267 |
|
|
PE2_shift_len <= (blk4x4_intra_calculate_counter != 0)? 3'd5 :3'd0;
|
1268 |
|
|
end
|
1269 |
|
|
default:
|
1270 |
|
|
begin
|
1271 |
|
|
PE2_in0 <= 0; PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0;
|
1272 |
|
|
PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0;
|
1273 |
|
|
PE2_full_bypass <= 0; PE2_round_value <= 0; PE2_shift_len <= 0;
|
1274 |
|
|
end
|
1275 |
|
|
endcase
|
1276 |
|
|
else
|
1277 |
|
|
begin
|
1278 |
|
|
PE2_in0 <= 0; PE2_in1 <= 0; PE2_in2 <= 0; PE2_in3 <= 0;
|
1279 |
|
|
PE2_IsShift <= 0; PE2_IsStore <= 0; PE2_IsClip <= 0;
|
1280 |
|
|
PE2_full_bypass <= 0; PE2_round_value <= 0; PE2_shift_len <= 0;
|
1281 |
|
|
end
|
1282 |
|
|
|
1283 |
|
|
//----
|
1284 |
|
|
//PE3 |
|
1285 |
|
|
//----
|
1286 |
|
|
always @ (mb_type_general or blk4x4_rec_counter or blk4x4_intra_calculate_counter
|
1287 |
|
|
or Intra4x4_predmode or Intra16x16_predmode or Intra_chroma_predmode
|
1288 |
|
|
or mbAddrA_availability or mbAddrB_availability
|
1289 |
|
|
or Intra_mbAddrA_window0 or Intra_mbAddrA_window1 or Intra_mbAddrA_window2 or Intra_mbAddrA_window3
|
1290 |
|
|
or Intra_mbAddrB_window0 or Intra_mbAddrB_window1 or Intra_mbAddrB_window2 or Intra_mbAddrB_window3
|
1291 |
|
|
or Intra_mbAddrC_window0 or Intra_mbAddrC_window1 or Intra_mbAddrC_window2 or Intra_mbAddrC_window3
|
1292 |
|
|
|
1293 |
|
|
or Intra_mbAddrA_reg12 or Intra_mbAddrA_reg13 or Intra_mbAddrA_reg14 or Intra_mbAddrA_reg15
|
1294 |
|
|
or Intra_mbAddrB_reg13 or Intra_mbAddrB_reg14 or Intra_mbAddrB_reg15
|
1295 |
|
|
or blk4x4_pred_output0 or blk4x4_pred_output4 or blk4x4_pred_output5
|
1296 |
|
|
or blk4x4_pred_output6 or blk4x4_pred_output8 or blk4x4_pred_output9
|
1297 |
|
|
or PE3_out_reg
|
1298 |
|
|
|
1299 |
|
|
or seed or b_ext or c_ext)
|
1300 |
|
|
//Intra 4x4
|
1301 |
|
|
if (mb_type_general[3:2] == 2'b11 && blk4x4_rec_counter < 16)
|
1302 |
|
|
case (Intra4x4_predmode)
|
1303 |
|
|
`Intra4x4_Vertical: //---Vertical---
|
1304 |
|
|
begin
|
1305 |
|
|
case (blk4x4_intra_calculate_counter)
|
1306 |
|
|
4:PE3_in0 <= Intra_mbAddrB_window0;
|
1307 |
|
|
3:PE3_in0 <= Intra_mbAddrB_window1;
|
1308 |
|
|
2:PE3_in0 <= Intra_mbAddrB_window2;
|
1309 |
|
|
1:PE3_in0 <= Intra_mbAddrB_window3;
|
1310 |
|
|
default:PE3_in0 <= 0;
|
1311 |
|
|
endcase
|
1312 |
|
|
PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0;
|
1313 |
|
|
PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0;
|
1314 |
|
|
PE3_full_bypass <= 1; PE3_round_value <= 0; PE3_shift_len <= 0;
|
1315 |
|
|
end
|
1316 |
|
|
`Intra4x4_Horizontal: //---Horizontal---
|
1317 |
|
|
begin
|
1318 |
|
|
PE3_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window3:0;
|
1319 |
|
|
PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0;
|
1320 |
|
|
PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0;
|
1321 |
|
|
PE3_full_bypass <= 1; PE3_round_value <= 0; PE3_shift_len <= 0;
|
1322 |
|
|
end
|
1323 |
|
|
//-------------
|
1324 |
|
|
//no PE2 for DC
|
1325 |
|
|
//4'b0010:
|
1326 |
|
|
//-------------
|
1327 |
|
|
`Intra4x4_Diagonal_Down_Left: //---diagonal down-left---
|
1328 |
|
|
begin
|
1329 |
|
|
case (blk4x4_intra_calculate_counter)
|
1330 |
|
|
4:begin PE3_in0 <= Intra_mbAddrB_window3; PE3_in1 <= Intra_mbAddrC_window1;
|
1331 |
|
|
PE3_in2 <= Intra_mbAddrC_window0; end
|
1332 |
|
|
3:begin PE3_in0 <= Intra_mbAddrC_window0; PE3_in1 <= Intra_mbAddrC_window2;
|
1333 |
|
|
PE3_in2 <= Intra_mbAddrC_window1; end
|
1334 |
|
|
2:begin PE3_in0 <= Intra_mbAddrC_window1; PE3_in1 <= Intra_mbAddrC_window3;
|
1335 |
|
|
PE3_in2 <= Intra_mbAddrC_window2; end
|
1336 |
|
|
1:begin PE3_in0 <= Intra_mbAddrC_window2; PE3_in1 <= Intra_mbAddrC_window3;
|
1337 |
|
|
PE3_in2 <= Intra_mbAddrC_window3; end
|
1338 |
|
|
default:begin PE3_in0 <= 0;PE3_in1 <= 0;PE3_in2 <= 0; end
|
1339 |
|
|
endcase
|
1340 |
|
|
PE3_in3 <= 0;
|
1341 |
|
|
PE3_IsShift <= (blk4x4_intra_calculate_counter == 0)? 1'b0:1'b1;
|
1342 |
|
|
PE3_IsStore <= 1'b0; PE3_IsClip <= 1'b0; PE3_full_bypass <= 1'b0;
|
1343 |
|
|
PE3_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'd0:5'd2; // +2
|
1344 |
|
|
PE3_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'd0:3'd2; // >>2
|
1345 |
|
|
end
|
1346 |
|
|
`Intra4x4_Diagonal_Down_Right: //---diagonal down-right---
|
1347 |
|
|
begin
|
1348 |
|
|
case (blk4x4_intra_calculate_counter)
|
1349 |
|
|
4:PE3_in0 <= Intra_mbAddrA_window1;
|
1350 |
|
|
3:PE3_in0 <= blk4x4_pred_output8;
|
1351 |
|
|
2:PE3_in0 <= blk4x4_pred_output4;
|
1352 |
|
|
1:PE3_in0 <= blk4x4_pred_output0;
|
1353 |
|
|
default:PE3_in0 <= 0;
|
1354 |
|
|
endcase
|
1355 |
|
|
PE3_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window3:0;
|
1356 |
|
|
PE3_in2 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window2:0;
|
1357 |
|
|
PE3_in3 <= 0;
|
1358 |
|
|
PE3_IsShift <= (blk4x4_intra_calculate_counter == 0)? 1'b0:1'b1;
|
1359 |
|
|
PE3_IsStore <= 1'b0; PE3_IsClip <= 1'b0;
|
1360 |
|
|
PE3_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1;
|
1361 |
|
|
PE3_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'd0:5'd2; // +2
|
1362 |
|
|
PE3_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'd0:3'd2; // >>2
|
1363 |
|
|
end
|
1364 |
|
|
`Intra4x4_Vertical_Right: //---vertical right---
|
1365 |
|
|
begin
|
1366 |
|
|
case (blk4x4_intra_calculate_counter)
|
1367 |
|
|
4:PE3_in0 <= Intra_mbAddrA_window0;
|
1368 |
|
|
3:PE3_in0 <= blk4x4_pred_output4;
|
1369 |
|
|
2:PE3_in0 <= blk4x4_pred_output5;
|
1370 |
|
|
1:PE3_in0 <= blk4x4_pred_output6;
|
1371 |
|
|
default:PE3_in0 <= 0;
|
1372 |
|
|
endcase
|
1373 |
|
|
PE3_in1 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window2:0;
|
1374 |
|
|
PE3_in2 <= (blk4x4_intra_calculate_counter == 4)? Intra_mbAddrA_window1:0;
|
1375 |
|
|
PE3_in3 <= 0;
|
1376 |
|
|
PE3_IsShift <= (blk4x4_intra_calculate_counter == 0)? 1'b0:1'b1;
|
1377 |
|
|
PE3_IsStore <= 1'b0; PE3_IsClip <= 1'b0;
|
1378 |
|
|
PE3_full_bypass <= (blk4x4_intra_calculate_counter == 4)? 1'b0:1'b1;
|
1379 |
|
|
PE3_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'd0:5'd2; // +2
|
1380 |
|
|
PE3_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'd0:3'd2; // >>2
|
1381 |
|
|
end
|
1382 |
|
|
`Intra4x4_Horizontal_Down: //---horizontal down---
|
1383 |
|
|
begin
|
1384 |
|
|
case (blk4x4_intra_calculate_counter)
|
1385 |
|
|
4:PE3_in0 <= Intra_mbAddrA_window2;
|
1386 |
|
|
3:PE3_in0 <= Intra_mbAddrA_window1;
|
1387 |
|
|
2:PE3_in0 <= blk4x4_pred_output8;
|
1388 |
|
|
1:PE3_in0 <= blk4x4_pred_output9;
|
1389 |
|
|
default:PE3_in0 <= 0;
|
1390 |
|
|
endcase
|
1391 |
|
|
PE3_in1 <= (blk4x4_intra_calculate_counter == 4 || blk4x4_intra_calculate_counter == 3)?
|
1392 |
|
|
Intra_mbAddrA_window3:0;
|
1393 |
|
|
PE3_in2 <= (blk4x4_intra_calculate_counter == 3)? Intra_mbAddrA_window2:0;
|
1394 |
|
|
PE3_in3 <= 0;
|
1395 |
|
|
PE3_IsShift <= (blk4x4_intra_calculate_counter == 3)? 1'b1:1'b0;
|
1396 |
|
|
PE3_IsStore <= 1'b0; PE3_IsClip <= 1'b0;
|
1397 |
|
|
PE3_full_bypass <= (blk4x4_intra_calculate_counter == 2 ||
|
1398 |
|
|
blk4x4_intra_calculate_counter == 1)? 1'b1:1'b0;
|
1399 |
|
|
PE3_round_value <= (blk4x4_intra_calculate_counter == 4)? 5'd1:
|
1400 |
|
|
(blk4x4_intra_calculate_counter == 3)? 5'd2:5'd0;
|
1401 |
|
|
PE3_shift_len <= (blk4x4_intra_calculate_counter == 4)? 3'd1:
|
1402 |
|
|
(blk4x4_intra_calculate_counter == 3)? 3'd2:3'd0;
|
1403 |
|
|
end
|
1404 |
|
|
`Intra4x4_Vertical_Left: //---vertical left---
|
1405 |
|
|
begin
|
1406 |
|
|
case (blk4x4_intra_calculate_counter)
|
1407 |
|
|
4:begin PE3_in0 <= Intra_mbAddrB_window1; PE3_in1 <= Intra_mbAddrB_window3;
|
1408 |
|
|
PE3_in2 <= Intra_mbAddrB_window2; end
|
1409 |
|
|
3:begin PE3_in0 <= Intra_mbAddrB_window2; PE3_in1 <= Intra_mbAddrC_window0;
|
1410 |
|
|
PE3_in2 <= Intra_mbAddrB_window3; end
|
1411 |
|
|
2:begin PE3_in0 <= Intra_mbAddrB_window3; PE3_in1 <= Intra_mbAddrC_window1;
|
1412 |
|
|
PE3_in2 <= Intra_mbAddrC_window0; end
|
1413 |
|
|
1:begin PE3_in0 <= Intra_mbAddrC_window0; PE3_in1 <= Intra_mbAddrC_window2;
|
1414 |
|
|
PE3_in2 <= Intra_mbAddrC_window1; end
|
1415 |
|
|
default:begin PE3_in0 <= 0;PE3_in1 <= 0;PE3_in2 <= 0; end
|
1416 |
|
|
endcase
|
1417 |
|
|
PE3_in3 <= 0;
|
1418 |
|
|
PE3_IsShift <= (blk4x4_intra_calculate_counter == 0)? 1'b0:1'b1;
|
1419 |
|
|
PE3_IsStore <= 1'b0; PE3_IsClip <= 1'b0; PE3_full_bypass <= 1'b0;
|
1420 |
|
|
PE3_round_value <= (blk4x4_intra_calculate_counter == 0)? 5'd0:5'd2; // +2
|
1421 |
|
|
PE3_shift_len <= (blk4x4_intra_calculate_counter == 0)? 3'd0:3'd2; // >>2
|
1422 |
|
|
end
|
1423 |
|
|
`Intra4x4_Horizontal_Up: //---horizontal up---
|
1424 |
|
|
begin
|
1425 |
|
|
PE3_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window3:0;
|
1426 |
|
|
PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0;
|
1427 |
|
|
PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0;
|
1428 |
|
|
PE3_full_bypass <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0;
|
1429 |
|
|
PE3_round_value <= 0; PE3_shift_len <= 0;
|
1430 |
|
|
end
|
1431 |
|
|
default:
|
1432 |
|
|
begin
|
1433 |
|
|
PE3_in0 <= 0; PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0;
|
1434 |
|
|
PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0;
|
1435 |
|
|
PE3_full_bypass <= 0; PE3_round_value <= 0; PE3_shift_len <= 0;
|
1436 |
|
|
end
|
1437 |
|
|
endcase
|
1438 |
|
|
//Intra16x16
|
1439 |
|
|
else if (mb_type_general[3:2] == 2'b10 && blk4x4_rec_counter < 16)
|
1440 |
|
|
case (Intra16x16_predmode)
|
1441 |
|
|
`Intra16x16_Vertical: //---Vertical---
|
1442 |
|
|
begin
|
1443 |
|
|
case (blk4x4_intra_calculate_counter)
|
1444 |
|
|
4:PE3_in0 <= Intra_mbAddrB_window0;
|
1445 |
|
|
3:PE3_in0 <= Intra_mbAddrB_window1;
|
1446 |
|
|
2:PE3_in0 <= Intra_mbAddrB_window2;
|
1447 |
|
|
1:PE3_in0 <= Intra_mbAddrB_window3;
|
1448 |
|
|
default:PE3_in0 <= 0;
|
1449 |
|
|
endcase
|
1450 |
|
|
PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0;
|
1451 |
|
|
PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0;
|
1452 |
|
|
PE3_full_bypass <= 1; PE3_round_value <= 0; PE3_shift_len <= 0;
|
1453 |
|
|
end
|
1454 |
|
|
`Intra16x16_Horizontal: //---Horizontal---
|
1455 |
|
|
begin
|
1456 |
|
|
PE3_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window3:0;
|
1457 |
|
|
PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0;
|
1458 |
|
|
PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0;
|
1459 |
|
|
PE3_full_bypass <= 1; PE3_round_value <= 0; PE3_shift_len <= 0;
|
1460 |
|
|
end
|
1461 |
|
|
`Intra16x16_DC: //---DC---
|
1462 |
|
|
if (blk4x4_rec_counter == 0)
|
1463 |
|
|
case (blk4x4_intra_calculate_counter)
|
1464 |
|
|
4:begin // M2 + N2 + O2 + P2
|
1465 |
|
|
PE3_in0 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg12;
|
1466 |
|
|
PE3_in1 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg13;
|
1467 |
|
|
PE3_in2 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg14;
|
1468 |
|
|
PE3_in3 <= (mbAddrA_availability == 0)? 0:Intra_mbAddrA_reg15;
|
1469 |
|
|
PE3_IsShift <= 0; PE3_IsStore <= 1; PE3_IsClip <= 0;
|
1470 |
|
|
PE3_full_bypass <= 0; PE3_round_value <= 0; PE3_shift_len <= 0; end
|
1471 |
|
|
3:begin // PE3 output + N1 + O1 + P1
|
1472 |
|
|
PE3_in0 <= PE3_out_reg;
|
1473 |
|
|
PE3_in1 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg13;
|
1474 |
|
|
PE3_in2 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg14;
|
1475 |
|
|
PE3_in3 <= (mbAddrB_availability == 0)? 0:Intra_mbAddrB_reg15;
|
1476 |
|
|
PE3_IsShift <= 0; PE3_IsStore <= 1; PE3_IsClip <= 0;
|
1477 |
|
|
PE3_full_bypass <= 0; PE3_round_value <= 0; PE3_shift_len <= 0; end
|
1478 |
|
|
default:begin
|
1479 |
|
|
PE3_in0 <= 0; PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0;
|
1480 |
|
|
PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0;
|
1481 |
|
|
PE3_full_bypass <= 0; PE3_round_value <= 0; PE3_shift_len <= 0; end
|
1482 |
|
|
endcase
|
1483 |
|
|
else
|
1484 |
|
|
begin
|
1485 |
|
|
PE3_in0 <= 0; PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0;
|
1486 |
|
|
PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0;
|
1487 |
|
|
PE3_full_bypass <= 0; PE3_round_value <= 0; PE3_shift_len <= 0;
|
1488 |
|
|
end
|
1489 |
|
|
`Intra16x16_Plane: //---plane---
|
1490 |
|
|
begin
|
1491 |
|
|
if (blk4x4_intra_calculate_counter != 0)
|
1492 |
|
|
//blk0,2,4,6,8,10,12,14,calc counter == 3'b100:PE3_in0 <= seed;
|
1493 |
|
|
//other cases :PE3_in0 <= left pixel output
|
1494 |
|
|
PE3_in0 <= (blk4x4_intra_calculate_counter == 4 && blk4x4_rec_counter[0] == 1'b0)?
|
1495 |
|
|
seed:PE3_out_reg;
|
1496 |
|
|
else
|
1497 |
|
|
PE3_in0 <= 0;
|
1498 |
|
|
if (blk4x4_intra_calculate_counter != 0)
|
1499 |
|
|
//blk0,2,8,10,calc counter == 3'b100:PE3_in1 <= c_ext x 4
|
1500 |
|
|
//other cases :PE3_in1 <= b_ext
|
1501 |
|
|
PE3_in1 <= (blk4x4_intra_calculate_counter == 4 && !blk4x4_rec_counter[2] && !blk4x4_rec_counter[0])?
|
1502 |
|
|
{c_ext[13:0],2'b0}:b_ext;
|
1503 |
|
|
else
|
1504 |
|
|
PE3_in1 <= 0;
|
1505 |
|
|
//blk4,6,12,14,calc counter == 3'b100:PE3_in2 <= c_ext x 2;
|
1506 |
|
|
//other cases :PE3_in2 <= 0
|
1507 |
|
|
PE3_in2 <= (blk4x4_intra_calculate_counter == 3'b100 && blk4x4_rec_counter[2] && !blk4x4_rec_counter[0])?
|
1508 |
|
|
{c_ext[14:0],1'b0}:0;
|
1509 |
|
|
//blk4,6,12,14,calc counter == 3'b100:PE3_in3 <= c_ext;
|
1510 |
|
|
//other cases :PE3_in3 <= 0
|
1511 |
|
|
PE3_in3 <= (blk4x4_intra_calculate_counter == 3'b100 && blk4x4_rec_counter[2] && !blk4x4_rec_counter[0])?
|
1512 |
|
|
c_ext:0;
|
1513 |
|
|
PE3_IsShift <= 1'b0;
|
1514 |
|
|
PE3_IsStore <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0;
|
1515 |
|
|
PE3_IsClip <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0;
|
1516 |
|
|
PE3_full_bypass <= 1'b0;
|
1517 |
|
|
PE3_round_value <= (blk4x4_intra_calculate_counter != 0)? 5'd16:5'd0;
|
1518 |
|
|
PE3_shift_len <= (blk4x4_intra_calculate_counter != 0)? 3'd5 :3'd0;
|
1519 |
|
|
end
|
1520 |
|
|
endcase
|
1521 |
|
|
//Chroma
|
1522 |
|
|
else if (mb_type_general[3] == 1'b1 && blk4x4_rec_counter > 15)
|
1523 |
|
|
case (Intra_chroma_predmode)
|
1524 |
|
|
//--------------------
|
1525 |
|
|
//no PE2 for Chroma DC
|
1526 |
|
|
//2'b00:
|
1527 |
|
|
//--------------------
|
1528 |
|
|
`Intra_chroma_Horizontal: //---horizontal---
|
1529 |
|
|
begin
|
1530 |
|
|
PE3_in0 <= (blk4x4_intra_calculate_counter != 0)? Intra_mbAddrA_window3:0;
|
1531 |
|
|
PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0;
|
1532 |
|
|
PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0;
|
1533 |
|
|
PE3_full_bypass <= 1; PE3_round_value <= 0; PE3_shift_len <= 0;
|
1534 |
|
|
end
|
1535 |
|
|
`Intra_chroma_Vertical: //---vertical---
|
1536 |
|
|
begin
|
1537 |
|
|
case (blk4x4_intra_calculate_counter)
|
1538 |
|
|
4:PE3_in0 <= Intra_mbAddrB_window0;
|
1539 |
|
|
3:PE3_in0 <= Intra_mbAddrB_window1;
|
1540 |
|
|
2:PE3_in0 <= Intra_mbAddrB_window2;
|
1541 |
|
|
1:PE3_in0 <= Intra_mbAddrB_window3;
|
1542 |
|
|
default:PE3_in0 <= 0;
|
1543 |
|
|
endcase
|
1544 |
|
|
PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0;
|
1545 |
|
|
PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0;
|
1546 |
|
|
PE3_full_bypass <= 1; PE3_round_value <= 0; PE3_shift_len <= 0;
|
1547 |
|
|
end
|
1548 |
|
|
`Intra_chroma_Plane: //---plane---
|
1549 |
|
|
begin
|
1550 |
|
|
if (blk4x4_intra_calculate_counter != 0)
|
1551 |
|
|
//need seed, blk4x4 = 16 | 18 | 20 | 22
|
1552 |
|
|
//do not need seed,blk4x4 = 17 | 19 | 21 | 23
|
1553 |
|
|
PE3_in0 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)?
|
1554 |
|
|
seed:PE3_out_reg;
|
1555 |
|
|
else
|
1556 |
|
|
PE3_in0 <= 0;
|
1557 |
|
|
if (blk4x4_intra_calculate_counter != 0)
|
1558 |
|
|
PE3_in1 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)?
|
1559 |
|
|
{c_ext[14:0],1'b0}:b_ext;
|
1560 |
|
|
else
|
1561 |
|
|
PE3_in1 <= 0;
|
1562 |
|
|
PE3_in2 <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)?
|
1563 |
|
|
c_ext:0;
|
1564 |
|
|
PE3_in3 <= 0;
|
1565 |
|
|
PE3_IsShift <= (blk4x4_rec_counter[0] == 1'b0 && blk4x4_intra_calculate_counter == 4)?
|
1566 |
|
|
1'b1:1'b0;
|
1567 |
|
|
PE3_IsStore <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0;
|
1568 |
|
|
PE3_IsClip <= (blk4x4_intra_calculate_counter != 0)? 1'b1:1'b0;
|
1569 |
|
|
PE3_full_bypass <= 1'b0;
|
1570 |
|
|
PE3_round_value <= (blk4x4_intra_calculate_counter != 0)? 5'd16:5'd0;
|
1571 |
|
|
PE3_shift_len <= (blk4x4_intra_calculate_counter != 0)? 3'd5 :3'd0;
|
1572 |
|
|
end
|
1573 |
|
|
default:
|
1574 |
|
|
begin
|
1575 |
|
|
PE3_in0 <= 0; PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0;
|
1576 |
|
|
PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0;
|
1577 |
|
|
PE3_full_bypass <= 0; PE3_round_value <= 0; PE3_shift_len <= 0;
|
1578 |
|
|
end
|
1579 |
|
|
endcase
|
1580 |
|
|
else
|
1581 |
|
|
begin
|
1582 |
|
|
PE3_in0 <= 0; PE3_in1 <= 0; PE3_in2 <= 0; PE3_in3 <= 0;
|
1583 |
|
|
PE3_IsShift <= 0; PE3_IsStore <= 0; PE3_IsClip <= 0;
|
1584 |
|
|
PE3_full_bypass <= 0; PE3_round_value <= 0; PE3_shift_len <= 0;
|
1585 |
|
|
end
|
1586 |
|
|
endmodule
|
1587 |
|
|
|
1588 |
|
|
module PE (clk,reset_n,in0,in1,in2,in3,IsShift,IsStore,IsClip,full_bypass,round_value,shift_len,
|
1589 |
|
|
PE_out_reg,PE_out,sum_out);
|
1590 |
|
|
input clk,reset_n;
|
1591 |
|
|
input [15:0] in0,in1,in2,in3;
|
1592 |
|
|
input IsShift;
|
1593 |
|
|
input IsStore;
|
1594 |
|
|
input IsClip;
|
1595 |
|
|
input full_bypass;
|
1596 |
|
|
input [4:0] round_value;
|
1597 |
|
|
input [2:0] shift_len;
|
1598 |
|
|
|
1599 |
|
|
|
1600 |
|
|
output [15:0] PE_out_reg;
|
1601 |
|
|
output [7:0] PE_out;
|
1602 |
|
|
output [15:0] sum_out;
|
1603 |
|
|
reg [15:0] PE_out_reg;
|
1604 |
|
|
|
1605 |
|
|
wire [15:0] sum1;
|
1606 |
|
|
wire [15:0] sum2;
|
1607 |
|
|
wire [16:0] round_tmp;
|
1608 |
|
|
wire [15:0] round_out;
|
1609 |
|
|
wire [7:0] clip_out;
|
1610 |
|
|
|
1611 |
|
|
assign sum1 = (full_bypass)? 0:(in0 + in1);
|
1612 |
|
|
assign sum2 = (full_bypass)? 0:((IsShift)? {in2[14:0],1'b0}:(in2 + in3));
|
1613 |
|
|
assign sum_out = (full_bypass)? 0:(sum1 + sum2);
|
1614 |
|
|
|
1615 |
|
|
always @ (posedge clk)
|
1616 |
|
|
if (reset_n == 1'b0)
|
1617 |
|
|
PE_out_reg <= 0;
|
1618 |
|
|
else if (IsStore)
|
1619 |
|
|
PE_out_reg <= sum_out;
|
1620 |
|
|
|
1621 |
|
|
assign round_tmp = sum_out + round_value;
|
1622 |
|
|
assign round_out = round_tmp >> shift_len;
|
1623 |
|
|
assign clip_out = (IsClip)? ((round_out[15] == 1'b1)? 8'd0:((round_out[15:8] == 0)? round_out[7:0]:8'd255))
|
1624 |
|
|
:round_out[7:0];
|
1625 |
|
|
assign PE_out = (full_bypass)? in0[7:0]:clip_out;
|
1626 |
|
|
endmodule
|